Firmware for MNT ZZ9000 graphics and ARM coprocessor card for Amiga computers.
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main.c 55KB

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  1. /*
  2. * MNT ZZ9000 Amiga Graphics and Coprocessor Card Operating System (ZZ9000OS)
  3. *
  4. * Copyright (C) 2019, Lukas F. Hartmann <lukas@mntre.com>
  5. * MNT Research GmbH, Berlin
  6. * https://mntre.com
  7. *
  8. * More Info: https://mntre.com/zz9000
  9. *
  10. * SPDX-License-Identifier: GPL-3.0-or-later
  11. * GNU General Public License v3.0 or later
  12. *
  13. * https://spdx.org/licenses/GPL-3.0-or-later.html
  14. *
  15. */
  16. #include <stdio.h>
  17. #include <string.h>
  18. #include <malloc.h>
  19. #include <math.h>
  20. #include "platform.h"
  21. #include "xil_printf.h"
  22. #include "xparameters.h"
  23. #include "xil_io.h"
  24. #include "xiicps.h"
  25. #include "sleep.h"
  26. #include "xaxivdma.h"
  27. #include "xil_cache.h"
  28. #include "xclk_wiz.h"
  29. #include "xil_exception.h"
  30. #include "gfx.h"
  31. #include "ethernet.h"
  32. #include "usb.h"
  33. #include "xgpiops.h"
  34. #include "xil_misc_psreset_api.h"
  35. typedef u8 uint8_t;
  36. #define A9_CPU_RST_CTRL (XSLCR_BASEADDR + 0x244)
  37. #define A9_RST1_MASK 0x00000002
  38. #define A9_CLKSTOP1_MASK 0x00000020
  39. #define XSLCR_LOCK_ADDR (XSLCR_BASEADDR + 0x4)
  40. #define XSLCR_LOCK_CODE 0x0000767B
  41. #define IIC_DEVICE_ID XPAR_XIICPS_0_DEVICE_ID
  42. #define VDMA_DEVICE_ID XPAR_AXIVDMA_0_DEVICE_ID
  43. #define HDMI_I2C_ADDR 0x3b
  44. #define IIC_SCLK_RATE 400000
  45. #define GPIO_DEVICE_ID XPAR_XGPIOPS_0_DEVICE_ID
  46. #define I2C_PAUSE 10
  47. // I2C controller instance
  48. XIicPs Iic;
  49. int hdmi_ctrl_write_byte(u8 addr, u8 value) {
  50. u8 buffer[2];
  51. buffer[0] = addr;
  52. buffer[1] = value;
  53. int status;
  54. while (XIicPs_BusIsBusy(&Iic)) {
  55. };
  56. usleep(I2C_PAUSE);
  57. status = XIicPs_MasterSendPolled(&Iic, buffer, 1, HDMI_I2C_ADDR);
  58. while (XIicPs_BusIsBusy(&Iic)) {
  59. };
  60. usleep(I2C_PAUSE);
  61. buffer[1] = 0xff;
  62. status = XIicPs_MasterRecvPolled(&Iic, buffer + 1, 1, HDMI_I2C_ADDR);
  63. //printf("[hdmi] old value of 0x%0x: 0x%0x\n",addr,buffer[1]);
  64. buffer[1] = value;
  65. while (XIicPs_BusIsBusy(&Iic)) {
  66. };
  67. status = XIicPs_MasterSendPolled(&Iic, buffer, 2, HDMI_I2C_ADDR);
  68. while (XIicPs_BusIsBusy(&Iic)) {
  69. };
  70. usleep(I2C_PAUSE);
  71. status = XIicPs_MasterSendPolled(&Iic, buffer, 1, HDMI_I2C_ADDR);
  72. while (XIicPs_BusIsBusy(&Iic)) {
  73. };
  74. usleep(I2C_PAUSE);
  75. buffer[1] = 0xff;
  76. status = XIicPs_MasterRecvPolled(&Iic, buffer + 1, 1, HDMI_I2C_ADDR);
  77. if (buffer[1] != value) {
  78. printf("[hdmi] new value of 0x%x: 0x%x (should be 0x%x)\n", addr,
  79. buffer[1], value);
  80. }
  81. return status;
  82. }
  83. int hdmi_ctrl_read_byte(u8 addr, u8* buffer) {
  84. buffer[0] = addr;
  85. buffer[1] = 0xff;
  86. while (XIicPs_BusIsBusy(&Iic)) {
  87. };
  88. int status = XIicPs_MasterSendPolled(&Iic, buffer, 1, HDMI_I2C_ADDR);
  89. while (XIicPs_BusIsBusy(&Iic)) {
  90. };
  91. usleep(I2C_PAUSE);
  92. status = XIicPs_MasterRecvPolled(&Iic, buffer + 1, 1, HDMI_I2C_ADDR);
  93. return status;
  94. }
  95. static u8 sii9022_init[] = {
  96. 0x1e, 0x00,// TPI Device Power State Control Data (R/W)
  97. 0x09, 0x00, //
  98. 0x0a, 0x00,
  99. 0x60, 0x04, 0x3c, 0x01, // TPI Interrupt Enable (R/W)
  100. 0x1a, 0x10, // TPI System Control (R/W)
  101. 0x00, 0x4c, // PixelClock/10000 - LSB u16:6
  102. 0x01, 0x1d, // PixelClock/10000 - MSB
  103. 0x02, 0x70, // Frequency in HZ - LSB
  104. 0x03, 0x17, // Vertical Frequency in HZ - MSB
  105. 0x04, 0x70, // Total Pixels per line - LSB
  106. 0x05, 0x06, // Total Pixels per line - MSB
  107. 0x06, 0xEE, // Total Lines - LSB
  108. 0x07, 0x02, // Total Lines - MSB
  109. 0x08, 0x70, // pixel repeat rate?
  110. 0x1a, 0x00, // CTRL_DATA - bit 1 causes 2 purple extra columns on DVI monitors (probably HDMI mode)
  111. };
  112. void disable_reset_out() {
  113. XGpioPs Gpio;
  114. XGpioPs_Config *ConfigPtr;
  115. ConfigPtr = XGpioPs_LookupConfig(GPIO_DEVICE_ID);
  116. XGpioPs_CfgInitialize(&Gpio, ConfigPtr, ConfigPtr->BaseAddr);
  117. int output_pin = 7;
  118. XGpioPs_SetDirectionPin(&Gpio, output_pin, 1);
  119. XGpioPs_SetOutputEnablePin(&Gpio, output_pin, 1);
  120. XGpioPs_WritePin(&Gpio, output_pin, 0);
  121. usleep(10000);
  122. XGpioPs_WritePin(&Gpio, output_pin, 1);
  123. print("GPIO reset disable done.\n\r");
  124. }
  125. void hdmi_ctrl_init() {
  126. int status;
  127. XIicPs_Config *config;
  128. config = XIicPs_LookupConfig(IIC_DEVICE_ID);
  129. status = XIicPs_CfgInitialize(&Iic, config, config->BaseAddress);
  130. //printf("XIicPs_CfgInitialize: %d\n", status);
  131. usleep(10000);
  132. //printf("XIicPs is ready: %lx\n", Iic.IsReady);
  133. status = XIicPs_SelfTest(&Iic);
  134. //printf("XIicPs_SelfTest: %x\n", status);
  135. status = XIicPs_SetSClk(&Iic, IIC_SCLK_RATE);
  136. //printf("XIicPs_SetSClk: %x\n", status);
  137. usleep(2500);
  138. // reset
  139. status = hdmi_ctrl_write_byte(0xc7, 0);
  140. u8 buffer[2];
  141. status = hdmi_ctrl_read_byte(0x1b, buffer);
  142. printf("[%d] TPI device id: 0x%x\n", status, buffer[1]);
  143. status = hdmi_ctrl_read_byte(0x1c, buffer);
  144. //printf("[%d] TPI revision 1: 0x%x\n",status,buffer[1]);
  145. //status = hdmi_ctrl_read_byte(0x1d,buffer);
  146. //printf("[%d] TPI revision 2: 0x%x\n",status,buffer[1]);
  147. //status = hdmi_ctrl_read_byte(0x30,buffer);
  148. //printf("[%d] HDCP revision: 0x%x\n",status,buffer[1]);
  149. //status = hdmi_ctrl_read_byte(0x3d,buffer);
  150. printf("[%d] hotplug: 0x%x\n", status, buffer[1]);
  151. for (int i = 0; i < sizeof(sii9022_init); i += 2) {
  152. status = hdmi_ctrl_write_byte(sii9022_init[i], sii9022_init[i + 1]);
  153. usleep(1);
  154. }
  155. }
  156. XAxiVdma vdma;
  157. static u32* framebuffer = 0;
  158. static u32 framebuffer_pan_offset = 0;
  159. static u32 blitter_dst_offset = 0;
  160. static u32 blitter_src_offset = 0;
  161. static u32 vmode_hsize = 800, vmode_vsize = 600, vmode_hdiv = 1, vmode_vdiv = 2;
  162. // 32bit: hdiv=1, 16bit: hdiv=2, 8bit: hdiv=4, ...
  163. int init_vdma(int hsize, int vsize, int hdiv, int vdiv) {
  164. int status;
  165. XAxiVdma_Config *Config;
  166. Config = XAxiVdma_LookupConfig(VDMA_DEVICE_ID);
  167. if (!Config) {
  168. printf("VDMA not found for ID %d\r\n", VDMA_DEVICE_ID);
  169. return XST_FAILURE;
  170. }
  171. /*XAxiVdma_DmaStop(&vdma, XAXIVDMA_READ);
  172. XAxiVdma_Reset(&vdma, XAXIVDMA_READ);
  173. XAxiVdma_ClearDmaChannelErrors(&vdma, XAXIVDMA_READ, XAXIVDMA_SR_ERR_ALL_MASK);*/
  174. status = XAxiVdma_CfgInitialize(&vdma, Config, Config->BaseAddress);
  175. if (status != XST_SUCCESS) {
  176. printf("VDMA Configuration Initialization failed, status: 0x%X\r\n",
  177. status);
  178. //return status;
  179. }
  180. u32 stride = hsize * (Config->Mm2SStreamWidth >> 3);
  181. XAxiVdma_DmaSetup ReadCfg;
  182. //printf("VDMA HDIV: %d VDIV: %d\n", hdiv, vdiv);
  183. ReadCfg.VertSizeInput = vsize / vdiv;
  184. ReadCfg.HoriSizeInput = stride / hdiv; // note: changing this breaks the output
  185. ReadCfg.Stride = stride / hdiv; // note: changing this is not a problem
  186. ReadCfg.FrameDelay = 0; /* This example does not test frame delay */
  187. ReadCfg.EnableCircularBuf = 1; /* Only 1 buffer, continuous loop */
  188. ReadCfg.EnableSync = 0; /* Gen-Lock */
  189. ReadCfg.PointNum = 0;
  190. ReadCfg.EnableFrameCounter = 0; /* Endless transfers */
  191. ReadCfg.FixedFrameStoreAddr = 0; /* We are not doing parking */
  192. ReadCfg.FrameStoreStartAddr[0] = (u32) framebuffer + framebuffer_pan_offset;
  193. //printf("VDMA Framebuffer at 0x%x\n", ReadCfg.FrameStoreStartAddr[0]);
  194. status = XAxiVdma_DmaConfig(&vdma, XAXIVDMA_READ, &ReadCfg);
  195. if (status != XST_SUCCESS) {
  196. printf("VDMA Read channel config failed, status: 0x%X\r\n", status);
  197. return status;
  198. }
  199. status = XAxiVdma_DmaSetBufferAddr(&vdma, XAXIVDMA_READ, ReadCfg.FrameStoreStartAddr);
  200. if (status != XST_SUCCESS) {
  201. printf("VDMA Read channel set buffer address failed, status: 0x%X\r\n", status);
  202. return status;
  203. }
  204. status = XAxiVdma_DmaStart(&vdma, XAXIVDMA_READ);
  205. if (status != XST_SUCCESS) {
  206. printf("VDMA Failed to start DMA engine (read channel), status: 0x%X\r\n", status);
  207. return status;
  208. }
  209. return XST_SUCCESS;
  210. }
  211. void hdmi_set_video_mode(u16 htotal, u16 vtotal, u32 pixelclock_hz, u16 vhz, u8 hdmi) {
  212. /*
  213. * SII9022 registers
  214. *
  215. 0x00, 0x4c, // PixelClock/10000 - LSB
  216. 0x01, 0x1d, // PixelClock/10000 - MSB
  217. 0x02, 0x70, // Frequency in HZ - LSB
  218. 0x03, 0x17, // Vertical Frequency in HZ - MSB
  219. 0x04, 0x70, // Total Pixels per line - LSB
  220. 0x05, 0x06, // Total Pixels per line - MSB
  221. 0x06, 0xEE, // Total Lines - LSB
  222. 0x07, 0x02, // Total Lines - MSB
  223. 0x08, 0x70, // pixel repeat rate?
  224. 0x1a, 0x00, // 0: DVI, 1: HDMI
  225. */
  226. // see also https://github.com/torvalds/linux/blob/master/drivers/gpu/drm/bridge/sii902x.c#L358
  227. u8* sii_mode = sii9022_init + 12;
  228. sii_mode[2 * 0 + 1] = pixelclock_hz / 10000;
  229. sii_mode[2 * 1 + 1] = (pixelclock_hz / 10000) >> 8;
  230. sii_mode[2 * 2 + 1] = vhz * 100;
  231. sii_mode[2 * 3 + 1] = (vhz * 100) >> 8;
  232. sii_mode[2 * 4 + 1] = htotal;
  233. sii_mode[2 * 5 + 1] = htotal >> 8;
  234. sii_mode[2 * 6 + 1] = vtotal;
  235. sii_mode[2 * 7 + 1] = vtotal >> 8;
  236. sii_mode[2 * 9 + 1] = hdmi;
  237. }
  238. u32 dump_vdma_status(XAxiVdma *InstancePtr) {
  239. u32 status = XAxiVdma_GetStatus(InstancePtr, XAXIVDMA_READ);
  240. xil_printf("Read channel dump\n\r");
  241. xil_printf("\tMM2S DMA Control Register: %x\r\n",
  242. XAxiVdma_ReadReg(InstancePtr->ReadChannel.ChanBase,
  243. XAXIVDMA_CR_OFFSET));
  244. xil_printf("\tMM2S DMA Status Register: %x\r\n",
  245. XAxiVdma_ReadReg(InstancePtr->ReadChannel.ChanBase,
  246. XAXIVDMA_SR_OFFSET));
  247. xil_printf("\tMM2S HI_FRMBUF Reg: %x\r\n",
  248. XAxiVdma_ReadReg(InstancePtr->ReadChannel.ChanBase,
  249. XAXIVDMA_HI_FRMBUF_OFFSET));
  250. xil_printf("\tFRMSTORE Reg: %d\r\n",
  251. XAxiVdma_ReadReg(InstancePtr->ReadChannel.ChanBase,
  252. XAXIVDMA_FRMSTORE_OFFSET));
  253. xil_printf("\tBUFTHRES Reg: %d\r\n",
  254. XAxiVdma_ReadReg(InstancePtr->ReadChannel.ChanBase,
  255. XAXIVDMA_BUFTHRES_OFFSET));
  256. xil_printf("\tMM2S Vertical Size Register: %d\r\n",
  257. XAxiVdma_ReadReg(InstancePtr->ReadChannel.ChanBase,
  258. XAXIVDMA_MM2S_ADDR_OFFSET + XAXIVDMA_VSIZE_OFFSET));
  259. xil_printf("\tMM2S Horizontal Size Register: %d\r\n",
  260. XAxiVdma_ReadReg(InstancePtr->ReadChannel.ChanBase,
  261. XAXIVDMA_MM2S_ADDR_OFFSET + XAXIVDMA_HSIZE_OFFSET));
  262. xil_printf("\tMM2S Frame Delay and Stride Register: %d\r\n",
  263. XAxiVdma_ReadReg(InstancePtr->ReadChannel.ChanBase,
  264. XAXIVDMA_MM2S_ADDR_OFFSET + XAXIVDMA_STRD_FRMDLY_OFFSET));
  265. xil_printf("\tMM2S Start Address 1: %x\r\n",
  266. XAxiVdma_ReadReg(InstancePtr->ReadChannel.ChanBase,
  267. XAXIVDMA_MM2S_ADDR_OFFSET + XAXIVDMA_START_ADDR_OFFSET));
  268. xil_printf("VDMA status: ");
  269. if (status & XAXIVDMA_SR_HALTED_MASK)
  270. xil_printf("halted\n");
  271. else
  272. xil_printf("running\n");
  273. if (status & XAXIVDMA_SR_IDLE_MASK)
  274. xil_printf("idle\n");
  275. if (status & XAXIVDMA_SR_ERR_INTERNAL_MASK)
  276. xil_printf("internal err\n");
  277. if (status & XAXIVDMA_SR_ERR_SLAVE_MASK)
  278. xil_printf("slave err\n");
  279. if (status & XAXIVDMA_SR_ERR_DECODE_MASK)
  280. xil_printf("decode err\n");
  281. if (status & XAXIVDMA_SR_ERR_FSZ_LESS_MASK)
  282. xil_printf("FSize Less Mismatch err\n");
  283. if (status & XAXIVDMA_SR_ERR_LSZ_LESS_MASK)
  284. xil_printf("LSize Less Mismatch err\n");
  285. if (status & XAXIVDMA_SR_ERR_SG_SLV_MASK)
  286. xil_printf("SG slave err\n");
  287. if (status & XAXIVDMA_SR_ERR_SG_DEC_MASK)
  288. xil_printf("SG decode err\n");
  289. if (status & XAXIVDMA_SR_ERR_FSZ_MORE_MASK)
  290. xil_printf("FSize More Mismatch err\n");
  291. return status;
  292. }
  293. void fb_fill(uint32_t offset) {
  294. memset(framebuffer + offset, 0, 1280 * 1024 * 4);
  295. }
  296. static XClk_Wiz clkwiz;
  297. void pixelclock_init(int mhz) {
  298. XClk_Wiz_Config conf;
  299. XClk_Wiz_CfgInitialize(&clkwiz, &conf, XPAR_CLK_WIZ_0_BASEADDR);
  300. u32 phase = XClk_Wiz_ReadReg(XPAR_CLK_WIZ_0_BASEADDR, 0x20C);
  301. u32 duty = XClk_Wiz_ReadReg(XPAR_CLK_WIZ_0_BASEADDR, 0x210);
  302. u32 divide = XClk_Wiz_ReadReg(XPAR_CLK_WIZ_0_BASEADDR, 0x208);
  303. u32 muldiv = XClk_Wiz_ReadReg(XPAR_CLK_WIZ_0_BASEADDR, 0x200);
  304. u32 mul = 11;
  305. u32 div = 1;
  306. u32 otherdiv = 11;
  307. // Multiply/divide 100mhz fabric clock to desired pixel clock
  308. if (mhz == 50) {
  309. mul = 15;
  310. div = 1;
  311. otherdiv = 30;
  312. } else if (mhz == 40) {
  313. mul = 14;
  314. div = 1;
  315. otherdiv = 35;
  316. } else if (mhz == 75) {
  317. mul = 15;
  318. div = 1;
  319. otherdiv = 20;
  320. } else if (mhz == 65) {
  321. mul = 13;
  322. div = 1;
  323. otherdiv = 20;
  324. } else if (mhz == 27) {
  325. mul = 27;
  326. div = 2;
  327. otherdiv = 50;
  328. } else if (mhz == 54) {
  329. mul = 27;
  330. div = 1;
  331. otherdiv = 50;
  332. } else if (mhz == 150) {
  333. mul = 15;
  334. div = 1;
  335. otherdiv = 10;
  336. } else if (mhz == 25) { // 25.205
  337. mul = 15;
  338. div = 1;
  339. otherdiv = 60;
  340. } else if (mhz == 108) {
  341. mul = 54;
  342. div = 5;
  343. otherdiv = 10;
  344. }
  345. XClk_Wiz_WriteReg(XPAR_CLK_WIZ_0_BASEADDR, 0x200, (mul << 8) | div);
  346. XClk_Wiz_WriteReg(XPAR_CLK_WIZ_0_BASEADDR, 0x208, otherdiv);
  347. // load configuration
  348. XClk_Wiz_WriteReg(XPAR_CLK_WIZ_0_BASEADDR, 0x25C, 0x00000003);
  349. //XClk_Wiz_WriteReg(XPAR_CLK_WIZ_0_BASEADDR, 0x25C, 0x00000001);
  350. phase = XClk_Wiz_ReadReg(XPAR_CLK_WIZ_0_BASEADDR, 0x20C);
  351. printf("CLK phase: %lu\n", phase);
  352. duty = XClk_Wiz_ReadReg(XPAR_CLK_WIZ_0_BASEADDR, 0x210);
  353. printf("CLK duty: %lu\n", duty);
  354. divide = XClk_Wiz_ReadReg(XPAR_CLK_WIZ_0_BASEADDR, 0x208);
  355. printf("CLK divide: %lu\n", divide);
  356. muldiv = XClk_Wiz_ReadReg(XPAR_CLK_WIZ_0_BASEADDR, 0x200);
  357. printf("CLK muldiv: %lu\n", muldiv);
  358. }
  359. // FIXME!
  360. #define MNTZ_BASE_ADDR 0x43C00000
  361. #define MNTZORRO_REG0 0
  362. #define MNTZORRO_REG1 4
  363. #define MNTZORRO_REG2 8
  364. #define MNTZORRO_REG3 12
  365. #define mntzorro_read(BaseAddress, RegOffset) \
  366. Xil_In32((BaseAddress) + (RegOffset))
  367. #define mntzorro_write(BaseAddress, RegOffset, Data) \
  368. Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
  369. void video_formatter_valign() {
  370. // vertical alignment
  371. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG3, 1);
  372. usleep(1);
  373. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG2, 0x80000000 + 0x5); // OP_VSYNC
  374. usleep(1);
  375. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG3, 0);
  376. usleep(1);
  377. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG2, 0x80000000); // NOP
  378. usleep(1);
  379. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG2, 0); // NOP
  380. usleep(1);
  381. }
  382. #define VF_DLY ;
  383. #define MNTVF_OP_UNUSED 12
  384. #define MNTVF_OP_SPRITE_XY 13
  385. #define MNTVF_OP_SPRITE_ADDR 14
  386. #define MNTVF_OP_SPRITE_DATA 15
  387. #define MNTVF_OP_MAX 6
  388. #define MNTVF_OP_HS 7
  389. #define MNTVF_OP_VS 8
  390. #define MNTVF_OP_POLARITY 10
  391. #define MNTVF_OP_SCALE 4
  392. #define MNTVF_OP_DIMENSIONS 2
  393. #define MNTVF_OP_COLORMODE 1
  394. void video_formatter_write(uint32_t data, uint16_t op) {
  395. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG3, data);
  396. VF_DLY;
  397. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG2, 0x80000000 | op); // OP_MAX (vmax | hmax)
  398. VF_DLY;
  399. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG2, 0x80000000); // NOP
  400. VF_DLY;
  401. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG2, 0); // clear
  402. VF_DLY;
  403. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG3, 0); // clear
  404. VF_DLY;
  405. }
  406. void video_formatter_init(int scalemode, int colormode, int width, int height,
  407. int htotal, int vtotal, int hss, int hse, int vss, int vse,
  408. int polarity) {
  409. video_formatter_write((vtotal << 16) | htotal, MNTVF_OP_MAX);
  410. video_formatter_write((height << 16) | width, MNTVF_OP_DIMENSIONS);
  411. video_formatter_write((hss << 16) | hse, MNTVF_OP_HS);
  412. video_formatter_write((vss << 16) | vse, MNTVF_OP_VS);
  413. video_formatter_write(polarity, MNTVF_OP_POLARITY);
  414. video_formatter_write(scalemode, MNTVF_OP_SCALE);
  415. video_formatter_write(colormode, MNTVF_OP_COLORMODE);
  416. video_formatter_valign();
  417. }
  418. void video_system_init(int hres, int vres, int htotal, int vtotal, int mhz,
  419. int vhz, int hdiv, int vdiv, int hdmi) {
  420. printf("VSI: %d x %d [%d x %d] %d MHz %d Hz, hdiv: %d vdiv: %d\n", hres,
  421. vres, htotal, vtotal, mhz, vhz, hdiv, vdiv);
  422. printf("pixelclock_init()...\n");
  423. pixelclock_init(mhz);
  424. printf("...done.\n");
  425. printf("hdmi_set_video_mode()...\n");
  426. hdmi_set_video_mode(hres, vres, mhz, vhz, hdmi);
  427. printf("hdmi_ctrl_init()...\n");
  428. hdmi_ctrl_init();
  429. printf("init_vdma()...\n");
  430. init_vdma(hres, vres, hdiv, vdiv);
  431. printf("...done.\n");
  432. //dump_vdma_status(&vdma);
  433. }
  434. // Our address space is relative to the autoconfig base address (for example, it could be 0x600000)
  435. #define MNT_REG_BASE 0x000000
  436. #define MNT_FB_BASE 0x010000
  437. #define MNT_BASE_MODE MNT_REG_BASE+0x02
  438. #define MNT_BASE_CONFIG MNT_REG_BASE+0x04
  439. #define MNT_BASE_SPRITEX MNT_REG_BASE+0x06
  440. #define MNT_BASE_SPRITEY MNT_REG_BASE+0x08
  441. #define MNT_BASE_PAN_HI MNT_REG_BASE+0x0a
  442. #define MNT_BASE_PAN_LO MNT_REG_BASE+0x0c
  443. #define MNT_BASE_VCAP_VMODE MNT_REG_BASE+0x0e
  444. #define MNT_BASE_RECTOP MNT_REG_BASE+0x10
  445. #define MNT_BASE_BLIT_SRC_HI MNT_REG_BASE+0x28
  446. #define MNT_BASE_BLIT_SRC_LO MNT_REG_BASE+0x2a
  447. #define MNT_BASE_BLIT_DST_HI MNT_REG_BASE+0x2c
  448. #define MNT_BASE_BLIT_DST_LO MNT_REG_BASE+0x2e
  449. #define MNT_BASE_BLITTER_COLORMODE MNT_REG_BASE+0x30
  450. #define MNT_BASE_BLIT_SRC_PITCH MNT_REG_BASE+0x32
  451. #define MNT_BASE_ETH_TX MNT_REG_BASE+0x80
  452. #define MNT_BASE_ETH_RX MNT_REG_BASE+0x82
  453. #define MNT_BASE_ETH_MAC_HI MNT_REG_BASE+0x84
  454. #define MNT_BASE_ETH_MAC_HI2 MNT_REG_BASE+0x86
  455. #define MNT_BASE_ETH_MAC_LO MNT_REG_BASE+0x88
  456. #define MNT_BASE_RUN_HI MNT_REG_BASE+0x90
  457. #define MNT_BASE_RUN_LO MNT_REG_BASE+0x92
  458. #define MNT_BASE_RUN_ARGC MNT_REG_BASE+0x94
  459. #define MNT_BASE_RUN_ARG0 MNT_REG_BASE+0x96
  460. #define MNT_BASE_RUN_ARG1 MNT_REG_BASE+0x98
  461. #define MNT_BASE_RUN_ARG2 MNT_REG_BASE+0x9a
  462. #define MNT_BASE_RUN_ARG3 MNT_REG_BASE+0x9c
  463. #define MNT_BASE_RUN_ARG4 MNT_REG_BASE+0x9e
  464. #define MNT_BASE_RUN_ARG5 MNT_REG_BASE+0xa0
  465. #define MNT_BASE_RUN_ARG6 MNT_REG_BASE+0xa2
  466. #define MNT_BASE_RUN_ARG7 MNT_REG_BASE+0xa4
  467. #define MNT_BASE_EVENT_SERIAL MNT_REG_BASE+0xb0
  468. #define MNT_BASE_EVENT_CODE MNT_REG_BASE+0xb2
  469. #define MNT_BASE_FW_VERSION MNT_REG_BASE+0xc0
  470. #define MNT_BASE_USBBLK_TX_HI MNT_REG_BASE+0xd0
  471. #define MNT_BASE_USBBLK_TX_LO MNT_REG_BASE+0xd2
  472. #define MNT_BASE_USBBLK_RX_HI MNT_REG_BASE+0xd4
  473. #define MNT_BASE_USBBLK_RX_LO MNT_REG_BASE+0xd6
  474. #define MNT_BASE_USB_STATUS MNT_REG_BASE+0xd8
  475. #define MNT_BASE_USB_BUFSEL MNT_REG_BASE+0xda
  476. #define MNT_BASE_USB_CAPACITY MNT_REG_BASE+0xdc
  477. #define MNT_BASE_DEBUG MNT_REG_BASE+0xfc
  478. #define REVISION_MAJOR 1
  479. #define REVISION_MINOR 5
  480. #define ZZVMODE_1280x720 0
  481. #define ZZVMODE_800x600 1
  482. #define ZZVMODE_640x480 2
  483. #define ZZVMODE_1024x768 3
  484. #define ZZVMODE_1280x1024 4
  485. #define ZZVMODE_1920x1080_60 5
  486. #define ZZVMODE_720x576 6 // 50hz
  487. #define ZZVMODE_1920x1080_50 7 // 50hz
  488. #define ZZVMODE_720x480 8
  489. #define ZZVMODE_640x512 9
  490. void video_mode_init(int mode, int scalemode, int colormode) {
  491. int hres, vres, hmax, vmax, hstart, hend, vstart, vend, polarity, mhz, vhz, hdmi;
  492. int hdiv = 1, vdiv = 1;
  493. if (scalemode & 1)
  494. hdiv = 2;
  495. if (scalemode & 2)
  496. vdiv = 2;
  497. if (colormode == 0)
  498. hdiv *= 4;
  499. if (colormode == 1)
  500. hdiv *= 2;
  501. switch (mode) {
  502. case ZZVMODE_1280x720:
  503. hres = 1280;
  504. vres = 720;
  505. hstart = 1390;
  506. hend = 1430;
  507. hmax = 1650;
  508. vstart = 725;
  509. vend = 730;
  510. vmax = 750;
  511. polarity = 0;
  512. mhz = 75;
  513. vhz = 60;
  514. hdmi = 0;
  515. break;
  516. case ZZVMODE_800x600:
  517. hres = 800;
  518. vres = 600;
  519. hstart = 840;
  520. hend = 968;
  521. hmax = 1056;
  522. vstart = 601;
  523. vend = 605;
  524. vmax = 628;
  525. polarity = 0;
  526. mhz = 40;
  527. vhz = 60;
  528. hdmi = 0;
  529. break;
  530. case ZZVMODE_640x480:
  531. hres = 640;
  532. vres = 480;
  533. hstart = 656;
  534. hend = 752;
  535. hmax = 800;
  536. vstart = 490;
  537. vend = 492;
  538. vmax = 525;
  539. polarity = 0;
  540. mhz = 25;
  541. vhz = 60;
  542. hdmi = 0;
  543. break;
  544. case ZZVMODE_640x512:
  545. hres = 640;
  546. vres = 512;
  547. hstart = 840;
  548. hend = 968;
  549. hmax = 1056;
  550. vstart = 601;
  551. vend = 605;
  552. vmax = 628;
  553. polarity = 0;
  554. mhz = 40;
  555. vhz = 60;
  556. hdmi = 0;
  557. break;
  558. case ZZVMODE_720x480:
  559. hres = 720;
  560. vres = 480;
  561. hstart = 720;
  562. hend = 752;
  563. hmax = 800;
  564. vstart = 490;
  565. vend = 492;
  566. vmax = 525;
  567. polarity = 0;
  568. mhz = 25;
  569. vhz = 60;
  570. hdmi = 0;
  571. break;
  572. case ZZVMODE_1024x768:
  573. hres = 1024;
  574. vres = 768;
  575. hstart = 1048;
  576. hend = 1184;
  577. hmax = 1344;
  578. vstart = 771;
  579. vend = 777;
  580. vmax = 806;
  581. polarity = 0;
  582. mhz = 65;
  583. vhz = 60;
  584. hdmi = 0;
  585. break;
  586. case ZZVMODE_1280x1024:
  587. hres = 1280;
  588. vres = 1024;
  589. hstart = 1328;
  590. hend = 1440;
  591. hmax = 1688;
  592. vstart = 1025;
  593. vend = 1028;
  594. vmax = 1066;
  595. polarity = 0;
  596. mhz = 108;
  597. vhz = 60;
  598. hdmi = 0;
  599. break;
  600. case ZZVMODE_1920x1080_50:
  601. hres = 1920;
  602. vres = 1080;
  603. hstart = 2448;
  604. hend = 2492;
  605. hmax = 2640;
  606. vstart = 1084;
  607. vend = 1089;
  608. vmax = 1125;
  609. polarity = 0;
  610. mhz = 150;
  611. vhz = 50;
  612. hdmi = 0;
  613. break;
  614. case ZZVMODE_1920x1080_60:
  615. hres = 1920;
  616. vres = 1080;
  617. hstart = 2008;
  618. hend = 2052;
  619. hmax = 2200;
  620. vstart = 1084;
  621. vend = 1089;
  622. vmax = 1125;
  623. polarity = 0;
  624. mhz = 150;
  625. vhz = 50;
  626. hdmi = 0;
  627. break;
  628. case ZZVMODE_720x576:
  629. hres = 720;
  630. vres = 576;
  631. hstart = 732;
  632. hend = 796;
  633. hmax = 864;
  634. vstart = 581;
  635. vend = 586;
  636. vmax = 625;
  637. polarity = 1;
  638. mhz = 27;
  639. vhz = 50;
  640. hdmi = 0;
  641. break;
  642. default:
  643. printf("Error: unknown mode\n");
  644. return;
  645. }
  646. video_system_init(hres, vres, hmax, vmax, mhz, vhz, hdiv, vdiv, hdmi);
  647. video_formatter_init(scalemode, colormode, hres, vres, hmax, vmax, hstart,
  648. hend, vstart, vend, polarity);
  649. vmode_hsize = hres;
  650. vmode_vsize = vres;
  651. vmode_vdiv = vdiv;
  652. vmode_hdiv = hdiv;
  653. }
  654. int16_t sprite_x = 0, sprite_x_adj = 0;
  655. int16_t sprite_y = 0, sprite_y_adj = 0;
  656. uint16_t sprite_enabled = 0;
  657. uint32_t sprite_buf[32 * 48];
  658. uint8_t sprite_clipped = 0;
  659. int16_t sprite_clip_x = 0, sprite_clip_y = 0;
  660. int8_t sprite_x_offset = 0;
  661. int8_t sprite_y_offset = 0;
  662. uint8_t sprite_width = 16;
  663. uint8_t sprite_height = 16;
  664. uint32_t sprite_colors[4] = { 0x00ff00ff, 0x00000000, 0x00000000, 0x00000000 };
  665. uint8_t sprite_template[16*16] = {
  666. 0,0,0,1,1,0,0,0,0,0,0,0,0,0,0,0,
  667. 0,0,0,3,3,1,1,0,0,0,0,0,0,0,0,0,
  668. 0,0,0,2,3,3,3,1,1,0,0,0,0,0,0,0,
  669. 0,0,0,2,3,3,3,3,3,1,1,0,0,0,0,0,
  670. 0,0,0,0,2,3,3,3,3,3,3,1,1,0,0,0,
  671. 0,0,0,0,2,3,3,3,3,3,3,3,3,1,1,0,
  672. 0,0,0,0,0,2,3,3,3,3,3,3,3,3,2,0,
  673. 0,0,0,0,0,2,3,3,3,3,3,3,3,2,2,0,
  674. 0,0,0,0,0,0,2,3,3,3,3,3,3,2,0,0,
  675. 0,0,0,0,0,0,2,3,3,3,3,3,3,1,0,0,
  676. 0,0,0,0,0,0,0,2,3,3,2,2,3,3,1,0,
  677. 0,0,0,0,0,0,0,2,3,2,2,2,2,3,3,1,
  678. 0,0,0,0,0,0,0,0,2,2,0,0,2,2,3,2,
  679. 0,0,0,0,0,0,0,0,2,0,0,0,0,2,2,2,
  680. 0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,
  681. 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
  682. };
  683. void sprite_hide() {
  684. sprite_x = 2000;
  685. sprite_y = 2000;
  686. sprite_enabled = 0;
  687. video_formatter_write((sprite_y << 16) | sprite_x, MNTVF_OP_SPRITE_XY);
  688. }
  689. void sprite_reset() {
  690. sprite_hide();
  691. for (int y=0; y<16; y++) {
  692. for (int x=0; x<16; x++) {
  693. uint8_t addr = y*16+x;
  694. uint32_t data = 0xff00ff;
  695. if (sprite_template[y*16+x]==1) {
  696. data = 0xffffff;
  697. } else if (sprite_template[y*16+x]==2) {
  698. data = 0x000000;
  699. } else if (sprite_template[y*16+x]==3) {
  700. data = (255-15*y)<<16;
  701. }
  702. video_formatter_write((addr << 24) | data, MNTVF_OP_SPRITE_DATA);
  703. }
  704. }
  705. }
  706. // this mode can be changed by amiga software to select a different resolution / framerate for
  707. // native video capture
  708. //static int videocap_video_mode = ZZVMODE_720x576;
  709. //static int video_mode = ZZVMODE_720x576|2<<12|MNTVA_COLOR_32BIT<<8;
  710. //static int default_pan_offset = 0x00e00000;
  711. // default to more compatible 60hz mode
  712. static int videocap_video_mode = ZZVMODE_800x600;
  713. static int video_mode = ZZVMODE_800x600 | 2 << 12 | MNTVA_COLOR_32BIT << 8;
  714. static int default_pan_offset = 0x00e00bf8;
  715. static char usb_storage_available = 0;
  716. static uint32_t usb_storage_read_block = 0;
  717. static uint32_t usb_storage_write_block = 0;
  718. // ethernet state
  719. uint16_t ethernet_send_result = 0;
  720. // usb state
  721. uint16_t usb_status = 0;
  722. // we can read or write a number of USB blocks at once, and amiga can select which one is mapped at the USB storage buffer area
  723. uint32_t usb_selected_buffer_block = 0;
  724. uint32_t usb_read_write_num_blocks = 1;
  725. // debug things like individual reads/writes, greatly slowing the system down
  726. uint32_t debug_lowlevel = 0;
  727. void videocap_area_clear() {
  728. fb_fill(0x00e00000 / 4);
  729. }
  730. void reset_default_videocap_pan() {
  731. if (videocap_video_mode == ZZVMODE_800x600) {
  732. default_pan_offset = 0x00e00bf8;
  733. } else {
  734. default_pan_offset = 0x00e00000;
  735. }
  736. }
  737. void handle_amiga_reset() {
  738. reset_default_videocap_pan();
  739. framebuffer_pan_offset = default_pan_offset;
  740. videocap_area_clear();
  741. printf(" _______________ ___ ___ ___ \n");
  742. printf(" |___ /___ / _ \\ / _ \\ / _ \\ / _ \\ \n");
  743. printf(" / / / / (_) | | | | | | | | | |\n");
  744. printf(" / / / / \\__, | | | | | | | | | |\n");
  745. printf(" / /__ / /__ / /| |_| | |_| | |_| |\n");
  746. printf(" /_____/_____|/_/ \\___/ \\___/ \\___/ \n\n");
  747. usleep(10000);
  748. // scalemode 2 (vertical doubling)
  749. video_mode_init(videocap_video_mode, 2, MNTVA_COLOR_32BIT);
  750. video_mode = videocap_video_mode | 2 << 12 | MNTVA_COLOR_32BIT << 8;
  751. sprite_reset();
  752. ethernet_init();
  753. usb_storage_available = zz_usb_init();
  754. usb_status = 0;
  755. usb_selected_buffer_block = 0;
  756. usb_read_write_num_blocks = 1;
  757. ethernet_send_result = 0;
  758. // FIXME there should be more state to be reset
  759. }
  760. uint16_t arm_app_output_event_serial = 0;
  761. uint16_t arm_app_output_event_code = 0;
  762. char arm_app_output_event_ack = 0;
  763. uint16_t arm_app_output_events_blocking = 0;
  764. uint16_t arm_app_output_putchar_to_events = 0;
  765. uint16_t arm_app_input_event_serial = 0;
  766. uint16_t arm_app_input_event_code = 0;
  767. char arm_app_input_event_ack = 0;
  768. uint32_t arm_app_output_events_timeout = 100000;
  769. void arm_app_put_event_code(uint16_t code) {
  770. arm_app_output_event_code = code;
  771. arm_app_output_event_ack = 0;
  772. arm_app_output_event_serial++;
  773. }
  774. char arm_app_output_event_acked() {
  775. return arm_app_output_event_ack;
  776. }
  777. void arm_app_set_output_events_blocking(char blocking) {
  778. arm_app_output_events_blocking = blocking;
  779. }
  780. void arm_app_set_output_putchar_to_events(char putchar_enabled) {
  781. arm_app_output_putchar_to_events = putchar_enabled;
  782. }
  783. uint16_t arm_app_get_event_serial() {
  784. return arm_app_input_event_serial;
  785. }
  786. uint16_t arm_app_get_event_code() {
  787. arm_app_input_event_ack = 1;
  788. return arm_app_input_event_code;
  789. }
  790. int __attribute__ ((visibility ("default"))) _putchar(char c) {
  791. if (arm_app_output_putchar_to_events) {
  792. if (arm_app_output_events_blocking) {
  793. for (uint32_t i = 0; i < arm_app_output_events_timeout; i++) {
  794. usleep(1);
  795. if (arm_app_output_event_ack)
  796. break;
  797. }
  798. }
  799. arm_app_put_event_code(c);
  800. }
  801. return putchar(c);
  802. }
  803. struct ZZ9K_ENV {
  804. uint32_t api_version;
  805. uint32_t argv[8];
  806. uint32_t argc;
  807. int (*fn_putchar)(char);
  808. void (*fn_set_output_putchar_to_events)(char);
  809. void (*fn_set_output_events_blocking)(char);
  810. void (*fn_put_event_code)(uint16_t);
  811. uint16_t (*fn_get_event_serial)();
  812. uint16_t (*fn_get_event_code)();
  813. char (*fn_output_event_acked)();
  814. };
  815. void arm_exception_handler(void *callback);
  816. void arm_exception_handler_illinst(void *callback);
  817. volatile struct ZZ9K_ENV arm_run_env;
  818. volatile void (*core1_trampoline)(volatile struct ZZ9K_ENV* env);
  819. volatile int core2_execute = 0;
  820. #pragma GCC push_options
  821. #pragma GCC optimize ("O1")
  822. // core1_loop is executed on core1 (vs core0)
  823. void core1_loop() {
  824. asm("mov r0, r0");
  825. asm("mrc p15, 0, r1, c1, c0, 2");
  826. /* read cp access control register (CACR) into r1 */
  827. asm("orr r1, r1, #(0xf << 20)");
  828. /* enable full access for p10 & p11 */
  829. asm("mcr p15, 0, r1, c1, c0, 2");
  830. /* write back into CACR */
  831. // enable FPU
  832. asm("fmrx r1, FPEXC");
  833. /* read the exception register */
  834. asm("orr r1,r1, #0x40000000");
  835. /* set VFP enable bit, leave the others in orig state */
  836. asm("fmxr FPEXC, r1");
  837. /* write back the exception register */
  838. // enable flow prediction
  839. asm("mrc p15,0,r0,c1,c0,0");
  840. /* flow prediction enable */
  841. asm("orr r0, r0, #(0x01 << 11)");
  842. /* #0x8000 */
  843. asm("mcr p15,0,r0,c1,c0,0");
  844. asm("mrc p15,0,r0,c1,c0,1");
  845. /* read Auxiliary Control Register */
  846. asm("orr r0, r0, #(0x1 << 2)");
  847. /* enable Dside prefetch */
  848. asm("orr r0, r0, #(0x1 << 1)");
  849. /* enable L2 Prefetch hint */
  850. asm("mcr p15,0,r0,c1,c0,1");
  851. /* write Auxiliary Control Register */
  852. // stack
  853. asm("mov sp, #0x06000000");
  854. volatile uint32_t* addr = 0;
  855. addr[0] = 0xe3e0000f; // mvn r0, #15 -- loads 0xfffffff0
  856. addr[1] = 0xe590f000; // ldr pc, [r0] -- jumps to the address in that address
  857. // FIXME these don't seem to do anything useful yet
  858. Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_RESET,
  859. (Xil_ExceptionHandler) arm_exception_handler, NULL);
  860. Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_DATA_ABORT_INT,
  861. (Xil_ExceptionHandler) arm_exception_handler, NULL);
  862. Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_PREFETCH_ABORT_INT,
  863. (Xil_ExceptionHandler) arm_exception_handler, NULL);
  864. Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_UNDEFINED_INT,
  865. (Xil_ExceptionHandler) arm_exception_handler_illinst, NULL);
  866. while (1) {
  867. while (!core2_execute) {
  868. usleep(1);
  869. }
  870. core2_execute = 0;
  871. printf("[CPU1] executing at %p.\n", core1_trampoline);
  872. Xil_DCacheFlush();
  873. Xil_ICacheInvalidate();
  874. asm("push {r0-r12}");
  875. // FIXME HACK save our stack pointer in 0x10000
  876. asm("mov r0, #0x00010000");
  877. asm("str sp, [r0]");
  878. core1_trampoline(&arm_run_env);
  879. asm("mov r0, #0x00010000");
  880. asm("ldr sp, [r0]");
  881. asm("pop {r0-r12}");
  882. }
  883. }
  884. #pragma GCC pop_options
  885. int main() {
  886. const char* zstates[53] = { "RESET ", "Z2_CONF ", "Z2_IDLE ", "WAIT_WRI",
  887. "WAIT_WR2", "Z2WRIFIN", "WAIT_RD ", "WAIT_RD2", "WAIT_RD3",
  888. "CONFIGED", "CONF_CLR", "D_Z2_Z3 ", "Z3_IDLE ", "Z3_WRITE_UPP",
  889. "Z3_WRITE_LOW", "Z3_READ_UP", "Z3_READ_LOW", "Z3_READ_DLY",
  890. "Z3_READ_DLY1", "Z3_READ_DLY2", "Z3_WRITE_PRE", "Z3_WRITE_FIN",
  891. "Z3_ENDCYCLE", "Z3_DTACK", "Z3_CONFIG", "Z2_REGWRITE", "REGWRITE",
  892. "REGREAD", "Z2_REGR_POST", "Z3_REGR_POST", "Z3_REGWRITE",
  893. "Z2_REGREAD", "Z3_REGREAD", "NONE_33", "Z2_PRE_CONF", "Z2_ENDCYCLE",
  894. "NONE_36", "NONE_37", "NONE_38", "RESET_DVID", "COLD", "WR2B",
  895. "WR2C", "Z3DMA1", "Z3DMA2", "Z3_AUTOCONF_RD", "Z3_AUTOCONF_WR",
  896. "Z3_AUTOCONF_RD_DLY", "Z3_AUTOCONF_RD_DLY2", "Z3_REGWRITE_PRE",
  897. "Z3_REGREAD_PRE", "Z3_WRITE_PRE2", "UNDEF", };
  898. init_platform();
  899. Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_DATA_ABORT_INT,
  900. (Xil_ExceptionHandler) arm_exception_handler, NULL);
  901. Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_PREFETCH_ABORT_INT,
  902. (Xil_ExceptionHandler) arm_exception_handler, NULL);
  903. Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_UNDEFINED_INT,
  904. (Xil_ExceptionHandler) arm_exception_handler_illinst, NULL);
  905. disable_reset_out();
  906. // FIXME constant
  907. framebuffer = (u32*) 0x00200000;
  908. int need_req_ack = 0;
  909. u8* mem = (u8*) framebuffer;
  910. // blitter etc
  911. uint16_t rect_x1 = 0;
  912. uint16_t rect_x2 = 0;
  913. uint16_t rect_x3 = 0;
  914. uint16_t rect_y1 = 0;
  915. uint16_t rect_y2 = 0;
  916. uint16_t rect_y3 = 0;
  917. uint16_t blitter_dst_pitch = 640;
  918. uint32_t rect_rgb = 0;
  919. uint32_t rect_rgb2 = 0;
  920. uint32_t blitter_colormode = MNTVA_COLOR_32BIT;
  921. uint16_t blitter_src_pitch = 0;
  922. uint16_t blitter_user1 = 0;
  923. uint16_t blitter_user2 = 0;
  924. uint16_t blitter_user3 = 0;
  925. uint16_t blitter_user4 = 0;
  926. // ARM app run environment
  927. arm_run_env.api_version = 1;
  928. arm_run_env.fn_putchar = _putchar;
  929. arm_run_env.fn_get_event_code = arm_app_get_event_code;
  930. arm_run_env.fn_get_event_serial = arm_app_get_event_serial;
  931. arm_run_env.fn_output_event_acked = arm_app_output_event_acked;
  932. arm_run_env.fn_put_event_code = arm_app_put_event_code;
  933. arm_run_env.fn_set_output_events_blocking =
  934. arm_app_set_output_events_blocking;
  935. arm_run_env.fn_set_output_putchar_to_events =
  936. arm_app_set_output_putchar_to_events;
  937. arm_run_env.argc = 0;
  938. uint32_t arm_run_address = 0;
  939. // zorro state
  940. u32 zstate_raw;
  941. int interlace_old = 0;
  942. int videocap_ntsc_old = 0;
  943. handle_amiga_reset();
  944. printf("launch core1...\n");
  945. volatile uint32_t* core1_addr = (volatile uint32_t*) 0xFFFFFFF0;
  946. *core1_addr = (uint32_t) core1_loop;
  947. // Place some machine code in strategic positions that will catch core1 if it crashes
  948. // FIXME: clean this up and turn into a debug handler / monitor
  949. volatile uint32_t* core1_addr2 = (volatile uint32_t*) 0x140; // catch 1
  950. core1_addr2[0] = 0xe3e0000f; // mvn r0, #15 -- loads 0xfffffff0
  951. core1_addr2[1] = 0xe590f000; // ldr pc, [r0] -- jumps to the address in that address
  952. core1_addr2 = (volatile uint32_t*) 0x100; // catch 2
  953. core1_addr2[0] = 0xe3e0000f; // mvn r0, #15 -- loads 0xfffffff0
  954. core1_addr2[1] = 0xe590f000; // ldr pc, [r0] -- jumps to the address in that address
  955. asm("sev");
  956. printf("core1 now idling.\n");
  957. int cache_counter = 0;
  958. int videocap_enabled_old = 1;
  959. int scalemode = 0;
  960. int colormode = 0;
  961. uint32_t framebuffer_pan_offset_old = framebuffer_pan_offset;
  962. video_mode = 0x2200;
  963. int backlog_nag_counter = 0;
  964. int interrupt_enabled = 0;
  965. int request_video_align=0;
  966. int vblank=0;
  967. while (1) {
  968. u32 zstate = mntzorro_read(MNTZ_BASE_ADDR, MNTZORRO_REG3);
  969. zstate_raw = zstate;
  970. u32 writereq = (zstate & (1 << 31));
  971. u32 readreq = (zstate & (1 << 30));
  972. zstate = zstate & 0xff;
  973. if (zstate > 52) zstate = 52;
  974. if (writereq) {
  975. u32 zaddr = mntzorro_read(MNTZ_BASE_ADDR, MNTZORRO_REG0);
  976. u32 zdata = mntzorro_read(MNTZ_BASE_ADDR, MNTZORRO_REG1);
  977. u32 ds3 = (zstate_raw & (1 << 29));
  978. u32 ds2 = (zstate_raw & (1 << 28));
  979. u32 ds1 = (zstate_raw & (1 << 27));
  980. u32 ds0 = (zstate_raw & (1 << 26));
  981. if (debug_lowlevel) {
  982. printf("WRTE: %08lx <- %08lx [%d%d%d%d]\n",zaddr,zdata,!!ds3,!!ds2,!!ds1,!!ds0);
  983. }
  984. if (zaddr > 0x10000000) {
  985. printf("ERRW illegal address %08lx\n", zaddr);
  986. } else if (zaddr >= MNT_FB_BASE || zaddr >= MNT_REG_BASE + 0x2000) {
  987. u8* ptr = mem;
  988. if (zaddr >= MNT_FB_BASE) {
  989. ptr = mem + zaddr - MNT_FB_BASE;
  990. } else if (zaddr < MNT_REG_BASE + 0x8000) {
  991. // FIXME remove
  992. ptr = (u8*) (RX_FRAME_ADDRESS + zaddr - (MNT_REG_BASE + 0x2000));
  993. //printf("ERXF write: %08lx\n", (u32) ptr);
  994. } else if (zaddr < MNT_REG_BASE + 0xa000) {
  995. ptr = (u8*) (TX_FRAME_ADDRESS + zaddr - (MNT_REG_BASE + 0x8000));
  996. } else if (zaddr < MNT_REG_BASE + 0x10000) {
  997. // 0xa000-0xafff: write to block device (usb storage)
  998. // TODO: this should be moved to DMA space?
  999. ptr = (u8*) (USB_BLOCK_STORAGE_ADDRESS + zaddr - (MNT_REG_BASE + 0xa000) + usb_selected_buffer_block * 512);
  1000. }
  1001. // FIXME cache this
  1002. u32 z3 = (zstate_raw & (1 << 25));
  1003. if (z3) {
  1004. if (ds3) ptr[0] = zdata >> 24;
  1005. if (ds2) ptr[1] = zdata >> 16;
  1006. if (ds1) ptr[2] = zdata >> 8;
  1007. if (ds0) ptr[3] = zdata;
  1008. } else {
  1009. // swap bytes
  1010. if (ds1) ptr[0] = zdata >> 8;
  1011. if (ds0) ptr[1] = zdata;
  1012. }
  1013. } else if (zaddr >= MNT_REG_BASE && zaddr < MNT_FB_BASE) {
  1014. // register area
  1015. //printf("REGW: %08lx <- %08lx [%d%d%d%d]\n",zaddr,zdata,!!ds3,!!ds2,!!ds1,!!ds0);
  1016. u32 z3 = (zstate_raw & (1 << 25));
  1017. if (z3) {
  1018. // convert 32bit to 16bit addresses
  1019. if (ds3 && ds2) {
  1020. zdata = zdata >> 16;
  1021. } else if (ds1 && ds0) {
  1022. zdata = zdata & 0xffff;
  1023. zaddr += 2;
  1024. } else {
  1025. zaddr = 0; // cancel
  1026. }
  1027. }
  1028. //printf("CONV: %08lx <- %08lx\n",zaddr,zdata);
  1029. switch (zaddr) {
  1030. // Various blitter/video registers
  1031. case MNT_BASE_PAN_HI:
  1032. framebuffer_pan_offset = zdata << 16;
  1033. break;
  1034. case MNT_BASE_PAN_LO:
  1035. framebuffer_pan_offset |= zdata;
  1036. if (framebuffer_pan_offset != framebuffer_pan_offset_old) {
  1037. // VDMA will be reinitialized on the next vertical blank
  1038. request_video_align = 1;
  1039. framebuffer_pan_offset_old = framebuffer_pan_offset;
  1040. }
  1041. break;
  1042. case MNT_BASE_BLIT_SRC_HI:
  1043. blitter_src_offset = zdata << 16;
  1044. break;
  1045. case MNT_BASE_BLIT_SRC_LO:
  1046. blitter_src_offset |= zdata;
  1047. break;
  1048. case MNT_BASE_BLIT_DST_HI:
  1049. blitter_dst_offset = zdata << 16;
  1050. break;
  1051. case MNT_BASE_BLIT_DST_LO:
  1052. blitter_dst_offset |= zdata;
  1053. break;
  1054. case MNT_BASE_BLITTER_COLORMODE:
  1055. blitter_colormode = zdata;
  1056. break;
  1057. case MNT_BASE_CONFIG:
  1058. // enable/disable INT6, currently used to signal incoming ethernet packets
  1059. interrupt_enabled = zdata & 1;
  1060. break;
  1061. case MNT_BASE_MODE:
  1062. printf("mode change: %lx\n", zdata);
  1063. if (video_mode != zdata) {
  1064. int mode = zdata & 0xff;
  1065. colormode = (zdata & 0xf00) >> 8;
  1066. scalemode = (zdata & 0xf000) >> 12;
  1067. printf("mode: %d color: %d scale: %d\n", mode,
  1068. colormode, scalemode);
  1069. video_mode_init(mode, scalemode, colormode);
  1070. }
  1071. // remember selected video mode
  1072. video_mode = zdata;
  1073. break;
  1074. case MNT_BASE_VCAP_VMODE:
  1075. printf("videocap default mode select: %lx\n", zdata);
  1076. videocap_video_mode = zdata &0xff;
  1077. break;
  1078. case MNT_BASE_SPRITEX:
  1079. case MNT_BASE_SPRITEY:
  1080. if (!sprite_enabled)
  1081. break;
  1082. if (zaddr == MNT_BASE_SPRITEX) {
  1083. // The "+#" offset at the end is dependent on implementation timing slack, and needs
  1084. // to be adjusted based on the sprite X offset produced by the current run.
  1085. sprite_x = (int16_t)zdata + sprite_x_offset + 3;
  1086. sprite_x_adj = sprite_x;
  1087. // horizontally doubled mode
  1088. if (scalemode&1) sprite_x*=2;
  1089. }
  1090. else {
  1091. sprite_y = (int16_t)zdata + sprite_y_offset;
  1092. sprite_y_adj = sprite_y;
  1093. // vertically doubled mode
  1094. if (scalemode&2) sprite_y*=2;
  1095. if (sprite_x < 0 || sprite_y < 0) {
  1096. if (sprite_clip_x != sprite_x || sprite_clip_y != sprite_y) {
  1097. clip_hw_sprite((sprite_x < 0) ? sprite_x : 0, (sprite_y < 0) ? sprite_y : 0);
  1098. }
  1099. sprite_clipped = 1;
  1100. if (sprite_x < 0) {
  1101. sprite_x_adj = 0;
  1102. sprite_clip_x = sprite_x;
  1103. }
  1104. if (sprite_y < 0) {
  1105. sprite_y_adj = 0;
  1106. sprite_clip_y = sprite_y;
  1107. }
  1108. }
  1109. else if (sprite_clipped && sprite_x >= 0 && sprite_y >= 0) {
  1110. clip_hw_sprite(0, 0);
  1111. sprite_clipped = 0;
  1112. }
  1113. video_formatter_write((sprite_y_adj << 16) | sprite_x_adj, MNTVF_OP_SPRITE_XY);
  1114. }
  1115. break;
  1116. case MNT_BASE_RECTOP + 0x38: { // SPRITE_BITMAP
  1117. if (zdata == 1) { // Hardware sprite enabled
  1118. sprite_enabled = 1;
  1119. break;
  1120. }
  1121. else if (zdata == 2) { // Hardware sprite disabled
  1122. sprite_hide();
  1123. break;
  1124. }
  1125. uint8_t* bmp_data = (uint8_t*) ((u32) framebuffer
  1126. + blitter_src_offset);
  1127. clear_hw_sprite();
  1128. sprite_x_offset = rect_x1;
  1129. sprite_y_offset = rect_y1;
  1130. sprite_width = rect_x2;
  1131. sprite_height = rect_y2;
  1132. update_hw_sprite(bmp_data, sprite_colors, sprite_width, sprite_height);
  1133. break;
  1134. }
  1135. case MNT_BASE_RECTOP + 0x3a: { // SPRITE_COLORS
  1136. sprite_colors[zdata] = (blitter_user1 << 16) | blitter_user2;
  1137. if (sprite_colors[zdata] == 0xff00ff) sprite_colors[zdata] = 0xfe00fe;
  1138. break;
  1139. }
  1140. case MNT_BASE_BLIT_SRC_PITCH:
  1141. blitter_src_pitch = zdata;
  1142. break;
  1143. case MNT_BASE_RECTOP:
  1144. rect_x1 = zdata;
  1145. break;
  1146. case MNT_BASE_RECTOP + 2:
  1147. rect_y1 = zdata;
  1148. break;
  1149. case MNT_BASE_RECTOP + 4:
  1150. rect_x2 = zdata;
  1151. break;
  1152. case MNT_BASE_RECTOP + 6:
  1153. rect_y2 = zdata;
  1154. break;
  1155. case MNT_BASE_RECTOP + 8:
  1156. blitter_dst_pitch = zdata;
  1157. break;
  1158. case MNT_BASE_RECTOP + 0xa:
  1159. rect_x3 = zdata;
  1160. break;
  1161. case MNT_BASE_RECTOP + 0xc:
  1162. rect_y3 = zdata;
  1163. break;
  1164. case MNT_BASE_RECTOP + 0x30:
  1165. blitter_user1 = zdata;
  1166. break;
  1167. case MNT_BASE_RECTOP + 0x32:
  1168. blitter_user2 = zdata;
  1169. break;
  1170. case MNT_BASE_RECTOP + 0x34:
  1171. blitter_user3 = zdata;
  1172. break;
  1173. case MNT_BASE_RECTOP + 0x36:
  1174. blitter_user4 = zdata;
  1175. break;
  1176. case MNT_BASE_RECTOP + 0xe:
  1177. rect_rgb &= 0xffff0000;
  1178. rect_rgb |= (((zdata & 0xff) << 8) | zdata >> 8);
  1179. break;
  1180. case MNT_BASE_RECTOP + 0x10:
  1181. rect_rgb &= 0x0000ffff;
  1182. rect_rgb |= (((zdata & 0xff) << 8) | zdata >> 8) << 16;
  1183. break;
  1184. case MNT_BASE_RECTOP + 0x24:
  1185. rect_rgb2 &= 0xffff0000;
  1186. rect_rgb2 |= (((zdata & 0xff) << 8) | zdata >> 8);
  1187. break;
  1188. case MNT_BASE_RECTOP + 0x26:
  1189. rect_rgb2 &= 0x0000ffff;
  1190. rect_rgb2 |= (((zdata & 0xff) << 8) | zdata >> 8) << 16;
  1191. break;
  1192. // RTG rendering
  1193. case MNT_BASE_RECTOP + 0x12:
  1194. // fill rectangle
  1195. set_fb((uint32_t*) ((u32) framebuffer + blitter_dst_offset),
  1196. blitter_dst_pitch);
  1197. uint8_t mask = zdata;
  1198. if (mask == 0xFF)
  1199. fill_rect_solid(rect_x1, rect_y1, rect_x2, rect_y2,
  1200. rect_rgb, blitter_colormode);
  1201. else
  1202. fill_rect(rect_x1, rect_y1, rect_x2, rect_y2, rect_rgb,
  1203. blitter_colormode, mask);
  1204. break;
  1205. case MNT_BASE_RECTOP + 0x14: {
  1206. // copy rectangle
  1207. set_fb((uint32_t*) ((u32) framebuffer + blitter_dst_offset),
  1208. blitter_dst_pitch);
  1209. mask = (blitter_colormode >> 8);
  1210. switch (zdata) {
  1211. case 1: // Regular BlitRect
  1212. if (mask == 0xFF || (mask != 0xFF && (blitter_colormode & 0x0F)) != MNTVA_COLOR_8BIT)
  1213. copy_rect_nomask(rect_x1, rect_y1, rect_x2, rect_y2, rect_x3,
  1214. rect_y3, blitter_colormode & 0x0F,
  1215. (uint32_t*) ((u32) framebuffer
  1216. + blitter_dst_offset),
  1217. blitter_dst_pitch, MINTERM_SRC);
  1218. else
  1219. copy_rect(rect_x1, rect_y1, rect_x2, rect_y2, rect_x3,
  1220. rect_y3, blitter_colormode & 0x0F,
  1221. (uint32_t*) ((u32) framebuffer
  1222. + blitter_dst_offset),
  1223. blitter_dst_pitch, mask);
  1224. break;
  1225. case 2: // BlitRectNoMaskComplete
  1226. copy_rect_nomask(rect_x1, rect_y1, rect_x2, rect_y2, rect_x3,
  1227. rect_y3, blitter_colormode & 0x0F,
  1228. (uint32_t*) ((u32) framebuffer
  1229. + blitter_src_offset),
  1230. blitter_src_pitch, mask); // Mask in this case is minterm/opcode.
  1231. break;
  1232. }
  1233. break;
  1234. }
  1235. case MNT_BASE_RECTOP + 0x16: {
  1236. uint8_t draw_mode = blitter_colormode >> 8;
  1237. uint8_t* tmpl_data = (uint8_t*) ((u32) framebuffer
  1238. + blitter_src_offset);
  1239. set_fb((uint32_t*) ((u32) framebuffer + blitter_dst_offset),
  1240. blitter_dst_pitch);
  1241. uint8_t bpp = 2 * (blitter_colormode & 0xff);
  1242. if (bpp == 0)
  1243. bpp = 1;
  1244. uint16_t loop_rows = 0;
  1245. mask = zdata;
  1246. if (zdata & 0x8000) {
  1247. // pattern mode
  1248. // TODO yoffset
  1249. loop_rows = zdata & 0xff;
  1250. mask = blitter_user1;
  1251. blitter_src_pitch = 16;
  1252. pattern_fill_rect((blitter_colormode & 0x0F), rect_x1,
  1253. rect_y1, rect_x2, rect_y2, draw_mode, mask,
  1254. rect_rgb, rect_rgb2, rect_x3, rect_y3, tmpl_data,
  1255. blitter_src_pitch, loop_rows);
  1256. }
  1257. else {
  1258. template_fill_rect((blitter_colormode & 0x0F), rect_x1,
  1259. rect_y1, rect_x2, rect_y2, draw_mode, mask,
  1260. rect_rgb, rect_rgb2, rect_x3, rect_y3, tmpl_data,
  1261. blitter_src_pitch);
  1262. }
  1263. break;
  1264. }
  1265. case MNT_BASE_RECTOP + 0x28: {
  1266. // Rect P2C
  1267. uint8_t draw_mode = blitter_colormode >> 8;
  1268. uint8_t planes = (zdata & 0xFF00) >> 8;
  1269. uint8_t mask = (zdata & 0xFF);
  1270. uint16_t num_rows = blitter_user1;
  1271. uint8_t layer_mask = blitter_user2;
  1272. uint8_t* bmp_data = (uint8_t*) ((u32) framebuffer
  1273. + blitter_src_offset);
  1274. set_fb((uint32_t*) ((u32) framebuffer + blitter_dst_offset),
  1275. blitter_dst_pitch);
  1276. p2c_rect(rect_x1, 0, rect_x2, rect_y2, rect_x3,
  1277. rect_y3, num_rows, draw_mode, planes, mask,
  1278. layer_mask, blitter_src_pitch, bmp_data);
  1279. break;
  1280. }
  1281. case MNT_BASE_RECTOP + 0x2c: {
  1282. // Rect P2D
  1283. uint8_t draw_mode = blitter_colormode >> 8;
  1284. uint8_t planes = (zdata & 0xFF00) >> 8;
  1285. uint8_t mask = (zdata & 0xFF);
  1286. uint16_t num_rows = blitter_user1;
  1287. uint8_t layer_mask = blitter_user2;
  1288. uint8_t* bmp_data = (uint8_t*) ((u32) framebuffer
  1289. + blitter_src_offset);
  1290. set_fb((uint32_t*) ((u32) framebuffer + blitter_dst_offset),
  1291. blitter_dst_pitch);
  1292. p2d_rect(rect_x1, 0, rect_x2, rect_y2, rect_x3,
  1293. rect_y3, num_rows, draw_mode, planes, mask, layer_mask, rect_rgb,
  1294. blitter_src_pitch, bmp_data, (blitter_colormode & 0x0F));
  1295. break;
  1296. }
  1297. case MNT_BASE_RECTOP + 0x2a: {
  1298. // DrawLine
  1299. uint8_t draw_mode = blitter_colormode >> 8;
  1300. set_fb((uint32_t*) ((u32) framebuffer + blitter_dst_offset),
  1301. blitter_dst_pitch);
  1302. // rect_x3 contains the pattern. if all bits are set for both the mask and the pattern,
  1303. // there's no point in passing non-essential data to the pattern/mask aware function.
  1304. if (rect_x3 == 0xFFFF && zdata == 0xFF)
  1305. draw_line_solid(rect_x1, rect_y1, rect_x2, rect_y2,
  1306. blitter_user1, rect_rgb,
  1307. (blitter_colormode & 0x0F));
  1308. else
  1309. draw_line(rect_x1, rect_y1, rect_x2, rect_y2,
  1310. blitter_user1, rect_x3, rect_y3, rect_rgb,
  1311. rect_rgb2, (blitter_colormode & 0x0F), zdata,
  1312. draw_mode);
  1313. break;
  1314. }
  1315. case MNT_BASE_RECTOP + 0x2e:
  1316. // InvertRect
  1317. set_fb((uint32_t*) ((u32) framebuffer + blitter_dst_offset),
  1318. blitter_dst_pitch);
  1319. invert_rect(rect_x1, rect_y1, rect_x2, rect_y2,
  1320. zdata & 0xFF, blitter_colormode);
  1321. break;
  1322. // Ethernet
  1323. case MNT_BASE_ETH_TX:
  1324. ethernet_send_result = ethernet_send_frame(zdata);
  1325. //printf("SEND frame sz: %ld res: %d\n",zdata,ethernet_send_result);
  1326. break;
  1327. case MNT_BASE_ETH_RX:
  1328. //printf("RECV eth frame sz: %ld\n",zdata);
  1329. ethernet_receive_frame();
  1330. break;
  1331. case MNT_BASE_ETH_MAC_HI: {
  1332. uint8_t* mac = ethernet_get_mac_address_ptr();
  1333. mac[0] = (zdata & 0xff00) >> 8;
  1334. mac[1] = (zdata & 0x00ff);
  1335. break;
  1336. }
  1337. case MNT_BASE_ETH_MAC_HI2: {
  1338. uint8_t* mac = ethernet_get_mac_address_ptr();
  1339. mac[2] = (zdata & 0xff00) >> 8;
  1340. mac[3] = (zdata & 0x00ff);
  1341. break;
  1342. }
  1343. case MNT_BASE_ETH_MAC_LO: {
  1344. uint8_t* mac = ethernet_get_mac_address_ptr();
  1345. mac[4] = (zdata & 0xff00) >> 8;
  1346. mac[5] = (zdata & 0x00ff);
  1347. ethernet_update_mac_address();
  1348. break;
  1349. }
  1350. case MNT_BASE_USBBLK_TX_HI: {
  1351. usb_storage_write_block = ((u32) zdata) << 16;
  1352. break;
  1353. }
  1354. case MNT_BASE_USBBLK_TX_LO: {
  1355. usb_storage_write_block |= zdata;
  1356. if (usb_storage_available) {
  1357. usb_status = zz_usb_write_blocks(0, usb_storage_write_block, usb_read_write_num_blocks, (void*)USB_BLOCK_STORAGE_ADDRESS);
  1358. } else {
  1359. printf("[USB] TX but no storage available!\n");
  1360. }
  1361. break;
  1362. }
  1363. case MNT_BASE_USBBLK_RX_HI: {
  1364. usb_storage_read_block = ((u32) zdata) << 16;
  1365. break;
  1366. }
  1367. case MNT_BASE_USBBLK_RX_LO: {
  1368. usb_storage_read_block |= zdata;
  1369. if (usb_storage_available) {
  1370. usb_status = zz_usb_read_blocks(0, usb_storage_read_block, usb_read_write_num_blocks, (void*)USB_BLOCK_STORAGE_ADDRESS);
  1371. } else {
  1372. printf("[USB] RX but no storage available!\n");
  1373. }
  1374. break;
  1375. }
  1376. case MNT_BASE_USB_STATUS: {
  1377. //printf("[USB] write to status/blocknum register: %d\n", zdata);
  1378. if (zdata==0) {
  1379. // reset USB
  1380. // FIXME memory leaks?
  1381. //usb_storage_available = zz_usb_init();
  1382. } else {
  1383. // set number of blocks to read/write at once
  1384. usb_read_write_num_blocks = zdata;
  1385. }
  1386. break;
  1387. }
  1388. case MNT_BASE_USB_BUFSEL: {
  1389. //printf("[USB] select buffer: %d\n", zdata);
  1390. usb_selected_buffer_block = zdata;
  1391. break;
  1392. }
  1393. case MNT_BASE_DEBUG: {
  1394. debug_lowlevel = zdata;
  1395. break;
  1396. }
  1397. // ARM core 2 execution
  1398. case MNT_BASE_RUN_HI:
  1399. arm_run_address = ((u32) zdata) << 16;
  1400. break;
  1401. case MNT_BASE_RUN_LO:
  1402. // TODO checksum?
  1403. arm_run_address |= zdata;
  1404. *core1_addr = (uint32_t) core1_loop;
  1405. core1_addr2[0] = 0xe3e0000f; // mvn r0, #15 -- loads 0xfffffff0
  1406. core1_addr2[1] = 0xe590f000; // ldr pc, [r0] -- jumps to the address in that address
  1407. printf("[ARM_RUN] %lx\n", arm_run_address);
  1408. if (arm_run_address > 0) {
  1409. core1_trampoline = (volatile void (*)(
  1410. volatile struct ZZ9K_ENV*)) arm_run_address;
  1411. printf("[ARM_RUN] signaling second core.\n");
  1412. Xil_DCacheFlush();
  1413. Xil_ICacheInvalidate();
  1414. core2_execute = 1;
  1415. Xil_DCacheFlush();
  1416. Xil_ICacheInvalidate();
  1417. } else {
  1418. core1_trampoline = 0;
  1419. core2_execute = 0;
  1420. }
  1421. // FIXME move this out of here
  1422. // sequence to reset cpu1 taken from https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842504/XAPP1079+Latest+Information
  1423. Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
  1424. uint32_t RegVal = Xil_In32(A9_CPU_RST_CTRL);
  1425. RegVal |= A9_RST1_MASK;
  1426. Xil_Out32(A9_CPU_RST_CTRL, RegVal);
  1427. RegVal |= A9_CLKSTOP1_MASK;
  1428. Xil_Out32(A9_CPU_RST_CTRL, RegVal);
  1429. RegVal &= ~A9_RST1_MASK;
  1430. Xil_Out32(A9_CPU_RST_CTRL, RegVal);
  1431. RegVal &= ~A9_CLKSTOP1_MASK;
  1432. Xil_Out32(A9_CPU_RST_CTRL, RegVal);
  1433. Xil_Out32(XSLCR_LOCK_ADDR, XSLCR_LOCK_CODE);
  1434. dmb();
  1435. dsb();
  1436. isb();
  1437. asm("sev");
  1438. break;
  1439. case MNT_BASE_RUN_ARGC:
  1440. arm_run_env.argc = zdata;
  1441. break;
  1442. case MNT_BASE_RUN_ARG0:
  1443. arm_run_env.argv[0] = ((u32) zdata) << 16;
  1444. break;
  1445. case MNT_BASE_RUN_ARG1:
  1446. arm_run_env.argv[0] |= zdata;
  1447. printf("ARG0 set: %lx\n", arm_run_env.argv[0]);
  1448. break;
  1449. case MNT_BASE_RUN_ARG2:
  1450. arm_run_env.argv[1] = ((u32) zdata) << 16;
  1451. break;
  1452. case MNT_BASE_RUN_ARG3:
  1453. arm_run_env.argv[1] |= zdata;
  1454. printf("ARG1 set: %lx\n", arm_run_env.argv[1]);
  1455. break;
  1456. case MNT_BASE_RUN_ARG4:
  1457. arm_run_env.argv[2] = ((u32) zdata) << 16;
  1458. break;
  1459. case MNT_BASE_RUN_ARG5:
  1460. arm_run_env.argv[2] |= zdata;
  1461. printf("ARG2 set: %lx\n", arm_run_env.argv[2]);
  1462. break;
  1463. case MNT_BASE_RUN_ARG6:
  1464. arm_run_env.argv[3] = ((u32) zdata) << 16;
  1465. break;
  1466. case MNT_BASE_RUN_ARG7:
  1467. arm_run_env.argv[3] |= zdata;
  1468. printf("ARG3 set: %lx\n", arm_run_env.argv[3]);
  1469. break;
  1470. case MNT_BASE_EVENT_CODE:
  1471. arm_app_input_event_code = zdata;
  1472. arm_app_input_event_serial++;
  1473. arm_app_input_event_ack = 0;
  1474. break;
  1475. }
  1476. }
  1477. // ack the write, set bit 31 in register 0
  1478. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG0, (1 << 31));
  1479. need_req_ack = 1;
  1480. } else if (readreq) {
  1481. uint32_t zaddr = mntzorro_read(MNTZ_BASE_ADDR, MNTZORRO_REG0);
  1482. if (debug_lowlevel) {
  1483. printf("READ: %08lx\n",zaddr);
  1484. }
  1485. u32 z3 = (zstate_raw & (1 << 25)); // TODO cache
  1486. if (zaddr > 0x10000000) {
  1487. printf("ERRR: illegal address %08lx\n", zaddr);
  1488. }
  1489. if (zaddr >= MNT_FB_BASE || zaddr >= MNT_REG_BASE + 0x2000) {
  1490. u8* ptr = mem;
  1491. if (zaddr >= MNT_FB_BASE) {
  1492. // read from framebuffer / generic memory
  1493. ptr = mem + zaddr - MNT_FB_BASE;
  1494. } else if (zaddr < MNT_REG_BASE + 0x8000) {
  1495. // 0x2000-0x7fff: FIXME: waste of address space
  1496. // read from ethernet RX frame
  1497. // disable INT6 interrupt
  1498. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG2, (1 << 30) | 0);
  1499. ptr = (u8*) (ethernet_current_receive_ptr() + zaddr - (MNT_REG_BASE + 0x2000));
  1500. } else if (zaddr < MNT_REG_BASE + 0xa000) {
  1501. // 0x8000-0x9fff: read from TX frame (unusual)
  1502. ptr = (u8*) (TX_FRAME_ADDRESS + zaddr - (MNT_REG_BASE + 0x8000));
  1503. //printf("ETXF read: %08lx\n", (u32) ptr);
  1504. } else if (zaddr < MNT_REG_BASE + 0x10000) {
  1505. // 0xa000-0xafff: read from block device (usb storage)
  1506. // TODO: this should be moved to DMA space?
  1507. ptr = (u8*) (USB_BLOCK_STORAGE_ADDRESS + zaddr - (MNT_REG_BASE + 0xa000) + usb_selected_buffer_block * 512);
  1508. }
  1509. if (z3) {
  1510. u32 b1 = ptr[0] << 24;
  1511. u32 b2 = ptr[1] << 16;
  1512. u32 b3 = ptr[2] << 8;
  1513. u32 b4 = ptr[3];
  1514. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG1,
  1515. b1 | b2 | b3 | b4);
  1516. } else {
  1517. u16 ubyte = ptr[0] << 8;
  1518. u16 lbyte = ptr[1];
  1519. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG1,
  1520. ubyte | lbyte);
  1521. }
  1522. } else if (zaddr >= MNT_REG_BASE) {
  1523. // read ARM "register"
  1524. uint32_t data = 0;
  1525. uint32_t zaddr32 = zaddr & 0xffffffc;
  1526. if (zaddr32 == MNT_BASE_EVENT_SERIAL) {
  1527. data = (arm_app_output_event_serial << 16)
  1528. | arm_app_output_event_code;
  1529. arm_app_output_event_ack = 1;
  1530. } else if (zaddr32 == MNT_BASE_ETH_MAC_HI) {
  1531. uint8_t* mac = ethernet_get_mac_address_ptr();
  1532. data = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3];
  1533. } else if (zaddr32 == MNT_BASE_ETH_MAC_LO) {
  1534. uint8_t* mac = ethernet_get_mac_address_ptr();
  1535. data = mac[4] << 24 | mac[5] << 16;
  1536. } else if (zaddr32 == MNT_BASE_ETH_TX) {
  1537. // FIXME this is probably wrong (doesn't need swapping?)
  1538. data = (ethernet_send_result & 0xff) << 24
  1539. | (ethernet_send_result & 0xff00) << 16;
  1540. } else if (zaddr32 == MNT_BASE_FW_VERSION) {
  1541. data = (REVISION_MAJOR << 24 | REVISION_MINOR << 16);
  1542. } else if (zaddr32 == MNT_BASE_USB_STATUS) {
  1543. data = usb_status << 16;
  1544. } else if (zaddr32 == MNT_BASE_USB_CAPACITY) {
  1545. if (usb_storage_available) {
  1546. printf("[USB] query capacity: %lx\n",zz_usb_storage_capacity(0));
  1547. data = zz_usb_storage_capacity(0);
  1548. } else {
  1549. printf("[USB] query capacity: no device.\n");
  1550. data = 0;
  1551. }
  1552. }
  1553. if (z3) {
  1554. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG1, data);
  1555. } else {
  1556. if (zaddr & 2) {
  1557. // lower 16 bit
  1558. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG1, data);
  1559. } else {
  1560. // upper 16 bit
  1561. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG1, data >> 16);
  1562. }
  1563. }
  1564. }
  1565. // ack the read, set bit 30 in register 0
  1566. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG0, (1 << 30));
  1567. need_req_ack = 2;
  1568. } else {
  1569. // there are no read/write requests, we can do other housekeeping
  1570. // we flush the cache at regular intervals to avoid too much visible cache activity on the screen
  1571. // FIXME make this adjustable for user
  1572. if (cache_counter > 25000) {
  1573. Xil_DCacheFlush();
  1574. cache_counter = 0;
  1575. }
  1576. cache_counter++;
  1577. int videocap_enabled = (zstate_raw & (1 << 23));
  1578. int videocap_ntsc = (zstate_raw & (1<<22));
  1579. // FIXME magic constant
  1580. if (videocap_enabled && framebuffer_pan_offset >= 0xe00000) {
  1581. if (sprite_enabled) {
  1582. sprite_hide();
  1583. }
  1584. if (!videocap_enabled_old) {
  1585. videocap_area_clear();
  1586. videocap_ntsc_old = 0;
  1587. }
  1588. if (videocap_ntsc != videocap_ntsc_old) {
  1589. // change between ntsc+pal
  1590. videocap_area_clear();
  1591. if (videocap_ntsc) {
  1592. framebuffer_pan_offset = 0x00e00000;
  1593. video_mode_init(ZZVMODE_720x480, 2, MNTVA_COLOR_32BIT);
  1594. } else {
  1595. // PAL
  1596. reset_default_videocap_pan();
  1597. framebuffer_pan_offset = default_pan_offset;
  1598. video_mode_init(videocap_video_mode, 2, MNTVA_COLOR_32BIT);
  1599. }
  1600. }
  1601. videocap_ntsc_old = videocap_ntsc;
  1602. int interlace = !!(zstate_raw & (1 << 24));
  1603. if (interlace != interlace_old) {
  1604. // interlace has changed, we need to reconfigure vdma for the new screen height
  1605. vmode_vdiv = 2;
  1606. if (interlace) {
  1607. vmode_vdiv = 1;
  1608. }
  1609. videocap_area_clear();
  1610. init_vdma(vmode_hsize, vmode_vsize, 1, vmode_vdiv);
  1611. video_formatter_valign();
  1612. printf("videocap interlace mode changed to %d.\n", interlace);
  1613. // avoid multiple video re-alignments in the same cycle
  1614. request_video_align = 0;
  1615. }
  1616. interlace_old = interlace;
  1617. }
  1618. else {
  1619. if(!sprite_enabled)
  1620. sprite_enabled = 1;
  1621. }
  1622. if (videocap_enabled_old != videocap_enabled) {
  1623. if (framebuffer_pan_offset >= 0xe00000) {
  1624. videocap_area_clear();
  1625. }
  1626. videocap_enabled_old = videocap_enabled;
  1627. }
  1628. if (zstate == 0) {
  1629. // RESET
  1630. handle_amiga_reset();
  1631. }
  1632. }
  1633. // re-init VDMA if requested
  1634. if (request_video_align) {
  1635. vblank = (zstate_raw & (1<<21));
  1636. if (vblank) {
  1637. request_video_align = 0;
  1638. init_vdma(vmode_hsize, vmode_vsize, vmode_hdiv, vmode_vdiv);
  1639. }
  1640. }
  1641. // TODO: potential hang, timeout?
  1642. if (need_req_ack) {
  1643. while (1) {
  1644. // 1. fpga needs to respond to flag bit 31 or 30 going high (signals request fulfilled)
  1645. // 2. it does that by clearing the request bit
  1646. // 3. we read register 3 until request bit (31:write, 30:read) goes to 0 again
  1647. //
  1648. u32 zstate = mntzorro_read(MNTZ_BASE_ADDR, MNTZORRO_REG3);
  1649. u32 writereq = (zstate & (1 << 31));
  1650. u32 readreq = (zstate & (1 << 30));
  1651. if (need_req_ack == 1 && !writereq)
  1652. break;
  1653. if (need_req_ack == 2 && !readreq)
  1654. break;
  1655. if ((zstate & 0xff) == 0)
  1656. break; // reset
  1657. }
  1658. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG0, 0);
  1659. need_req_ack = 0;
  1660. }
  1661. // check for queued up ethernet frames
  1662. int ethernet_backlog = ethernet_get_backlog();
  1663. if (ethernet_backlog > 0 && backlog_nag_counter > 5000) {
  1664. // interrupt amiga (trigger int6/2)
  1665. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG2, (1 << 30) | 1);
  1666. usleep(1);
  1667. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG2, (1 << 30) | 0);
  1668. backlog_nag_counter = 0;
  1669. }
  1670. if (interrupt_enabled && ethernet_backlog > 0) {
  1671. backlog_nag_counter++;
  1672. }
  1673. }
  1674. cleanup_platform();
  1675. return 0;
  1676. }
  1677. void arm_exception_handler(void *callback) {
  1678. printf("arm_exception_handler()!\n");
  1679. while (1) {
  1680. }
  1681. }
  1682. void arm_exception_handler_illinst(void *callback) {
  1683. printf("arm_exception_handler_illinst()!\n");
  1684. while (1) {
  1685. }
  1686. }