Firmware for MNT ZZ9000 graphics and ARM coprocessor card for Amiga computers.
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ehci.h 11KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*-
  3. * Copyright (c) 2007-2008, Juniper Networks, Inc.
  4. * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
  5. * All rights reserved.
  6. */
  7. #ifndef USB_EHCI_H
  8. #define USB_EHCI_H
  9. #include <stdbool.h>
  10. #include "usb.h"
  11. #include "generic-phy.h"
  12. #include "io.h"
  13. /* Section 2.2.3 - N_PORTS */
  14. #define MAX_HC_PORTS 15
  15. /*
  16. * Register Space.
  17. */
  18. struct ehci_hccr {
  19. uint32_t cr_capbase;
  20. #define HC_LENGTH(p) (((p) >> 0) & 0x00ff)
  21. #define HC_VERSION(p) (((p) >> 16) & 0xffff)
  22. uint32_t cr_hcsparams;
  23. #define HCS_PPC(p) ((p) & (1 << 4))
  24. #define HCS_INDICATOR(p) ((p) & (1 << 16)) /* Port indicators */
  25. #define HCS_N_PORTS(p) (((p) >> 0) & 0xf)
  26. uint32_t cr_hccparams;
  27. uint8_t cr_hcsp_portrt[8];
  28. } __attribute__ ((packed, aligned(4)));
  29. struct ehci_hcor {
  30. uint32_t or_usbcmd;
  31. #define CMD_PARK (1 << 11) /* enable "park" */
  32. #define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */
  33. #define CMD_LRESET (1 << 7) /* partial reset */
  34. #define CMD_IAAD (1 << 6) /* "doorbell" interrupt */
  35. #define CMD_ASE (1 << 5) /* async schedule enable */
  36. #define CMD_PSE (1 << 4) /* periodic schedule enable */
  37. #define CMD_RESET (1 << 1) /* reset HC not bus */
  38. #define CMD_RUN (1 << 0) /* start/stop HC */
  39. uint32_t or_usbsts;
  40. #define STS_ASS (1 << 15)
  41. #define STS_PSS (1 << 14)
  42. #define STS_HALT (1 << 12)
  43. uint32_t or_usbintr;
  44. #define INTR_UE (1 << 0) /* USB interrupt enable */
  45. #define INTR_UEE (1 << 1) /* USB error interrupt enable */
  46. #define INTR_PCE (1 << 2) /* Port change detect enable */
  47. #define INTR_SEE (1 << 4) /* system error enable */
  48. #define INTR_AAE (1 << 5) /* Interrupt on async adavance enable */
  49. uint32_t or_frindex;
  50. uint32_t or_ctrldssegment;
  51. uint32_t or_periodiclistbase;
  52. uint32_t or_asynclistaddr;
  53. uint32_t _reserved_0_;
  54. uint32_t or_burstsize;
  55. uint32_t or_txfilltuning;
  56. #define TXFIFO_THRESH_MASK (0x3f << 16)
  57. #define TXFIFO_THRESH(p) ((p & 0x3f) << 16)
  58. uint32_t _reserved_1_[6];
  59. uint32_t or_configflag;
  60. #define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
  61. uint32_t or_portsc[MAX_HC_PORTS];
  62. #define PORTSC_PSPD(x) (((x) >> 26) & 0x3)
  63. #define PORTSC_PSPD_FS 0x0
  64. #define PORTSC_PSPD_LS 0x1
  65. #define PORTSC_PSPD_HS 0x2
  66. #define PORTSC_FSL_PFSC (1<<24) /* PFSC bit to disable HS chirping */
  67. uint32_t or_systune;
  68. } __attribute__ ((packed, aligned(4)));
  69. #define USBMODE 0x68 /* USB Device mode */
  70. #define USBMODE_SDIS (1 << 3) /* Stream disable */
  71. #define USBMODE_BE (1 << 2) /* BE/LE endiannes select */
  72. #define USBMODE_CM_HC (3 << 0) /* host controller mode */
  73. #define USBMODE_CM_IDLE (0 << 0) /* idle state */
  74. /* Interface descriptor */
  75. struct usb_linux_interface_descriptor {
  76. unsigned char bLength;
  77. unsigned char bDescriptorType;
  78. unsigned char bInterfaceNumber;
  79. unsigned char bAlternateSetting;
  80. unsigned char bNumEndpoints;
  81. unsigned char bInterfaceClass;
  82. unsigned char bInterfaceSubClass;
  83. unsigned char bInterfaceProtocol;
  84. unsigned char iInterface;
  85. } __attribute__ ((packed));
  86. /* Configuration descriptor information.. */
  87. struct usb_linux_config_descriptor {
  88. unsigned char bLength;
  89. unsigned char bDescriptorType;
  90. unsigned short wTotalLength;
  91. unsigned char bNumInterfaces;
  92. unsigned char bConfigurationValue;
  93. unsigned char iConfiguration;
  94. unsigned char bmAttributes;
  95. unsigned char MaxPower;
  96. } __attribute__ ((packed));
  97. #if defined CONFIG_EHCI_DESC_BIG_ENDIAN
  98. #define ehci_readl(x) be32_to_cpu(__raw_readl(x))
  99. #define ehci_writel(a, b) __raw_writel(cpu_to_be32(b), a)
  100. #else
  101. #define ehci_readl(x) readl(x)
  102. #define ehci_writel(a, b) writel(b, a)
  103. #endif
  104. #if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
  105. #define hc32_to_cpu(x) be32_to_cpu((x))
  106. #define cpu_to_hc32(x) cpu_to_be32((x))
  107. #else
  108. #define hc32_to_cpu(x) le32_to_cpu((x))
  109. #define cpu_to_hc32(x) cpu_to_le32((x))
  110. #endif
  111. #define EHCI_PS_WKOC_E (1 << 22) /* RW wake on over current */
  112. #define EHCI_PS_WKDSCNNT_E (1 << 21) /* RW wake on disconnect */
  113. #define EHCI_PS_WKCNNT_E (1 << 20) /* RW wake on connect */
  114. #define EHCI_PS_PO (1 << 13) /* RW port owner */
  115. #define EHCI_PS_PP (1 << 12) /* RW,RO port power */
  116. #define EHCI_PS_LS (3 << 10) /* RO line status */
  117. #define EHCI_PS_PR (1 << 8) /* RW port reset */
  118. #define EHCI_PS_SUSP (1 << 7) /* RW suspend */
  119. #define EHCI_PS_FPR (1 << 6) /* RW force port resume */
  120. #define EHCI_PS_OCC (1 << 5) /* RWC over current change */
  121. #define EHCI_PS_OCA (1 << 4) /* RO over current active */
  122. #define EHCI_PS_PEC (1 << 3) /* RWC port enable change */
  123. #define EHCI_PS_PE (1 << 2) /* RW port enable */
  124. #define EHCI_PS_CSC (1 << 1) /* RWC connect status change */
  125. #define EHCI_PS_CS (1 << 0) /* RO connect status */
  126. #define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
  127. #define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == (1 << 10))
  128. /*
  129. * Schedule Interface Space.
  130. *
  131. * IMPORTANT: Software must ensure that no interface data structure
  132. * reachable by the EHCI host controller spans a 4K page boundary!
  133. *
  134. * Periodic transfers (i.e. isochronous and interrupt transfers) are
  135. * not supported.
  136. */
  137. /* Queue Element Transfer Descriptor (qTD). */
  138. struct qTD {
  139. /* this part defined by EHCI spec */
  140. uint32_t qt_next; /* see EHCI 3.5.1 */
  141. #define QT_NEXT_TERMINATE 1
  142. uint32_t qt_altnext; /* see EHCI 3.5.2 */
  143. uint32_t qt_token; /* see EHCI 3.5.3 */
  144. #define QT_TOKEN_DT(x) (((x) & 0x1) << 31) /* Data Toggle */
  145. #define QT_TOKEN_GET_DT(x) (((x) >> 31) & 0x1)
  146. #define QT_TOKEN_TOTALBYTES(x) (((x) & 0x7fff) << 16) /* Total Bytes to Transfer */
  147. #define QT_TOKEN_GET_TOTALBYTES(x) (((x) >> 16) & 0x7fff)
  148. #define QT_TOKEN_IOC(x) (((x) & 0x1) << 15) /* Interrupt On Complete */
  149. #define QT_TOKEN_CPAGE(x) (((x) & 0x7) << 12) /* Current Page */
  150. #define QT_TOKEN_CERR(x) (((x) & 0x3) << 10) /* Error Counter */
  151. #define QT_TOKEN_PID(x) (((x) & 0x3) << 8) /* PID Code */
  152. #define QT_TOKEN_PID_OUT 0x0
  153. #define QT_TOKEN_PID_IN 0x1
  154. #define QT_TOKEN_PID_SETUP 0x2
  155. #define QT_TOKEN_STATUS(x) (((x) & 0xff) << 0) /* Status */
  156. #define QT_TOKEN_GET_STATUS(x) (((x) >> 0) & 0xff)
  157. #define QT_TOKEN_STATUS_ACTIVE 0x80
  158. #define QT_TOKEN_STATUS_HALTED 0x40
  159. #define QT_TOKEN_STATUS_DATBUFERR 0x20
  160. #define QT_TOKEN_STATUS_BABBLEDET 0x10
  161. #define QT_TOKEN_STATUS_XACTERR 0x08
  162. #define QT_TOKEN_STATUS_MISSEDUFRAME 0x04
  163. #define QT_TOKEN_STATUS_SPLITXSTATE 0x02
  164. #define QT_TOKEN_STATUS_PERR 0x01
  165. #define QT_BUFFER_CNT 5
  166. uint32_t qt_buffer[QT_BUFFER_CNT]; /* see EHCI 3.5.4 */
  167. uint32_t qt_buffer_hi[QT_BUFFER_CNT]; /* Appendix B */
  168. /* pad struct for 32 byte alignment */
  169. uint32_t unused[3];
  170. };
  171. #define EHCI_PAGE_SIZE 4096
  172. /* Queue Head (QH). */
  173. struct QH {
  174. uint32_t qh_link;
  175. #define QH_LINK_TERMINATE 1
  176. #define QH_LINK_TYPE_ITD 0
  177. #define QH_LINK_TYPE_QH 2
  178. #define QH_LINK_TYPE_SITD 4
  179. #define QH_LINK_TYPE_FSTN 6
  180. uint32_t qh_endpt1;
  181. #define QH_ENDPT1_RL(x) (((x) & 0xf) << 28) /* NAK Count Reload */
  182. #define QH_ENDPT1_C(x) (((x) & 0x1) << 27) /* Control Endpoint Flag */
  183. #define QH_ENDPT1_MAXPKTLEN(x) (((x) & 0x7ff) << 16) /* Maximum Packet Length */
  184. #define QH_ENDPT1_H(x) (((x) & 0x1) << 15) /* Head of Reclamation List Flag */
  185. #define QH_ENDPT1_DTC(x) (((x) & 0x1) << 14) /* Data Toggle Control */
  186. #define QH_ENDPT1_DTC_IGNORE_QTD_TD 0x0
  187. #define QH_ENDPT1_DTC_DT_FROM_QTD 0x1
  188. #define QH_ENDPT1_EPS(x) (((x) & 0x3) << 12) /* Endpoint Speed */
  189. #define QH_ENDPT1_EPS_FS 0x0
  190. #define QH_ENDPT1_EPS_LS 0x1
  191. #define QH_ENDPT1_EPS_HS 0x2
  192. #define QH_ENDPT1_ENDPT(x) (((x) & 0xf) << 8) /* Endpoint Number */
  193. #define QH_ENDPT1_I(x) (((x) & 0x1) << 7) /* Inactivate on Next Transaction */
  194. #define QH_ENDPT1_DEVADDR(x) (((x) & 0x7f) << 0) /* Device Address */
  195. uint32_t qh_endpt2;
  196. #define QH_ENDPT2_MULT(x) (((x) & 0x3) << 30) /* High-Bandwidth Pipe Multiplier */
  197. #define QH_ENDPT2_PORTNUM(x) (((x) & 0x7f) << 23) /* Port Number */
  198. #define QH_ENDPT2_HUBADDR(x) (((x) & 0x7f) << 16) /* Hub Address */
  199. #define QH_ENDPT2_UFCMASK(x) (((x) & 0xff) << 8) /* Split Completion Mask */
  200. #define QH_ENDPT2_UFSMASK(x) (((x) & 0xff) << 0) /* Interrupt Schedule Mask */
  201. uint32_t qh_curtd;
  202. struct qTD qh_overlay;
  203. /*
  204. * Add dummy fill value to make the size of this struct
  205. * aligned to 32 bytes
  206. */
  207. union {
  208. uint32_t fill[4];
  209. void *buffer;
  210. };
  211. };
  212. /* Tweak flags for EHCI, used to control operation */
  213. enum {
  214. /* don't use or_configflag in init */
  215. EHCI_TWEAK_NO_INIT_CF = 1 << 0,
  216. };
  217. struct ehci_ctrl;
  218. struct ehci_ops {
  219. void (*set_usb_mode)(struct ehci_ctrl *ctrl);
  220. int (*get_port_speed)(struct ehci_ctrl *ctrl, uint32_t reg);
  221. void (*powerup_fixup)(struct ehci_ctrl *ctrl, uint32_t *status_reg,
  222. uint32_t *reg);
  223. uint32_t *(*get_portsc_register)(struct ehci_ctrl *ctrl, int port);
  224. int (*init_after_reset)(struct ehci_ctrl *ctrl);
  225. };
  226. struct ehci_ctrl {
  227. enum usb_init_type init;
  228. struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
  229. struct ehci_hcor *hcor;
  230. int rootdev;
  231. uint16_t portreset;
  232. struct QH qh_list __attribute__((aligned(USB_DMA_MINALIGN)));
  233. struct QH periodic_queue __attribute__((aligned(USB_DMA_MINALIGN)));
  234. uint32_t *periodic_list;
  235. int periodic_schedules;
  236. int ntds;
  237. bool has_fsl_erratum_a005275; /* Freescale HS silicon quirk */
  238. struct ehci_ops ops;
  239. void *priv; /* client's private data */
  240. };
  241. // FIXME
  242. struct zynq_ehci_priv {
  243. struct ehci_ctrl ehcictrl;
  244. struct usb_ehci *ehci;
  245. };
  246. int ehci_zynq_probe(struct zynq_ehci_priv *priv);
  247. /**
  248. * ehci_set_controller_info() - Set up private data for the controller
  249. *
  250. * This function can be called in ehci_hcd_init() to tell the EHCI layer
  251. * about the controller's private data pointer. Then in the above functions
  252. * this can be accessed given the struct ehci_ctrl pointer. Also special
  253. * EHCI operation methods can be provided if required
  254. *
  255. * @index: Controller number to set
  256. * @priv: Controller pointer
  257. * @ops: Controller operations, or NULL to use default
  258. */
  259. void ehci_set_controller_priv(int index, void *priv,
  260. const struct ehci_ops *ops);
  261. /**
  262. * ehci_get_controller_priv() - Get controller private data
  263. *
  264. * @index Controller number to get
  265. * @return controller pointer for this index
  266. */
  267. void *ehci_get_controller_priv(int index);
  268. /* Low level init functions */
  269. int ehci_hcd_init(int index, enum usb_init_type init,
  270. struct ehci_hccr **hccr, struct ehci_hcor **hcor);
  271. int ehci_hcd_stop(int index);
  272. int ehci_register(struct ehci_ctrl *ctrl, struct ehci_hccr *hccr,
  273. struct ehci_hcor *hcor, const struct ehci_ops *ops,
  274. unsigned int tweaks, enum usb_init_type init);
  275. int ehci_deregister(struct udevice *dev);
  276. extern struct dm_usb_ops ehci_usb_ops;
  277. /* EHCI PHY functions */
  278. int ehci_setup_phy(struct udevice *dev, struct phy *phy, int index);
  279. int ehci_shutdown_phy(struct udevice *dev, struct phy *phy);
  280. #endif /* USB_EHCI_H */