Firmware for MNT ZZ9000 graphics and ARM coprocessor card for Amiga computers.
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ehci-hcd.c 45KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*-
  3. * Copyright (c) 2007-2008, Juniper Networks, Inc. */
  4. #include <errno.h>
  5. #include <asm/byteorder.h>
  6. #include "usb.h"
  7. #include "io.h"
  8. #include <malloc.h>
  9. #include <stdio.h>
  10. //#include <watchdog.h>
  11. #include <xil_cache.h>
  12. #include <string.h>
  13. #include <sleep.h>
  14. #include "ehci.h"
  15. #include "memalign.h"
  16. void flush_dcache_range(unsigned long start, unsigned long stop) {
  17. Xil_DCacheFlushRange(start, stop-start);
  18. }
  19. void invalidate_dcache_range(unsigned long start, unsigned long stop) {
  20. Xil_DCacheInvalidateRange(start, stop-start);
  21. }
  22. uint32_t virt_to_phys(void* addr) {
  23. return (uint32_t)addr;
  24. }
  25. // FIXME
  26. int tmr=0;
  27. void udelay(int us) {
  28. usleep(us);
  29. }
  30. void mdelay(int ms) {
  31. usleep(1000*ms);
  32. }
  33. int get_timer(int i) {
  34. mdelay(1);
  35. return tmr++;
  36. }
  37. #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
  38. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  39. #endif
  40. /*
  41. * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt.
  42. * Let's time out after 8 to have a little safety margin on top of that.
  43. */
  44. #define HCHALT_TIMEOUT (8 * 1000)
  45. static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
  46. static struct descriptor {
  47. struct usb_hub_descriptor hub;
  48. struct usb_device_descriptor device;
  49. struct usb_linux_config_descriptor config;
  50. struct usb_linux_interface_descriptor interface;
  51. struct usb_endpoint_descriptor endpoint;
  52. } __attribute__ ((packed)) descriptor = {
  53. {
  54. 0x8, /* bDescLength */
  55. 0x29, /* bDescriptorType: hub descriptor */
  56. 2, /* bNrPorts -- runtime modified */
  57. 0, /* wHubCharacteristics */
  58. 10, /* bPwrOn2PwrGood */
  59. 0, /* bHubCntrCurrent */
  60. { /* Device removable */
  61. } /* at most 7 ports! XXX */
  62. },
  63. {
  64. 0x12, /* bLength */
  65. 1, /* bDescriptorType: UDESC_DEVICE */
  66. cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
  67. 9, /* bDeviceClass: UDCLASS_HUB */
  68. 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
  69. 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
  70. 64, /* bMaxPacketSize: 64 bytes */
  71. 0x0000, /* idVendor */
  72. 0x0000, /* idProduct */
  73. cpu_to_le16(0x0100), /* bcdDevice */
  74. 1, /* iManufacturer */
  75. 2, /* iProduct */
  76. 0, /* iSerialNumber */
  77. 1 /* bNumConfigurations: 1 */
  78. },
  79. {
  80. 0x9,
  81. 2, /* bDescriptorType: UDESC_CONFIG */
  82. cpu_to_le16(0x19),
  83. 1, /* bNumInterface */
  84. 1, /* bConfigurationValue */
  85. 0, /* iConfiguration */
  86. 0x40, /* bmAttributes: UC_SELF_POWER */
  87. 0 /* bMaxPower */
  88. },
  89. {
  90. 0x9, /* bLength */
  91. 4, /* bDescriptorType: UDESC_INTERFACE */
  92. 0, /* bInterfaceNumber */
  93. 0, /* bAlternateSetting */
  94. 1, /* bNumEndpoints */
  95. 9, /* bInterfaceClass: UICLASS_HUB */
  96. 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
  97. 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
  98. 0 /* iInterface */
  99. },
  100. {
  101. 0x7, /* bLength */
  102. 5, /* bDescriptorType: UDESC_ENDPOINT */
  103. 0x81, /* bEndpointAddress:
  104. * UE_DIR_IN | EHCI_INTR_ENDPT
  105. */
  106. 3, /* bmAttributes: UE_INTERRUPT */
  107. 8, /* wMaxPacketSize */
  108. 255 /* bInterval */
  109. },
  110. };
  111. #if defined(CONFIG_EHCI_IS_TDI)
  112. #define ehci_is_TDI() (1)
  113. #else
  114. #define ehci_is_TDI() (0)
  115. #endif
  116. static struct ehci_ctrl *ehci_get_ctrl(struct usb_device *udev)
  117. {
  118. return udev->controller;
  119. }
  120. static int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg)
  121. {
  122. return PORTSC_PSPD(reg);
  123. }
  124. static void ehci_set_usbmode(struct ehci_ctrl *ctrl)
  125. {
  126. uint32_t tmp;
  127. uint32_t *reg_ptr;
  128. reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + USBMODE);
  129. tmp = ehci_readl(reg_ptr);
  130. tmp |= USBMODE_CM_HC;
  131. #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
  132. tmp |= USBMODE_BE;
  133. #else
  134. tmp &= ~USBMODE_BE;
  135. #endif
  136. ehci_writel(reg_ptr, tmp);
  137. }
  138. static void ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
  139. uint32_t *reg)
  140. {
  141. mdelay(50); // FIXME
  142. }
  143. static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port)
  144. {
  145. int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
  146. if (port < 0 || port >= max_ports) {
  147. /* Printing the message would cause a scan failure! */
  148. printf("The request port(%u) exceeds maximum port number\n", port);
  149. return NULL;
  150. }
  151. return (uint32_t *)&ctrl->hcor->or_portsc[port];
  152. }
  153. static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
  154. {
  155. uint32_t result;
  156. do {
  157. result = ehci_readl(ptr);
  158. udelay(5);
  159. if (result == ~(uint32_t)0)
  160. return -1;
  161. result &= mask;
  162. if (result == done)
  163. return 0;
  164. usec--;
  165. } while (usec > 0);
  166. return -1;
  167. }
  168. static int ehci_reset(struct ehci_ctrl *ctrl)
  169. {
  170. uint32_t cmd;
  171. int ret = 0;
  172. cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
  173. cmd = (cmd & ~CMD_RUN) | CMD_RESET;
  174. ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
  175. ret = handshake((uint32_t *)&ctrl->hcor->or_usbcmd,
  176. CMD_RESET, 0, 250 * 1000);
  177. if (ret < 0) {
  178. printf("EHCI fail to reset\n");
  179. goto out;
  180. }
  181. if (ehci_is_TDI())
  182. ctrl->ops.set_usb_mode(ctrl);
  183. #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
  184. cmd = ehci_readl(&ctrl->hcor->or_txfilltuning);
  185. cmd &= ~TXFIFO_THRESH_MASK;
  186. cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
  187. ehci_writel(&ctrl->hcor->or_txfilltuning, cmd);
  188. #endif
  189. out:
  190. return ret;
  191. }
  192. static int ehci_shutdown(struct ehci_ctrl *ctrl)
  193. {
  194. int i, ret = 0;
  195. uint32_t cmd, reg;
  196. int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
  197. cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
  198. /* If not run, directly return */
  199. if (!(cmd & CMD_RUN))
  200. return 0;
  201. cmd &= ~(CMD_PSE | CMD_ASE);
  202. ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
  203. ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0,
  204. 100 * 1000);
  205. if (!ret) {
  206. for (i = 0; i < max_ports; i++) {
  207. reg = ehci_readl(&ctrl->hcor->or_portsc[i]);
  208. reg |= EHCI_PS_SUSP;
  209. ehci_writel(&ctrl->hcor->or_portsc[i], reg);
  210. }
  211. cmd &= ~CMD_RUN;
  212. ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
  213. ret = handshake(&ctrl->hcor->or_usbsts, STS_HALT, STS_HALT,
  214. HCHALT_TIMEOUT);
  215. }
  216. if (ret)
  217. puts("EHCI failed to shut down host controller.\n");
  218. return ret;
  219. }
  220. static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
  221. {
  222. uint32_t delta, next;
  223. unsigned long addr = (unsigned long)buf;
  224. int idx;
  225. if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
  226. printf("EHCI-HCD: Misaligned buffer address (%p vs %x)\n", buf, ALIGN(addr, ARCH_DMA_MINALIGN));
  227. flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
  228. idx = 0;
  229. while (idx < QT_BUFFER_CNT) {
  230. td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys((void *)addr));
  231. td->qt_buffer_hi[idx] = 0;
  232. next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
  233. delta = next - addr;
  234. if (delta >= sz)
  235. break;
  236. sz -= delta;
  237. addr = next;
  238. idx++;
  239. }
  240. if (idx == QT_BUFFER_CNT) {
  241. printf("out of buffer pointers (%zu bytes left)\n", sz);
  242. return -1;
  243. }
  244. return 0;
  245. }
  246. static inline u8 ehci_encode_speed(enum usb_device_speed speed)
  247. {
  248. #define QH_HIGH_SPEED 2
  249. #define QH_FULL_SPEED 0
  250. #define QH_LOW_SPEED 1
  251. if (speed == USB_SPEED_HIGH)
  252. return QH_HIGH_SPEED;
  253. if (speed == USB_SPEED_LOW)
  254. return QH_LOW_SPEED;
  255. return QH_FULL_SPEED;
  256. }
  257. static void ehci_update_endpt2_dev_n_port(struct usb_device *udev,
  258. struct QH *qh)
  259. {
  260. uint8_t portnr = 0;
  261. uint8_t hubaddr = 0;
  262. if (udev->speed != USB_SPEED_LOW && udev->speed != USB_SPEED_FULL)
  263. return;
  264. usb_find_usb2_hub_address_port(udev, &hubaddr, &portnr);
  265. qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(portnr) |
  266. QH_ENDPT2_HUBADDR(hubaddr));
  267. }
  268. static int
  269. ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
  270. int length, struct devrequest *req)
  271. {
  272. ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
  273. struct qTD *qtd;
  274. int qtd_count = 0;
  275. int qtd_counter = 0;
  276. volatile struct qTD *vtd;
  277. unsigned long ts;
  278. uint32_t *tdp;
  279. uint32_t endpt, maxpacket, token, usbsts;
  280. uint32_t c, toggle;
  281. uint32_t cmd;
  282. int timeout;
  283. int ret = 0;
  284. struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
  285. //printf("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
  286. // buffer, length, req);
  287. /*if (req != NULL)
  288. printf("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
  289. req->request, req->request,
  290. req->requesttype, req->requesttype,
  291. le16_to_cpu(req->value), le16_to_cpu(req->value),
  292. le16_to_cpu(req->index));*/
  293. #define PKT_ALIGN 512
  294. /*
  295. * The USB transfer is split into qTD transfers. Eeach qTD transfer is
  296. * described by a transfer descriptor (the qTD). The qTDs form a linked
  297. * list with a queue head (QH).
  298. *
  299. * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
  300. * have its beginning in a qTD transfer and its end in the following
  301. * one, so the qTD transfer lengths have to be chosen accordingly.
  302. *
  303. * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
  304. * single pages. The first data buffer can start at any offset within a
  305. * page (not considering the cache-line alignment issues), while the
  306. * following buffers must be page-aligned. There is no alignment
  307. * constraint on the size of a qTD transfer.
  308. */
  309. if (req != NULL)
  310. /* 1 qTD will be needed for SETUP, and 1 for ACK. */
  311. qtd_count += 1 + 1;
  312. if (length > 0 || req == NULL) {
  313. /*
  314. * Determine the qTD transfer size that will be used for the
  315. * data payload (not considering the first qTD transfer, which
  316. * may be longer or shorter, and the final one, which may be
  317. * shorter).
  318. *
  319. * In order to keep each packet within a qTD transfer, the qTD
  320. * transfer size is aligned to PKT_ALIGN, which is a multiple of
  321. * wMaxPacketSize (except in some cases for interrupt transfers,
  322. * see comment in submit_int_msg()).
  323. *
  324. * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
  325. * QT_BUFFER_CNT full pages will be used.
  326. */
  327. int xfr_sz = QT_BUFFER_CNT;
  328. /*
  329. * However, if the input buffer is not aligned to PKT_ALIGN, the
  330. * qTD transfer size will be one page shorter, and the first qTD
  331. * data buffer of each transfer will be page-unaligned.
  332. */
  333. if ((unsigned long)buffer & (PKT_ALIGN - 1))
  334. xfr_sz--;
  335. /* Convert the qTD transfer size to bytes. */
  336. xfr_sz *= EHCI_PAGE_SIZE;
  337. /*
  338. * Approximate by excess the number of qTDs that will be
  339. * required for the data payload. The exact formula is way more
  340. * complicated and saves at most 2 qTDs, i.e. a total of 128
  341. * bytes.
  342. */
  343. qtd_count += 2 + length / xfr_sz;
  344. }
  345. /*
  346. * Threshold value based on the worst-case total size of the allocated qTDs for
  347. * a mass-storage transfer of 65535 blocks of 512 bytes.
  348. */
  349. //#if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
  350. //#warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
  351. //#endif
  352. // FIXME needs 128kB ram?
  353. qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD)); // FIXME dynamic allocation
  354. if (qtd == NULL) {
  355. printf("unable to allocate TDs\n");
  356. return -1;
  357. }
  358. memset(qh, 0, sizeof(struct QH));
  359. memset(qtd, 0, qtd_count * sizeof(*qtd));
  360. toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
  361. /*
  362. * Setup QH (3.6 in ehci-r10.pdf)
  363. *
  364. * qh_link ................. 03-00 H
  365. * qh_endpt1 ............... 07-04 H
  366. * qh_endpt2 ............... 0B-08 H
  367. * - qh_curtd
  368. * qh_overlay.qt_next ...... 13-10 H
  369. * - qh_overlay.qt_altnext
  370. */
  371. qh->qh_link = cpu_to_hc32(virt_to_phys(&ctrl->qh_list) | QH_LINK_TYPE_QH);
  372. c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe);
  373. maxpacket = usb_maxpacket(dev, pipe);
  374. endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
  375. QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
  376. QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
  377. QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
  378. QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
  379. /* Force FS for fsl HS quirk */
  380. if (!ctrl->has_fsl_erratum_a005275)
  381. endpt |= QH_ENDPT1_EPS(ehci_encode_speed(dev->speed));
  382. else
  383. endpt |= QH_ENDPT1_EPS(ehci_encode_speed(QH_FULL_SPEED));
  384. qh->qh_endpt1 = cpu_to_hc32(endpt);
  385. endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
  386. qh->qh_endpt2 = cpu_to_hc32(endpt);
  387. ehci_update_endpt2_dev_n_port(dev, qh);
  388. qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  389. qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  390. tdp = &qh->qh_overlay.qt_next;
  391. if (req != NULL) {
  392. /*
  393. * Setup request qTD (3.5 in ehci-r10.pdf)
  394. *
  395. * qt_next ................ 03-00 H
  396. * qt_altnext ............. 07-04 H
  397. * qt_token ............... 0B-08 H
  398. *
  399. * [ buffer, buffer_hi ] loaded with "req".
  400. */
  401. qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  402. qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  403. token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
  404. QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
  405. QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
  406. QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
  407. qtd[qtd_counter].qt_token = cpu_to_hc32(token);
  408. if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
  409. printf("unable to construct SETUP TD\n");
  410. goto fail;
  411. }
  412. /* Update previous qTD! */
  413. *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
  414. tdp = &qtd[qtd_counter++].qt_next;
  415. toggle = 1;
  416. }
  417. if (length > 0 || req == NULL) {
  418. uint8_t *buf_ptr = buffer;
  419. int left_length = length;
  420. do {
  421. /*
  422. * Determine the size of this qTD transfer. By default,
  423. * QT_BUFFER_CNT full pages can be used.
  424. */
  425. int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
  426. /*
  427. * However, if the input buffer is not page-aligned, the
  428. * portion of the first page before the buffer start
  429. * offset within that page is unusable.
  430. */
  431. xfr_bytes -= (unsigned long)buf_ptr & (EHCI_PAGE_SIZE - 1);
  432. /*
  433. * In order to keep each packet within a qTD transfer,
  434. * align the qTD transfer size to PKT_ALIGN.
  435. */
  436. xfr_bytes &= ~(PKT_ALIGN - 1);
  437. /*
  438. * This transfer may be shorter than the available qTD
  439. * transfer size that has just been computed.
  440. */
  441. xfr_bytes = min(xfr_bytes, left_length);
  442. /*
  443. * Setup request qTD (3.5 in ehci-r10.pdf)
  444. *
  445. * qt_next ................ 03-00 H
  446. * qt_altnext ............. 07-04 H
  447. * qt_token ............... 0B-08 H
  448. *
  449. * [ buffer, buffer_hi ] loaded with "buffer".
  450. */
  451. qtd[qtd_counter].qt_next =
  452. cpu_to_hc32(QT_NEXT_TERMINATE);
  453. qtd[qtd_counter].qt_altnext =
  454. cpu_to_hc32(QT_NEXT_TERMINATE);
  455. token = QT_TOKEN_DT(toggle) |
  456. QT_TOKEN_TOTALBYTES(xfr_bytes) |
  457. QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
  458. QT_TOKEN_CERR(3) |
  459. QT_TOKEN_PID(usb_pipein(pipe) ?
  460. QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
  461. QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
  462. qtd[qtd_counter].qt_token = cpu_to_hc32(token);
  463. if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
  464. xfr_bytes)) {
  465. printf("unable to construct DATA TD\n");
  466. goto fail;
  467. }
  468. /* Update previous qTD! */
  469. *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
  470. tdp = &qtd[qtd_counter++].qt_next;
  471. /*
  472. * Data toggle has to be adjusted since the qTD transfer
  473. * size is not always an even multiple of
  474. * wMaxPacketSize.
  475. */
  476. if ((xfr_bytes / maxpacket) & 1)
  477. toggle ^= 1;
  478. buf_ptr += xfr_bytes;
  479. left_length -= xfr_bytes;
  480. } while (left_length > 0);
  481. }
  482. if (req != NULL) {
  483. /*
  484. * Setup request qTD (3.5 in ehci-r10.pdf)
  485. *
  486. * qt_next ................ 03-00 H
  487. * qt_altnext ............. 07-04 H
  488. * qt_token ............... 0B-08 H
  489. */
  490. qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  491. qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  492. token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
  493. QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
  494. QT_TOKEN_PID(usb_pipein(pipe) ?
  495. QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
  496. QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
  497. qtd[qtd_counter].qt_token = cpu_to_hc32(token);
  498. /* Update previous qTD! */
  499. *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
  500. tdp = &qtd[qtd_counter++].qt_next;
  501. }
  502. ctrl->qh_list.qh_link = cpu_to_hc32(virt_to_phys(qh) | QH_LINK_TYPE_QH);
  503. /* Flush dcache */
  504. uint32_t end = ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1);
  505. flush_dcache_range((unsigned long)&ctrl->qh_list, end);
  506. flush_dcache_range((unsigned long)qh, ALIGN_END_ADDR(struct QH, qh, 1));
  507. flush_dcache_range((unsigned long)qtd,
  508. ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
  509. /* Set async. queue head pointer. */
  510. ehci_writel(&ctrl->hcor->or_asynclistaddr, virt_to_phys(&ctrl->qh_list));
  511. usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
  512. ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
  513. /* Enable async. schedule. */
  514. cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
  515. cmd |= CMD_ASE;
  516. ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
  517. ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
  518. 100 * 1000);
  519. if (ret < 0) {
  520. printf("EHCI fail timeout STS_ASS set\n");
  521. goto fail;
  522. }
  523. /* Wait for TDs to be processed. */
  524. ts = get_timer(0); // FIXME
  525. vtd = &qtd[qtd_counter - 1];
  526. timeout = USB_TIMEOUT_MS(pipe);
  527. do {
  528. /* Invalidate dcache */
  529. invalidate_dcache_range((unsigned long)&ctrl->qh_list,
  530. ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
  531. invalidate_dcache_range((unsigned long)qh,
  532. ALIGN_END_ADDR(struct QH, qh, 1));
  533. invalidate_dcache_range((unsigned long)qtd,
  534. ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
  535. token = hc32_to_cpu(vtd->qt_token);
  536. if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
  537. break;
  538. //WATCHDOG_RESET(); // FIXME
  539. } while (get_timer(ts) < timeout);
  540. /*
  541. * Invalidate the memory area occupied by buffer
  542. * Don't try to fix the buffer alignment, if it isn't properly
  543. * aligned it's upper layer's fault so let invalidate_dcache_range()
  544. * vow about it. But we have to fix the length as it's actual
  545. * transfer length and can be unaligned. This is potentially
  546. * dangerous operation, it's responsibility of the calling
  547. * code to make sure enough space is reserved.
  548. */
  549. if (buffer != NULL && length > 0)
  550. invalidate_dcache_range((unsigned long)buffer,
  551. ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN));
  552. /* Check that the TD processing happened */
  553. if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
  554. printf("EHCI timed out on TD - token=%#lx\n", token);
  555. /* Disable async schedule. */
  556. cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
  557. cmd &= ~CMD_ASE;
  558. ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
  559. ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
  560. 100 * 1000);
  561. if (ret < 0) {
  562. printf("EHCI fail timeout STS_ASS reset\n");
  563. goto fail;
  564. }
  565. token = hc32_to_cpu(qh->qh_overlay.qt_token);
  566. if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) {
  567. //printf("TOKEN=%#lx\n", token);
  568. switch (QT_TOKEN_GET_STATUS(token) &
  569. ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
  570. case 0:
  571. toggle = QT_TOKEN_GET_DT(token);
  572. usb_settoggle(dev, usb_pipeendpoint(pipe),
  573. usb_pipeout(pipe), toggle);
  574. dev->status = 0;
  575. break;
  576. case QT_TOKEN_STATUS_HALTED:
  577. dev->status = USB_ST_STALLED;
  578. break;
  579. case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
  580. case QT_TOKEN_STATUS_DATBUFERR:
  581. dev->status = USB_ST_BUF_ERR;
  582. break;
  583. case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
  584. case QT_TOKEN_STATUS_BABBLEDET:
  585. dev->status = USB_ST_BABBLE_DET;
  586. break;
  587. default:
  588. dev->status = USB_ST_CRC_ERR;
  589. if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED)
  590. dev->status |= USB_ST_STALLED;
  591. break;
  592. }
  593. dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token);
  594. } else {
  595. dev->act_len = 0;
  596. //printf("dev=%u, usbsts=%#lx, p[1]=%#lx, p[2]=%#lx\n",
  597. // dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
  598. // ehci_readl(&ctrl->hcor->or_portsc[0]),
  599. // ehci_readl(&ctrl->hcor->or_portsc[1]));
  600. }
  601. free(qtd);
  602. return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
  603. fail:
  604. free(qtd);
  605. return -1;
  606. }
  607. static int ehci_submit_root(struct usb_device *dev, unsigned long pipe,
  608. void *buffer, int length, struct devrequest *req)
  609. {
  610. uint8_t tmpbuf[4];
  611. u16 typeReq;
  612. void *srcptr = NULL;
  613. int len, srclen;
  614. uint32_t reg;
  615. uint32_t *status_reg;
  616. int port = le16_to_cpu(req->index) & 0xff;
  617. struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
  618. srclen = 0;
  619. /*printf("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
  620. req->request, req->request,
  621. req->requesttype, req->requesttype,
  622. le16_to_cpu(req->value), le16_to_cpu(req->index));*/
  623. typeReq = req->request | req->requesttype << 8;
  624. switch (typeReq) {
  625. case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
  626. case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  627. case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  628. status_reg = ctrl->ops.get_portsc_register(ctrl, port - 1);
  629. if (!status_reg)
  630. return -1;
  631. break;
  632. default:
  633. status_reg = NULL;
  634. break;
  635. }
  636. switch (typeReq) {
  637. case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
  638. switch (le16_to_cpu(req->value) >> 8) {
  639. case USB_DT_DEVICE:
  640. //printf("USB_DT_DEVICE request\n");
  641. srcptr = &descriptor.device;
  642. srclen = descriptor.device.bLength;
  643. break;
  644. case USB_DT_CONFIG:
  645. //printf("USB_DT_CONFIG config\n");
  646. srcptr = &descriptor.config;
  647. srclen = descriptor.config.bLength +
  648. descriptor.interface.bLength +
  649. descriptor.endpoint.bLength;
  650. break;
  651. case USB_DT_STRING:
  652. //printf("USB_DT_STRING config\n");
  653. switch (le16_to_cpu(req->value) & 0xff) {
  654. case 0: /* Language */
  655. srcptr = "\4\3\1\0";
  656. srclen = 4;
  657. break;
  658. case 1: /* Vendor */
  659. srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
  660. srclen = 14;
  661. break;
  662. case 2: /* Product */
  663. srcptr = "\52\3E\0H\0C\0I\0 "
  664. "\0H\0o\0s\0t\0 "
  665. "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
  666. srclen = 42;
  667. break;
  668. default:
  669. printf("unknown value DT_STRING %x\n",
  670. le16_to_cpu(req->value));
  671. goto unknown;
  672. }
  673. break;
  674. default:
  675. printf("unknown value %x\n", le16_to_cpu(req->value));
  676. goto unknown;
  677. }
  678. break;
  679. case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
  680. switch (le16_to_cpu(req->value) >> 8) {
  681. case USB_DT_HUB:
  682. //printf("[ehci] USB_DT_HUB config\n");
  683. srcptr = &descriptor.hub;
  684. srclen = descriptor.hub.bLength;
  685. break;
  686. default:
  687. printf("unknown value %x\n", le16_to_cpu(req->value));
  688. goto unknown;
  689. }
  690. break;
  691. case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
  692. //printf("USB_REQ_SET_ADDRESS\n");
  693. ctrl->rootdev = le16_to_cpu(req->value);
  694. break;
  695. case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
  696. //printf("USB_REQ_SET_CONFIGURATION\n");
  697. /* Nothing to do */
  698. break;
  699. case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
  700. tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
  701. tmpbuf[1] = 0;
  702. srcptr = tmpbuf;
  703. srclen = 2;
  704. break;
  705. case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
  706. memset(tmpbuf, 0, 4);
  707. reg = ehci_readl(status_reg);
  708. if (reg & EHCI_PS_CS)
  709. tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
  710. if (reg & EHCI_PS_PE)
  711. tmpbuf[0] |= USB_PORT_STAT_ENABLE;
  712. if (reg & EHCI_PS_SUSP)
  713. tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
  714. if (reg & EHCI_PS_OCA)
  715. tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
  716. if (reg & EHCI_PS_PR)
  717. tmpbuf[0] |= USB_PORT_STAT_RESET;
  718. if (reg & EHCI_PS_PP)
  719. tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
  720. if (ehci_is_TDI()) {
  721. switch (ctrl->ops.get_port_speed(ctrl, reg)) {
  722. case PORTSC_PSPD_FS:
  723. break;
  724. case PORTSC_PSPD_LS:
  725. tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
  726. break;
  727. case PORTSC_PSPD_HS:
  728. default:
  729. tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
  730. break;
  731. }
  732. } else {
  733. tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
  734. }
  735. if (reg & EHCI_PS_CSC)
  736. tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
  737. if (reg & EHCI_PS_PEC)
  738. tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
  739. if (reg & EHCI_PS_OCC)
  740. tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
  741. if (ctrl->portreset & (1 << port))
  742. tmpbuf[2] |= USB_PORT_STAT_C_RESET;
  743. srcptr = tmpbuf;
  744. srclen = 4;
  745. break;
  746. case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  747. reg = ehci_readl(status_reg);
  748. reg &= ~EHCI_PS_CLEAR;
  749. switch (le16_to_cpu(req->value)) {
  750. case USB_PORT_FEAT_ENABLE:
  751. reg |= EHCI_PS_PE;
  752. ehci_writel(status_reg, reg);
  753. break;
  754. case USB_PORT_FEAT_POWER:
  755. if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
  756. reg |= EHCI_PS_PP;
  757. ehci_writel(status_reg, reg);
  758. }
  759. break;
  760. case USB_PORT_FEAT_RESET:
  761. if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
  762. !ehci_is_TDI() &&
  763. EHCI_PS_IS_LOWSPEED(reg)) {
  764. /* Low speed device, give up ownership. */
  765. printf("port %d low speed --> companion\n",
  766. port - 1);
  767. reg |= EHCI_PS_PO;
  768. ehci_writel(status_reg, reg);
  769. return -ENXIO;
  770. } else {
  771. int ret;
  772. /* Disable chirp for HS erratum */
  773. if (ctrl->has_fsl_erratum_a005275)
  774. reg |= PORTSC_FSL_PFSC;
  775. reg |= EHCI_PS_PR;
  776. reg &= ~EHCI_PS_PE;
  777. ehci_writel(status_reg, reg);
  778. /*
  779. * caller must wait, then call GetPortStatus
  780. * usb 2.0 specification say 50 ms resets on
  781. * root
  782. */
  783. ctrl->ops.powerup_fixup(ctrl, status_reg, &reg);
  784. ehci_writel(status_reg, reg & ~EHCI_PS_PR);
  785. /*
  786. * A host controller must terminate the reset
  787. * and stabilize the state of the port within
  788. * 2 milliseconds
  789. */
  790. ret = handshake(status_reg, EHCI_PS_PR, 0,
  791. 2 * 1000);
  792. if (!ret) {
  793. reg = ehci_readl(status_reg);
  794. if ((reg & (EHCI_PS_PE | EHCI_PS_CS))
  795. == EHCI_PS_CS && !ehci_is_TDI()) {
  796. printf("port %d full speed --> companion\n", port - 1);
  797. reg &= ~EHCI_PS_CLEAR;
  798. reg |= EHCI_PS_PO;
  799. ehci_writel(status_reg, reg);
  800. return -ENXIO;
  801. } else {
  802. ctrl->portreset |= 1 << port;
  803. }
  804. } else {
  805. printf("port(%d) reset error\n",
  806. port - 1);
  807. }
  808. }
  809. break;
  810. case USB_PORT_FEAT_TEST:
  811. ehci_shutdown(ctrl);
  812. reg &= ~(0xf << 16);
  813. reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16;
  814. ehci_writel(status_reg, reg);
  815. break;
  816. default:
  817. printf("unknown feature %x\n", le16_to_cpu(req->value));
  818. goto unknown;
  819. }
  820. /* unblock posted writes */
  821. (void) ehci_readl(&ctrl->hcor->or_usbcmd);
  822. break;
  823. case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  824. reg = ehci_readl(status_reg);
  825. reg &= ~EHCI_PS_CLEAR;
  826. switch (le16_to_cpu(req->value)) {
  827. case USB_PORT_FEAT_ENABLE:
  828. reg &= ~EHCI_PS_PE;
  829. break;
  830. case USB_PORT_FEAT_C_ENABLE:
  831. reg |= EHCI_PS_PE;
  832. break;
  833. case USB_PORT_FEAT_POWER:
  834. if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
  835. reg &= ~EHCI_PS_PP;
  836. break;
  837. case USB_PORT_FEAT_C_CONNECTION:
  838. reg |= EHCI_PS_CSC;
  839. break;
  840. case USB_PORT_FEAT_OVER_CURRENT:
  841. reg |= EHCI_PS_OCC;
  842. break;
  843. case USB_PORT_FEAT_C_RESET:
  844. ctrl->portreset &= ~(1 << port);
  845. break;
  846. default:
  847. printf("unknown feature %x\n", le16_to_cpu(req->value));
  848. goto unknown;
  849. }
  850. ehci_writel(status_reg, reg);
  851. /* unblock posted write */
  852. (void) ehci_readl(&ctrl->hcor->or_usbcmd);
  853. break;
  854. default:
  855. printf("Unknown request\n");
  856. goto unknown;
  857. }
  858. mdelay(1);
  859. len = min3(srclen, (int)le16_to_cpu(req->length), length);
  860. if (srcptr != NULL && len > 0)
  861. memcpy(buffer, srcptr, len);
  862. //else
  863. // printf("[ehci] Len is 0\n");
  864. dev->act_len = len;
  865. dev->status = 0;
  866. return 0;
  867. unknown:
  868. printf("[ehci unknown] requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
  869. req->requesttype, req->request, le16_to_cpu(req->value),
  870. le16_to_cpu(req->index), le16_to_cpu(req->length));
  871. dev->act_len = 0;
  872. dev->status = USB_ST_STALLED;
  873. return -1;
  874. }
  875. static const struct ehci_ops default_ehci_ops = {
  876. .set_usb_mode = ehci_set_usbmode,
  877. .get_port_speed = ehci_get_port_speed,
  878. .powerup_fixup = ehci_powerup_fixup,
  879. .get_portsc_register = ehci_get_portsc_register,
  880. };
  881. static void ehci_setup_ops(struct ehci_ctrl *ctrl, const struct ehci_ops *ops)
  882. {
  883. if (!ops) {
  884. ctrl->ops = default_ehci_ops;
  885. } else {
  886. ctrl->ops = *ops;
  887. if (!ctrl->ops.set_usb_mode)
  888. ctrl->ops.set_usb_mode = ehci_set_usbmode;
  889. if (!ctrl->ops.get_port_speed)
  890. ctrl->ops.get_port_speed = ehci_get_port_speed;
  891. if (!ctrl->ops.powerup_fixup)
  892. ctrl->ops.powerup_fixup = ehci_powerup_fixup;
  893. if (!ctrl->ops.get_portsc_register)
  894. ctrl->ops.get_portsc_register =
  895. ehci_get_portsc_register;
  896. }
  897. }
  898. void ehci_set_controller_priv(int index, void *priv, const struct ehci_ops *ops)
  899. {
  900. struct ehci_ctrl *ctrl = &ehcic[index];
  901. ctrl->priv = priv;
  902. ehci_setup_ops(ctrl, ops);
  903. }
  904. void *ehci_get_controller_priv(int index)
  905. {
  906. return ehcic[index].priv;
  907. }
  908. static int ehci_common_init(struct ehci_ctrl *ctrl, unsigned int tweaks)
  909. {
  910. struct QH *qh_list;
  911. struct QH *periodic;
  912. uint32_t reg;
  913. uint32_t cmd;
  914. int i;
  915. /* Set the high address word (aka segment) for 64-bit controller */
  916. if (ehci_readl(&ctrl->hccr->cr_hccparams) & 1)
  917. ehci_writel(&ctrl->hcor->or_ctrldssegment, 0);
  918. qh_list = &ctrl->qh_list;
  919. /* Set head of reclaim list */
  920. memset(qh_list, 0, sizeof(*qh_list));
  921. qh_list->qh_link = cpu_to_hc32(virt_to_phys(qh_list) | QH_LINK_TYPE_QH);
  922. qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
  923. QH_ENDPT1_EPS(USB_SPEED_HIGH));
  924. qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  925. qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  926. qh_list->qh_overlay.qt_token =
  927. cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
  928. flush_dcache_range((unsigned long)qh_list,
  929. ALIGN_END_ADDR(struct QH, qh_list, 1));
  930. /* Set async. queue head pointer. */
  931. ehci_writel(&ctrl->hcor->or_asynclistaddr, virt_to_phys(qh_list));
  932. /*
  933. * Set up periodic list
  934. * Step 1: Parent QH for all periodic transfers.
  935. */
  936. ctrl->periodic_schedules = 0;
  937. periodic = &ctrl->periodic_queue;
  938. memset(periodic, 0, sizeof(*periodic));
  939. periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
  940. periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  941. periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  942. flush_dcache_range((unsigned long)periodic,
  943. ALIGN_END_ADDR(struct QH, periodic, 1));
  944. /*
  945. * Step 2: Setup frame-list: Every microframe, USB tries the same list.
  946. * In particular, device specifications on polling frequency
  947. * are disregarded. Keyboards seem to send NAK/NYet reliably
  948. * when polled with an empty buffer.
  949. *
  950. * Split Transactions will be spread across microframes using
  951. * S-mask and C-mask.
  952. */
  953. if (ctrl->periodic_list == NULL)
  954. ctrl->periodic_list = memalign(4096, 1024 * 4); // FIXME dynamic allocation
  955. if (!ctrl->periodic_list) {
  956. printf("[ehci_common_init] ENOMEM\n");
  957. return -ENOMEM;
  958. }
  959. for (i = 0; i < 1024; i++) {
  960. ctrl->periodic_list[i] = cpu_to_hc32((unsigned long)periodic
  961. | QH_LINK_TYPE_QH);
  962. }
  963. flush_dcache_range((unsigned long)ctrl->periodic_list,
  964. ALIGN_END_ADDR(uint32_t, ctrl->periodic_list,
  965. 1024));
  966. /* Set periodic list base address */
  967. ehci_writel(&ctrl->hcor->or_periodiclistbase,
  968. (unsigned long)ctrl->periodic_list);
  969. reg = ehci_readl(&ctrl->hccr->cr_hcsparams);
  970. descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
  971. printf("Register %lx NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
  972. /* Port Indicators */
  973. if (HCS_INDICATOR(reg))
  974. put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
  975. | 0x80, &descriptor.hub.wHubCharacteristics);
  976. /* Port Power Control */
  977. if (HCS_PPC(reg))
  978. put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
  979. | 0x01, &descriptor.hub.wHubCharacteristics);
  980. /* Start the host controller. */
  981. cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
  982. /*
  983. * Philips, Intel, and maybe others need CMD_RUN before the
  984. * root hub will detect new devices (why?); NEC doesn't
  985. */
  986. cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
  987. cmd |= CMD_RUN;
  988. ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
  989. if (!(tweaks & EHCI_TWEAK_NO_INIT_CF)) {
  990. /* take control over the ports */
  991. cmd = ehci_readl(&ctrl->hcor->or_configflag);
  992. cmd |= FLAG_CF;
  993. ehci_writel(&ctrl->hcor->or_configflag, cmd);
  994. }
  995. /* unblock posted write */
  996. cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
  997. mdelay(5);
  998. reg = HC_VERSION(ehci_readl(&ctrl->hccr->cr_capbase));
  999. printf("USB EHCI %lx.%02lx\n", reg >> 8, reg & 0xff);
  1000. return 0;
  1001. }
  1002. int ehci_hcd_stop(int index)
  1003. {
  1004. return 0;
  1005. }
  1006. int usb_lowlevel_stop(int index)
  1007. {
  1008. ehci_shutdown(&ehcic[index]);
  1009. return ehci_hcd_stop(index);
  1010. }
  1011. int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
  1012. {
  1013. struct ehci_ctrl *ctrl = &ehcic[index];
  1014. unsigned int tweaks = 0;
  1015. int rc;
  1016. /**
  1017. * Set ops to default_ehci_ops, ehci_hcd_init should call
  1018. * ehci_set_controller_priv to change any of these function pointers.
  1019. */
  1020. ctrl->ops = default_ehci_ops;
  1021. rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
  1022. if (rc) {
  1023. printf("[usb_lowlevel_init] rc: %d\n",rc);
  1024. return rc;
  1025. }
  1026. if (!ctrl->hccr || !ctrl->hcor) {
  1027. printf("[usb_lowlevel_init] hccr or hcor missing: %p %p\n",ctrl->hccr,ctrl->hcor);
  1028. return -1;
  1029. }
  1030. if (init == USB_INIT_DEVICE)
  1031. goto done;
  1032. /* EHCI spec section 4.1 */
  1033. // FIXME mntmn
  1034. //if (ehci_reset(ctrl)) {
  1035. // printf("[usb_lowlevel_init] ehci_reset failed\n");
  1036. // return -1;
  1037. //}
  1038. printf("[usb_lowlevel_init] skipped ehci_reset\n");
  1039. #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
  1040. rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
  1041. if (rc)
  1042. return rc;
  1043. #endif
  1044. rc = ehci_common_init(ctrl, tweaks);
  1045. if (rc) {
  1046. printf("[usb_lowlevel_init] ehci_common_init failed\n");
  1047. return rc;
  1048. }
  1049. ctrl->rootdev = 0;
  1050. done:
  1051. *controller = &ehcic[index];
  1052. return 0;
  1053. }
  1054. static int _ehci_submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
  1055. void *buffer, int length)
  1056. {
  1057. if (usb_pipetype(pipe) != PIPE_BULK) {
  1058. printf("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
  1059. return -1;
  1060. }
  1061. return ehci_submit_async(dev, pipe, buffer, length, NULL);
  1062. }
  1063. static int _ehci_submit_control_msg(struct usb_device *dev, unsigned long pipe,
  1064. void *buffer, int length,
  1065. struct devrequest *setup)
  1066. {
  1067. struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
  1068. if (usb_pipetype(pipe) != PIPE_CONTROL) {
  1069. printf("non-control pipe (type=%lu)", usb_pipetype(pipe));
  1070. return -1;
  1071. }
  1072. if (usb_pipedevice(pipe) == ctrl->rootdev) {
  1073. if (!ctrl->rootdev)
  1074. dev->speed = USB_SPEED_HIGH;
  1075. return ehci_submit_root(dev, pipe, buffer, length, setup);
  1076. }
  1077. return ehci_submit_async(dev, pipe, buffer, length, setup);
  1078. }
  1079. struct int_queue {
  1080. int elementsize;
  1081. unsigned long pipe;
  1082. struct QH *first;
  1083. struct QH *current;
  1084. struct QH *last;
  1085. struct qTD *tds;
  1086. };
  1087. #define NEXT_QH(qh) (struct QH *)((unsigned long)hc32_to_cpu((qh)->qh_link) & ~0x1f)
  1088. static int
  1089. enable_periodic(struct ehci_ctrl *ctrl)
  1090. {
  1091. uint32_t cmd;
  1092. struct ehci_hcor *hcor = ctrl->hcor;
  1093. int ret;
  1094. cmd = ehci_readl(&hcor->or_usbcmd);
  1095. cmd |= CMD_PSE;
  1096. ehci_writel(&hcor->or_usbcmd, cmd);
  1097. ret = handshake((uint32_t *)&hcor->or_usbsts,
  1098. STS_PSS, STS_PSS, 100 * 1000);
  1099. if (ret < 0) {
  1100. printf("EHCI failed: timeout when enabling periodic list\n");
  1101. return -ETIMEDOUT;
  1102. }
  1103. udelay(1000);
  1104. return 0;
  1105. }
  1106. static int
  1107. disable_periodic(struct ehci_ctrl *ctrl)
  1108. {
  1109. uint32_t cmd;
  1110. struct ehci_hcor *hcor = ctrl->hcor;
  1111. int ret;
  1112. cmd = ehci_readl(&hcor->or_usbcmd);
  1113. cmd &= ~CMD_PSE;
  1114. ehci_writel(&hcor->or_usbcmd, cmd);
  1115. ret = handshake((uint32_t *)&hcor->or_usbsts,
  1116. STS_PSS, 0, 100 * 1000);
  1117. if (ret < 0) {
  1118. printf("EHCI failed: timeout when disabling periodic list\n");
  1119. return -ETIMEDOUT;
  1120. }
  1121. return 0;
  1122. }
  1123. static struct int_queue *_ehci_create_int_queue(struct usb_device *dev,
  1124. unsigned long pipe, int queuesize, int elementsize,
  1125. void *buffer, int interval)
  1126. {
  1127. struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
  1128. struct int_queue *result = NULL;
  1129. uint32_t i, toggle;
  1130. /*
  1131. * Interrupt transfers requiring several transactions are not supported
  1132. * because bInterval is ignored.
  1133. *
  1134. * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
  1135. * <= PKT_ALIGN if several qTDs are required, while the USB
  1136. * specification does not constrain this for interrupt transfers. That
  1137. * means that ehci_submit_async() would support interrupt transfers
  1138. * requiring several transactions only as long as the transfer size does
  1139. * not require more than a single qTD.
  1140. */
  1141. if (elementsize > usb_maxpacket(dev, pipe)) {
  1142. printf("%s: xfers requiring several transactions are not supported.\n",
  1143. __func__);
  1144. return NULL;
  1145. }
  1146. printf("Enter create_int_queue\n");
  1147. if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
  1148. printf("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
  1149. return NULL;
  1150. }
  1151. /* limit to 4 full pages worth of data -
  1152. * we can safely fit them in a single TD,
  1153. * no matter the alignment
  1154. */
  1155. if (elementsize >= 16384) {
  1156. printf("too large elements for interrupt transfers\n");
  1157. return NULL;
  1158. }
  1159. result = malloc(sizeof(*result)); // FIXME dynamic allocation
  1160. if (!result) {
  1161. printf("ehci intr queue: out of memory\n");
  1162. goto fail1;
  1163. }
  1164. result->elementsize = elementsize;
  1165. result->pipe = pipe;
  1166. result->first = memalign(USB_DMA_MINALIGN,
  1167. sizeof(struct QH) * queuesize); // FIXME dynamic allocation
  1168. if (!result->first) {
  1169. printf("ehci intr queue: out of memory\n");
  1170. goto fail2;
  1171. }
  1172. result->current = result->first;
  1173. result->last = result->first + queuesize - 1;
  1174. result->tds = memalign(USB_DMA_MINALIGN,
  1175. sizeof(struct qTD) * queuesize); // FIXME dynamic allocation
  1176. if (!result->tds) {
  1177. printf("ehci intr queue: out of memory\n");
  1178. goto fail3;
  1179. }
  1180. memset(result->first, 0, sizeof(struct QH) * queuesize);
  1181. memset(result->tds, 0, sizeof(struct qTD) * queuesize);
  1182. toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
  1183. for (i = 0; i < queuesize; i++) {
  1184. struct QH *qh = result->first + i;
  1185. struct qTD *td = result->tds + i;
  1186. void **buf = &qh->buffer;
  1187. qh->qh_link = cpu_to_hc32((unsigned long)(qh+1) | QH_LINK_TYPE_QH);
  1188. if (i == queuesize - 1)
  1189. qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
  1190. qh->qh_overlay.qt_next = cpu_to_hc32((unsigned long)td);
  1191. qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  1192. qh->qh_endpt1 =
  1193. cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */
  1194. (usb_maxpacket(dev, pipe) << 16) | /* MPS */
  1195. (1 << 14) |
  1196. QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
  1197. (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */
  1198. (usb_pipedevice(pipe) << 0));
  1199. qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */
  1200. (1 << 0)); /* S-mask: microframe 0 */
  1201. if (dev->speed == USB_SPEED_LOW ||
  1202. dev->speed == USB_SPEED_FULL) {
  1203. /* C-mask: microframes 2-4 */
  1204. qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8));
  1205. }
  1206. ehci_update_endpt2_dev_n_port(dev, qh);
  1207. td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  1208. td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  1209. printf("communication direction is '%s'\n",
  1210. usb_pipein(pipe) ? "in" : "out");
  1211. td->qt_token = cpu_to_hc32(
  1212. QT_TOKEN_DT(toggle) |
  1213. (elementsize << 16) |
  1214. ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
  1215. 0x80); /* active */
  1216. td->qt_buffer[0] =
  1217. cpu_to_hc32((unsigned long)buffer + i * elementsize);
  1218. td->qt_buffer[1] =
  1219. cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff);
  1220. td->qt_buffer[2] =
  1221. cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff);
  1222. td->qt_buffer[3] =
  1223. cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff);
  1224. td->qt_buffer[4] =
  1225. cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff);
  1226. *buf = buffer + i * elementsize;
  1227. toggle ^= 1;
  1228. }
  1229. flush_dcache_range((unsigned long)buffer,
  1230. ALIGN_END_ADDR(char, buffer,
  1231. queuesize * elementsize));
  1232. flush_dcache_range((unsigned long)result->first,
  1233. ALIGN_END_ADDR(struct QH, result->first,
  1234. queuesize));
  1235. flush_dcache_range((unsigned long)result->tds,
  1236. ALIGN_END_ADDR(struct qTD, result->tds,
  1237. queuesize));
  1238. if (ctrl->periodic_schedules > 0) {
  1239. if (disable_periodic(ctrl) < 0) {
  1240. printf("FATAL: periodic should never fail, but did");
  1241. goto fail3;
  1242. }
  1243. }
  1244. /* hook up to periodic list */
  1245. struct QH *list = &ctrl->periodic_queue;
  1246. result->last->qh_link = list->qh_link;
  1247. list->qh_link = cpu_to_hc32((unsigned long)result->first | QH_LINK_TYPE_QH);
  1248. flush_dcache_range((unsigned long)result->last,
  1249. ALIGN_END_ADDR(struct QH, result->last, 1));
  1250. flush_dcache_range((unsigned long)list,
  1251. ALIGN_END_ADDR(struct QH, list, 1));
  1252. if (enable_periodic(ctrl) < 0) {
  1253. printf("FATAL: periodic should never fail, but did");
  1254. goto fail3;
  1255. }
  1256. ctrl->periodic_schedules++;
  1257. printf("Exit create_int_queue\n");
  1258. return result;
  1259. fail3:
  1260. if (result->tds)
  1261. free(result->tds);
  1262. fail2:
  1263. if (result->first)
  1264. free(result->first);
  1265. if (result)
  1266. free(result);
  1267. fail1:
  1268. return NULL;
  1269. }
  1270. static void *_ehci_poll_int_queue(struct usb_device *dev,
  1271. struct int_queue *queue)
  1272. {
  1273. struct QH *cur = queue->current;
  1274. struct qTD *cur_td;
  1275. uint32_t token, toggle;
  1276. unsigned long pipe = queue->pipe;
  1277. /* depleted queue */
  1278. if (cur == NULL) {
  1279. printf("Exit poll_int_queue with completed queue\n");
  1280. return NULL;
  1281. }
  1282. /* still active */
  1283. cur_td = &queue->tds[queue->current - queue->first];
  1284. invalidate_dcache_range((unsigned long)cur_td,
  1285. ALIGN_END_ADDR(struct qTD, cur_td, 1));
  1286. token = hc32_to_cpu(cur_td->qt_token);
  1287. if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) {
  1288. printf("Exit poll_int_queue with no completed intr transfer. token is %lx\n", token);
  1289. return NULL;
  1290. }
  1291. toggle = QT_TOKEN_GET_DT(token);
  1292. usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), toggle);
  1293. if (!(cur->qh_link & QH_LINK_TERMINATE))
  1294. queue->current++;
  1295. else
  1296. queue->current = NULL;
  1297. invalidate_dcache_range((unsigned long)cur->buffer,
  1298. ALIGN_END_ADDR(char, cur->buffer,
  1299. queue->elementsize));
  1300. printf("Exit poll_int_queue with completed intr transfer. token is %lx at %p (first at %p)\n",
  1301. token, cur, queue->first);
  1302. return cur->buffer;
  1303. }
  1304. /* Do not free buffers associated with QHs, they're owned by someone else */
  1305. static int _ehci_destroy_int_queue(struct usb_device *dev,
  1306. struct int_queue *queue)
  1307. {
  1308. struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
  1309. int result = -1;
  1310. unsigned long timeout;
  1311. if (disable_periodic(ctrl) < 0) {
  1312. printf("FATAL: periodic should never fail, but did");
  1313. goto out;
  1314. }
  1315. ctrl->periodic_schedules--;
  1316. struct QH *cur = &ctrl->periodic_queue;
  1317. timeout = get_timer(0) + 500; /* abort after 500ms */
  1318. while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) {
  1319. printf("considering %p, with qh_link %lx\n", cur, cur->qh_link);
  1320. if (NEXT_QH(cur) == queue->first) {
  1321. printf("found candidate. removing from chain\n");
  1322. cur->qh_link = queue->last->qh_link;
  1323. flush_dcache_range((unsigned long)cur,
  1324. ALIGN_END_ADDR(struct QH, cur, 1));
  1325. result = 0;
  1326. break;
  1327. }
  1328. cur = NEXT_QH(cur);
  1329. if (get_timer(0) > timeout) {
  1330. printf("Timeout destroying interrupt endpoint queue\n");
  1331. result = -1;
  1332. goto out;
  1333. }
  1334. }
  1335. if (ctrl->periodic_schedules > 0) {
  1336. result = enable_periodic(ctrl);
  1337. if (result < 0)
  1338. printf("FATAL: periodic should never fail, but did");
  1339. }
  1340. out:
  1341. free(queue->tds);
  1342. free(queue->first);
  1343. free(queue);
  1344. return result;
  1345. }
  1346. static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe,
  1347. void *buffer, int length, int interval)
  1348. {
  1349. void *backbuffer;
  1350. struct int_queue *queue;
  1351. unsigned long timeout;
  1352. int result = 0, ret;
  1353. //printf("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
  1354. // dev, pipe, buffer, length, interval);
  1355. queue = _ehci_create_int_queue(dev, pipe, 1, length, buffer, interval);
  1356. if (!queue)
  1357. return -1;
  1358. timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
  1359. while ((backbuffer = _ehci_poll_int_queue(dev, queue)) == NULL)
  1360. if (get_timer(0) > timeout) {
  1361. printf("Timeout poll on interrupt endpoint\n");
  1362. result = -ETIMEDOUT;
  1363. break;
  1364. }
  1365. if (backbuffer != buffer) {
  1366. printf("got wrong buffer back (%p instead of %p)\n",
  1367. backbuffer, buffer);
  1368. return -EINVAL;
  1369. }
  1370. ret = _ehci_destroy_int_queue(dev, queue);
  1371. if (ret < 0)
  1372. return ret;
  1373. /* everything worked out fine */
  1374. return result;
  1375. }
  1376. int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
  1377. void *buffer, int length)
  1378. {
  1379. return _ehci_submit_bulk_msg(dev, pipe, buffer, length);
  1380. }
  1381. int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1382. int length, struct devrequest *setup)
  1383. {
  1384. return _ehci_submit_control_msg(dev, pipe, buffer, length, setup);
  1385. }
  1386. int submit_int_msg(struct usb_device *dev, unsigned long pipe,
  1387. void *buffer, int length, int interval)
  1388. {
  1389. return _ehci_submit_int_msg(dev, pipe, buffer, length, interval);
  1390. }
  1391. struct int_queue *create_int_queue(struct usb_device *dev,
  1392. unsigned long pipe, int queuesize, int elementsize,
  1393. void *buffer, int interval)
  1394. {
  1395. return _ehci_create_int_queue(dev, pipe, queuesize, elementsize,
  1396. buffer, interval);
  1397. }
  1398. void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
  1399. {
  1400. return _ehci_poll_int_queue(dev, queue);
  1401. }
  1402. int destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
  1403. {
  1404. return _ehci_destroy_int_queue(dev, queue);
  1405. }
  1406. int ehci_register(struct ehci_ctrl *ctrl, struct ehci_hccr *hccr,
  1407. struct ehci_hcor *hcor, const struct ehci_ops *ops,
  1408. uint tweaks, enum usb_init_type init)
  1409. {
  1410. //struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
  1411. //struct ehci_ctrl *ctrl = dev_get_priv(dev);
  1412. int ret = -1;
  1413. printf("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p, init=%d\n", __func__,
  1414. "zynq-ehci", ctrl, hccr, hcor, init);
  1415. if (!ctrl || !hccr || !hcor)
  1416. goto err;
  1417. // FIXME
  1418. //priv->desc_before_addr = true;
  1419. ehci_setup_ops(ctrl, ops);
  1420. ctrl->hccr = hccr;
  1421. ctrl->hcor = hcor;
  1422. ctrl->priv = ctrl;
  1423. ctrl->init = init;
  1424. if (ctrl->init == USB_INIT_DEVICE)
  1425. goto done;
  1426. ret = ehci_reset(ctrl);
  1427. if (ret)
  1428. goto err;
  1429. if (ctrl->ops.init_after_reset) {
  1430. ret = ctrl->ops.init_after_reset(ctrl);
  1431. if (ret)
  1432. goto err;
  1433. }
  1434. //ret = ehci_common_init(ctrl, tweaks);
  1435. if (ret)
  1436. goto err;
  1437. done:
  1438. return 0;
  1439. err:
  1440. free(ctrl);
  1441. printf("%s: failed, ret=%d\n", __func__, ret);
  1442. return ret;
  1443. }
  1444. #ifdef CONFIG_PHY
  1445. int ehci_setup_phy(struct udevice *dev, struct phy *phy, int index)
  1446. {
  1447. int ret;
  1448. if (!phy)
  1449. return 0;
  1450. ret = generic_phy_get_by_index(dev, index, phy);
  1451. if (ret) {
  1452. if (ret != -ENOENT) {
  1453. dev_err(dev, "failed to get usb phy\n");
  1454. return ret;
  1455. }
  1456. } else {
  1457. ret = generic_phy_init(phy);
  1458. if (ret) {
  1459. dev_err(dev, "failed to init usb phy\n");
  1460. return ret;
  1461. }
  1462. ret = generic_phy_power_on(phy);
  1463. if (ret) {
  1464. dev_err(dev, "failed to power on usb phy\n");
  1465. return generic_phy_exit(phy);
  1466. }
  1467. }
  1468. return 0;
  1469. }
  1470. int ehci_shutdown_phy(struct udevice *dev, struct phy *phy)
  1471. {
  1472. int ret = 0;
  1473. if (!phy)
  1474. return 0;
  1475. if (generic_phy_valid(phy)) {
  1476. ret = generic_phy_power_off(phy);
  1477. if (ret) {
  1478. dev_err(dev, "failed to power off usb phy\n");
  1479. return ret;
  1480. }
  1481. ret = generic_phy_exit(phy);
  1482. if (ret) {
  1483. dev_err(dev, "failed to power off usb phy\n");
  1484. return ret;
  1485. }
  1486. }
  1487. return 0;
  1488. }
  1489. #else
  1490. int ehci_setup_phy(struct udevice *dev, struct phy *phy, int index)
  1491. {
  1492. return 0;
  1493. }
  1494. int ehci_shutdown_phy(struct udevice *dev, struct phy *phy)
  1495. {
  1496. return 0;
  1497. }
  1498. #endif