Firmware for MNT ZZ9000 graphics and ARM coprocessor card for Amiga computers.
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ehci-ci.h 9.7KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (c) 2005, 2009 Freescale Semiconductor, Inc
  4. * Copyright (c) 2005 MontaVista Software
  5. * Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB
  6. */
  7. #ifndef _EHCI_CI_H
  8. #define _EHCI_CI_H
  9. //#include <asm/processor.h>
  10. #define CONTROL_REGISTER_W1C_MASK 0x00020000 /* W1C: PHY_CLK_VALID */
  11. /* Global offsets */
  12. #define FSL_SKIP_PCI 0x100
  13. /* offsets for the non-ehci registers in the FSL SOC USB controller */
  14. #define FSL_SOC_USB_ULPIVP 0x170
  15. #define FSL_SOC_USB_PORTSC1 0x184
  16. #define PORT_PTS_MSK (3 << 30)
  17. #define PORT_PTS_UTMI (0 << 30)
  18. #define PORT_PTS_ULPI (2 << 30)
  19. #define PORT_PTS_SERIAL (3 << 30)
  20. #define PORT_PTS_PTW (1 << 28)
  21. #define PORT_PFSC (1 << 24) /* Defined on Page 39-44 of the mpc5151 ERM */
  22. #define PORT_PTS_PHCD (1 << 23)
  23. #define PORT_PP (1 << 12)
  24. #define PORT_PR (1 << 8)
  25. /* USBMODE Register bits */
  26. #define CM_IDLE (0 << 0)
  27. #define CM_RESERVED (1 << 0)
  28. #define CM_DEVICE (2 << 0)
  29. #define CM_HOST (3 << 0)
  30. #define ES_BE (1 << 2) /* Big Endian Select, default is LE */
  31. #define USBMODE_RESERVED_2 (0 << 2)
  32. #define SLOM (1 << 3)
  33. #define SDIS (1 << 4)
  34. /* CONTROL Register bits */
  35. #define ULPI_INT_EN (1 << 0)
  36. #define WU_INT_EN (1 << 1)
  37. #define USB_EN (1 << 2)
  38. #define LSF_EN (1 << 3)
  39. #define KEEP_OTG_ON (1 << 4)
  40. #define OTG_PORT (1 << 5)
  41. #define REFSEL_12MHZ (0 << 6)
  42. #define REFSEL_16MHZ (1 << 6)
  43. #define REFSEL_48MHZ (2 << 6)
  44. #define PLL_RESET (1 << 8)
  45. #define UTMI_PHY_EN (1 << 9)
  46. #define PHY_CLK_SEL_UTMI (0 << 10)
  47. #define PHY_CLK_SEL_ULPI (1 << 10)
  48. #define CLKIN_SEL_USB_CLK (0 << 11)
  49. #define CLKIN_SEL_USB_CLK2 (1 << 11)
  50. #define CLKIN_SEL_SYS_CLK (2 << 11)
  51. #define CLKIN_SEL_SYS_CLK2 (3 << 11)
  52. #define RESERVED_18 (0 << 13)
  53. #define RESERVED_17 (0 << 14)
  54. #define RESERVED_16 (0 << 15)
  55. #define WU_INT (1 << 16)
  56. #define PHY_CLK_VALID (1 << 17)
  57. #define FSL_SOC_USB_PORTSC2 0x188
  58. /* OTG Status Control Register bits */
  59. #define FSL_SOC_USB_OTGSC 0x1a4
  60. #define CTRL_VBUS_DISCHARGE (0x1<<0)
  61. #define CTRL_VBUS_CHARGE (0x1<<1)
  62. #define CTRL_OTG_TERMINATION (0x1<<3)
  63. #define CTRL_DATA_PULSING (0x1<<4)
  64. #define CTRL_ID_PULL_EN (0x1<<5)
  65. #define HA_DATA_PULSE (0x1<<6)
  66. #define HA_BA (0x1<<7)
  67. #define STS_USB_ID (0x1<<8)
  68. #define STS_A_VBUS_VALID (0x1<<9)
  69. #define STS_A_SESSION_VALID (0x1<<10)
  70. #define STS_B_SESSION_VALID (0x1<<11)
  71. #define STS_B_SESSION_END (0x1<<12)
  72. #define STS_1MS_TOGGLE (0x1<<13)
  73. #define STS_DATA_PULSING (0x1<<14)
  74. #define INTSTS_USB_ID (0x1<<16)
  75. #define INTSTS_A_VBUS_VALID (0x1<<17)
  76. #define INTSTS_A_SESSION_VALID (0x1<<18)
  77. #define INTSTS_B_SESSION_VALID (0x1<<19)
  78. #define INTSTS_B_SESSION_END (0x1<<20)
  79. #define INTSTS_1MS (0x1<<21)
  80. #define INTSTS_DATA_PULSING (0x1<<22)
  81. #define INTR_USB_ID_EN (0x1<<24)
  82. #define INTR_A_VBUS_VALID_EN (0x1<<25)
  83. #define INTR_A_SESSION_VALID_EN (0x1<<26)
  84. #define INTR_B_SESSION_VALID_EN (0x1<<27)
  85. #define INTR_B_SESSION_END_EN (0x1<<28)
  86. #define INTR_1MS_TIMER_EN (0x1<<29)
  87. #define INTR_DATA_PULSING_EN (0x1<<30)
  88. #define INTSTS_MASK (0x00ff0000)
  89. #define INTERRUPT_ENABLE_BITS_MASK \
  90. (INTR_USB_ID_EN | \
  91. INTR_1MS_TIMER_EN | \
  92. INTR_A_VBUS_VALID_EN | \
  93. INTR_A_SESSION_VALID_EN | \
  94. INTR_B_SESSION_VALID_EN | \
  95. INTR_B_SESSION_END_EN | \
  96. INTR_DATA_PULSING_EN)
  97. #define INTERRUPT_STATUS_BITS_MASK \
  98. (INTSTS_USB_ID | \
  99. INTR_1MS_TIMER_EN | \
  100. INTSTS_A_VBUS_VALID | \
  101. INTSTS_A_SESSION_VALID | \
  102. INTSTS_B_SESSION_VALID | \
  103. INTSTS_B_SESSION_END | \
  104. INTSTS_DATA_PULSING)
  105. #define FSL_SOC_USB_USBMODE 0x1a8
  106. #define USBGENCTRL 0x200 /* NOTE: big endian */
  107. #define GC_WU_INT_CLR (1 << 5) /* Wakeup int clear */
  108. #define GC_ULPI_SEL (1 << 4) /* ULPI i/f select (usb0 only)*/
  109. #define GC_PPP (1 << 3) /* Port Power Polarity */
  110. #define GC_PFP (1 << 2) /* Power Fault Polarity */
  111. #define GC_WU_ULPI_EN (1 << 1) /* Wakeup on ULPI event */
  112. #define GC_WU_IE (1 << 1) /* Wakeup interrupt enable */
  113. #define ISIPHYCTRL 0x204 /* NOTE: big endian */
  114. #define PHYCTRL_PHYE (1 << 4) /* On-chip UTMI PHY enable */
  115. #define PHYCTRL_BSENH (1 << 3) /* Bit Stuff Enable High */
  116. #define PHYCTRL_BSEN (1 << 2) /* Bit Stuff Enable */
  117. #define PHYCTRL_LSFE (1 << 1) /* Line State Filter Enable */
  118. #define PHYCTRL_PXE (1 << 0) /* PHY oscillator enable */
  119. #define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */
  120. #define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */
  121. #define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */
  122. #define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
  123. #define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
  124. #define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
  125. #define SNOOP_SIZE_2GB 0x1e
  126. /* System Clock Control Register */
  127. #define MPC83XX_SCCR_USB_MASK 0x00f00000
  128. #define MPC83XX_SCCR_USB_DRCM_11 0x00300000
  129. #define MPC83XX_SCCR_USB_DRCM_01 0x00100000
  130. #define MPC83XX_SCCR_USB_DRCM_10 0x00200000
  131. #if defined(CONFIG_MPC83xx)
  132. #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC83xx_USB1_ADDR
  133. #if defined(CONFIG_MPC834x)
  134. #define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC83xx_USB2_ADDR
  135. #else
  136. #define CONFIG_SYS_FSL_USB2_ADDR 0
  137. #endif
  138. #elif defined(CONFIG_MPC85xx)
  139. #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR
  140. #define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR
  141. #elif defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_ARCH_LS1012A)
  142. #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR
  143. #define CONFIG_SYS_FSL_USB2_ADDR 0
  144. #endif
  145. /*
  146. * Increasing TX FIFO threshold value from 2 to 4 decreases
  147. * data burst rate with which data packets are posted from the TX
  148. * latency FIFO to compensate for latencies in DDR pipeline during DMA
  149. */
  150. #define TXFIFOTHRESH 4
  151. /*
  152. * USB Registers
  153. */
  154. struct usb_ehci {
  155. u32 id; /* 0x000 - Identification register */
  156. u32 hwgeneral; /* 0x004 - General hardware parameters */
  157. u32 hwhost; /* 0x008 - Host hardware parameters */
  158. u32 hwdevice; /* 0x00C - Device hardware parameters */
  159. u32 hwtxbuf; /* 0x010 - TX buffer hardware parameters */
  160. u32 hwrxbuf; /* 0x014 - RX buffer hardware parameters */
  161. u8 res1[0x68];
  162. u32 gptimer0_ld; /* 0x080 - General Purpose Timer 0 load value */
  163. u32 gptimer0_ctrl; /* 0x084 - General Purpose Timer 0 control */
  164. u32 gptimer1_ld; /* 0x088 - General Purpose Timer 1 load value */
  165. u32 gptimer1_ctrl; /* 0x08C - General Purpose Timer 1 control */
  166. u32 sbuscfg; /* 0x090 - System Bus Interface Control */
  167. u32 sbusstatus; /* 0x094 - System Bus Interface Status */
  168. u32 sbusmode; /* 0x098 - System Bus Interface Mode */
  169. u32 genconfig; /* 0x09C - USB Core Configuration */
  170. u32 genconfig2; /* 0x0A0 - USB Core Configuration 2 */
  171. u8 res2[0x5c];
  172. u8 caplength; /* 0x100 - Capability Register Length */
  173. u8 res3[0x1];
  174. u16 hciversion; /* 0x102 - Host Interface Version */
  175. u32 hcsparams; /* 0x104 - Host Structural Parameters */
  176. u32 hccparams; /* 0x108 - Host Capability Parameters */
  177. u8 res4[0x14];
  178. u32 dciversion; /* 0x120 - Device Interface Version */
  179. u32 dciparams; /* 0x124 - Device Controller Params */
  180. u8 res5[0x18];
  181. u32 usbcmd; /* 0x140 - USB Command */
  182. u32 usbsts; /* 0x144 - USB Status */
  183. u32 usbintr; /* 0x148 - USB Interrupt Enable */
  184. u32 frindex; /* 0x14C - USB Frame Index */
  185. u8 res6[0x4];
  186. u32 perlistbase; /* 0x154 - Periodic List Base
  187. - USB Device Address */
  188. u32 ep_list_addr; /* 0x158 - Next Asynchronous List
  189. - End Point Address */
  190. u8 res7[0x4];
  191. u32 burstsize; /* 0x160 - Programmable Burst Size */
  192. #define FSL_EHCI_TXPBURST(X) ((X) << 8)
  193. #define FSL_EHCI_RXPBURST(X) (X)
  194. u32 txfilltuning; /* 0x164 - Host TT Transmit
  195. pre-buffer packet tuning */
  196. u8 res8[0x8];
  197. u32 ulpi_viewpoint; /* 0x170 - ULPI Reister Access */
  198. u8 res9[0xc];
  199. u32 config_flag; /* 0x180 - Configured Flag Register */
  200. u32 portsc; /* 0x184 - Port status/control */
  201. u8 res10[0x1C];
  202. u32 otgsc; /* 0x1a4 - Oo-The-Go status and control */
  203. u32 usbmode; /* 0x1a8 - USB Device Mode */
  204. u32 epsetupstat; /* 0x1ac - End Point Setup Status */
  205. u32 epprime; /* 0x1b0 - End Point Init Status */
  206. u32 epflush; /* 0x1b4 - End Point De-initlialize */
  207. u32 epstatus; /* 0x1b8 - End Point Status */
  208. u32 epcomplete; /* 0x1bc - End Point Complete */
  209. u32 epctrl0; /* 0x1c0 - End Point Control 0 */
  210. u32 epctrl1; /* 0x1c4 - End Point Control 1 */
  211. u32 epctrl2; /* 0x1c8 - End Point Control 2 */
  212. u32 epctrl3; /* 0x1cc - End Point Control 3 */
  213. u32 epctrl4; /* 0x1d0 - End Point Control 4 */
  214. u32 epctrl5; /* 0x1d4 - End Point Control 5 */
  215. u8 res11[0x28];
  216. u32 usbgenctrl; /* 0x200 - USB General Control */
  217. u32 isiphyctrl; /* 0x204 - On-Chip PHY Control */
  218. u8 res12[0x1F8];
  219. u32 snoop1; /* 0x400 - Snoop 1 */
  220. u32 snoop2; /* 0x404 - Snoop 2 */
  221. u32 age_cnt_limit; /* 0x408 - Age Count Threshold */
  222. u32 prictrl; /* 0x40c - Priority Control */
  223. u32 sictrl; /* 0x410 - System Interface Control */
  224. u8 res13[0xEC];
  225. u32 control; /* 0x500 - Control */
  226. u8 res14[0xafc];
  227. };
  228. /*
  229. * For MXC SOCs
  230. */
  231. /* values for portsc field */
  232. #define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
  233. #define MXC_EHCI_FORCE_FS (1 << 24)
  234. #define MXC_EHCI_UTMI_8BIT (0 << 28)
  235. #define MXC_EHCI_UTMI_16BIT (1 << 28)
  236. #define MXC_EHCI_SERIAL (1 << 29)
  237. #define MXC_EHCI_MODE_UTMI (0 << 30)
  238. #define MXC_EHCI_MODE_PHILIPS (1 << 30)
  239. #define MXC_EHCI_MODE_ULPI (2 << 30)
  240. #define MXC_EHCI_MODE_SERIAL (3 << 30)
  241. /* values for flags field */
  242. #define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
  243. #define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
  244. #define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
  245. #define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
  246. #define MXC_EHCI_INTERFACE_MASK (0xf)
  247. #define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
  248. #define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6)
  249. #define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7)
  250. #define MXC_EHCI_TTL_ENABLED (1 << 8)
  251. #define MXC_EHCI_INTERNAL_PHY (1 << 9)
  252. #define MXC_EHCI_IPPUE_DOWN (1 << 10)
  253. #define MXC_EHCI_IPPUE_UP (1 << 11)
  254. int usb_phy_mode(int port);
  255. /* Board-specific initialization */
  256. int board_ehci_hcd_init(int port);
  257. int board_ehci_power(int port, int on);
  258. int board_usb_phy_mode(int port);
  259. #endif /* _EHCI_CI_H */