Firmware for MNT ZZ9000 graphics and ARM coprocessor card for Amiga computers.
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main.c 54KB

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  1. /*
  2. * MNT ZZ9000 Amiga Graphics and Coprocessor Card Operating System (ZZ9000OS)
  3. *
  4. * Copyright (C) 2019, Lukas F. Hartmann <lukas@mntre.com>
  5. * MNT Research GmbH, Berlin
  6. * https://mntre.com
  7. *
  8. * More Info: https://mntre.com/zz9000
  9. *
  10. * SPDX-License-Identifier: GPL-3.0-or-later
  11. * GNU General Public License v3.0 or later
  12. *
  13. * https://spdx.org/licenses/GPL-3.0-or-later.html
  14. *
  15. */
  16. #include <stdio.h>
  17. #include <string.h>
  18. #include <malloc.h>
  19. #include <math.h>
  20. #include "platform.h"
  21. #include "xil_printf.h"
  22. #include "xparameters.h"
  23. #include "xil_io.h"
  24. #include "xiicps.h"
  25. #include "sleep.h"
  26. #include "xaxivdma.h"
  27. #include "xil_cache.h"
  28. #include "xclk_wiz.h"
  29. #include "xil_exception.h"
  30. #include "gfx.h"
  31. #include "ethernet.h"
  32. #include "usb.h"
  33. #include "xgpiops.h"
  34. #include "xil_misc_psreset_api.h"
  35. typedef u8 uint8_t;
  36. #define A9_CPU_RST_CTRL (XSLCR_BASEADDR + 0x244)
  37. #define A9_RST1_MASK 0x00000002
  38. #define A9_CLKSTOP1_MASK 0x00000020
  39. #define XSLCR_LOCK_ADDR (XSLCR_BASEADDR + 0x4)
  40. #define XSLCR_LOCK_CODE 0x0000767B
  41. #define IIC_DEVICE_ID XPAR_XIICPS_0_DEVICE_ID
  42. #define VDMA_DEVICE_ID XPAR_AXIVDMA_0_DEVICE_ID
  43. #define HDMI_I2C_ADDR 0x3b
  44. #define IIC_SCLK_RATE 400000
  45. #define GPIO_DEVICE_ID XPAR_XGPIOPS_0_DEVICE_ID
  46. #define I2C_PAUSE 10
  47. // I2C controller instance
  48. XIicPs Iic;
  49. int hdmi_ctrl_write_byte(u8 addr, u8 value) {
  50. u8 buffer[2];
  51. buffer[0] = addr;
  52. buffer[1] = value;
  53. int status;
  54. while (XIicPs_BusIsBusy(&Iic)) {
  55. };
  56. usleep(I2C_PAUSE);
  57. status = XIicPs_MasterSendPolled(&Iic, buffer, 1, HDMI_I2C_ADDR);
  58. while (XIicPs_BusIsBusy(&Iic)) {
  59. };
  60. usleep(I2C_PAUSE);
  61. buffer[1] = 0xff;
  62. status = XIicPs_MasterRecvPolled(&Iic, buffer + 1, 1, HDMI_I2C_ADDR);
  63. //printf("[hdmi] old value of 0x%0x: 0x%0x\n",addr,buffer[1]);
  64. buffer[1] = value;
  65. while (XIicPs_BusIsBusy(&Iic)) {
  66. };
  67. status = XIicPs_MasterSendPolled(&Iic, buffer, 2, HDMI_I2C_ADDR);
  68. while (XIicPs_BusIsBusy(&Iic)) {
  69. };
  70. usleep(I2C_PAUSE);
  71. status = XIicPs_MasterSendPolled(&Iic, buffer, 1, HDMI_I2C_ADDR);
  72. while (XIicPs_BusIsBusy(&Iic)) {
  73. };
  74. usleep(I2C_PAUSE);
  75. buffer[1] = 0xff;
  76. status = XIicPs_MasterRecvPolled(&Iic, buffer + 1, 1, HDMI_I2C_ADDR);
  77. if (buffer[1] != value) {
  78. printf("[hdmi] new value of 0x%x: 0x%x (should be 0x%x)\n", addr,
  79. buffer[1], value);
  80. }
  81. return status;
  82. }
  83. int hdmi_ctrl_read_byte(u8 addr, u8* buffer) {
  84. buffer[0] = addr;
  85. buffer[1] = 0xff;
  86. while (XIicPs_BusIsBusy(&Iic)) {
  87. };
  88. int status = XIicPs_MasterSendPolled(&Iic, buffer, 1, HDMI_I2C_ADDR);
  89. while (XIicPs_BusIsBusy(&Iic)) {
  90. };
  91. usleep(I2C_PAUSE);
  92. status = XIicPs_MasterRecvPolled(&Iic, buffer + 1, 1, HDMI_I2C_ADDR);
  93. return status;
  94. }
  95. static u8 sii9022_init[] = {
  96. 0x1e, 0x00,// TPI Device Power State Control Data (R/W)
  97. 0x09, 0x00, //
  98. 0x0a, 0x00,
  99. 0x60, 0x04, 0x3c, 0x01, // TPI Interrupt Enable (R/W)
  100. 0x1a, 0x10, // TPI System Control (R/W)
  101. 0x00, 0x4c, // PixelClock/10000 - LSB u16:6
  102. 0x01, 0x1d, // PixelClock/10000 - MSB
  103. 0x02, 0x70, // Frequency in HZ - LSB
  104. 0x03, 0x17, // Vertical Frequency in HZ - MSB
  105. 0x04, 0x70, // Total Pixels per line - LSB
  106. 0x05, 0x06, // Total Pixels per line - MSB
  107. 0x06, 0xEE, // Total Lines - LSB
  108. 0x07, 0x02, // Total Lines - MSB
  109. 0x08, 0x70, // pixel repeat rate?
  110. 0x1a, 0x00, // CTRL_DATA - bit 1 causes 2 purple extra columns on DVI monitors (probably HDMI mode)
  111. };
  112. void disable_reset_out() {
  113. XGpioPs Gpio;
  114. XGpioPs_Config *ConfigPtr;
  115. ConfigPtr = XGpioPs_LookupConfig(GPIO_DEVICE_ID);
  116. XGpioPs_CfgInitialize(&Gpio, ConfigPtr, ConfigPtr->BaseAddr);
  117. int output_pin = 7;
  118. XGpioPs_SetDirectionPin(&Gpio, output_pin, 1);
  119. XGpioPs_SetOutputEnablePin(&Gpio, output_pin, 1);
  120. XGpioPs_WritePin(&Gpio, output_pin, 0);
  121. usleep(10000);
  122. XGpioPs_WritePin(&Gpio, output_pin, 1);
  123. print("GPIO reset disable done.\n\r");
  124. }
  125. void hdmi_ctrl_init() {
  126. int status;
  127. XIicPs_Config *config;
  128. config = XIicPs_LookupConfig(IIC_DEVICE_ID);
  129. status = XIicPs_CfgInitialize(&Iic, config, config->BaseAddress);
  130. //printf("XIicPs_CfgInitialize: %d\n", status);
  131. usleep(10000);
  132. //printf("XIicPs is ready: %lx\n", Iic.IsReady);
  133. status = XIicPs_SelfTest(&Iic);
  134. //printf("XIicPs_SelfTest: %x\n", status);
  135. status = XIicPs_SetSClk(&Iic, IIC_SCLK_RATE);
  136. //printf("XIicPs_SetSClk: %x\n", status);
  137. usleep(2500);
  138. // reset
  139. status = hdmi_ctrl_write_byte(0xc7, 0);
  140. u8 buffer[2];
  141. status = hdmi_ctrl_read_byte(0x1b, buffer);
  142. printf("[%d] TPI device id: 0x%x\n", status, buffer[1]);
  143. status = hdmi_ctrl_read_byte(0x1c, buffer);
  144. //printf("[%d] TPI revision 1: 0x%x\n",status,buffer[1]);
  145. //status = hdmi_ctrl_read_byte(0x1d,buffer);
  146. //printf("[%d] TPI revision 2: 0x%x\n",status,buffer[1]);
  147. //status = hdmi_ctrl_read_byte(0x30,buffer);
  148. //printf("[%d] HDCP revision: 0x%x\n",status,buffer[1]);
  149. //status = hdmi_ctrl_read_byte(0x3d,buffer);
  150. printf("[%d] hotplug: 0x%x\n", status, buffer[1]);
  151. for (int i = 0; i < sizeof(sii9022_init); i += 2) {
  152. status = hdmi_ctrl_write_byte(sii9022_init[i], sii9022_init[i + 1]);
  153. usleep(1);
  154. }
  155. }
  156. XAxiVdma vdma;
  157. static u32* framebuffer = 0;
  158. static u32 framebuffer_pan_offset = 0;
  159. static u32 blitter_dst_offset = 0;
  160. static u32 blitter_src_offset = 0;
  161. static u32 vmode_hsize = 800, vmode_vsize = 600, vmode_hdiv = 1, vmode_vdiv = 2;
  162. // 32bit: hdiv=1, 16bit: hdiv=2, 8bit: hdiv=4, ...
  163. int init_vdma(int hsize, int vsize, int hdiv, int vdiv) {
  164. int status;
  165. XAxiVdma_Config *Config;
  166. Config = XAxiVdma_LookupConfig(VDMA_DEVICE_ID);
  167. if (!Config) {
  168. printf("VDMA not found for ID %d\r\n", VDMA_DEVICE_ID);
  169. return XST_FAILURE;
  170. }
  171. /*XAxiVdma_DmaStop(&vdma, XAXIVDMA_READ);
  172. XAxiVdma_Reset(&vdma, XAXIVDMA_READ);
  173. XAxiVdma_ClearDmaChannelErrors(&vdma, XAXIVDMA_READ, XAXIVDMA_SR_ERR_ALL_MASK);*/
  174. status = XAxiVdma_CfgInitialize(&vdma, Config, Config->BaseAddress);
  175. if (status != XST_SUCCESS) {
  176. printf("VDMA Configuration Initialization failed, status: 0x%X\r\n",
  177. status);
  178. //return status;
  179. }
  180. u32 stride = hsize * (Config->Mm2SStreamWidth >> 3);
  181. XAxiVdma_DmaSetup ReadCfg;
  182. printf("VDMA HDIV: %d VDIV: %d\n", hdiv, vdiv);
  183. ReadCfg.VertSizeInput = vsize / vdiv;
  184. ReadCfg.HoriSizeInput = stride / hdiv; // note: changing this breaks the output
  185. ReadCfg.Stride = stride / hdiv; // note: changing this is not a problem
  186. ReadCfg.FrameDelay = 0; /* This example does not test frame delay */
  187. ReadCfg.EnableCircularBuf = 1; /* Only 1 buffer, continuous loop */
  188. ReadCfg.EnableSync = 0; /* Gen-Lock */
  189. ReadCfg.PointNum = 0;
  190. ReadCfg.EnableFrameCounter = 0; /* Endless transfers */
  191. ReadCfg.FixedFrameStoreAddr = 0; /* We are not doing parking */
  192. ReadCfg.FrameStoreStartAddr[0] = (u32) framebuffer + framebuffer_pan_offset;
  193. printf("VDMA Framebuffer at 0x%x\n", ReadCfg.FrameStoreStartAddr[0]);
  194. status = XAxiVdma_DmaConfig(&vdma, XAXIVDMA_READ, &ReadCfg);
  195. if (status != XST_SUCCESS) {
  196. printf("VDMA Read channel config failed, status: 0x%X\r\n", status);
  197. return status;
  198. }
  199. status = XAxiVdma_DmaSetBufferAddr(&vdma, XAXIVDMA_READ, ReadCfg.FrameStoreStartAddr);
  200. if (status != XST_SUCCESS) {
  201. printf("VDMA Read channel set buffer address failed, status: 0x%X\r\n", status);
  202. return status;
  203. }
  204. status = XAxiVdma_DmaStart(&vdma, XAXIVDMA_READ);
  205. if (status != XST_SUCCESS) {
  206. printf("VDMA Failed to start DMA engine (read channel), status: 0x%X\r\n", status);
  207. return status;
  208. }
  209. return XST_SUCCESS;
  210. }
  211. void hdmi_set_video_mode(u16 htotal, u16 vtotal, u32 pixelclock_hz, u16 vhz, u8 hdmi) {
  212. /*
  213. * SII9022 registers
  214. *
  215. 0x00, 0x4c, // PixelClock/10000 - LSB
  216. 0x01, 0x1d, // PixelClock/10000 - MSB
  217. 0x02, 0x70, // Frequency in HZ - LSB
  218. 0x03, 0x17, // Vertical Frequency in HZ - MSB
  219. 0x04, 0x70, // Total Pixels per line - LSB
  220. 0x05, 0x06, // Total Pixels per line - MSB
  221. 0x06, 0xEE, // Total Lines - LSB
  222. 0x07, 0x02, // Total Lines - MSB
  223. 0x08, 0x70, // pixel repeat rate?
  224. 0x1a, 0x00, // 0: DVI, 1: HDMI
  225. */
  226. // see also https://github.com/torvalds/linux/blob/master/drivers/gpu/drm/bridge/sii902x.c#L358
  227. u8* sii_mode = sii9022_init + 12;
  228. sii_mode[2 * 0 + 1] = pixelclock_hz / 10000;
  229. sii_mode[2 * 1 + 1] = (pixelclock_hz / 10000) >> 8;
  230. sii_mode[2 * 2 + 1] = vhz * 100;
  231. sii_mode[2 * 3 + 1] = (vhz * 100) >> 8;
  232. sii_mode[2 * 4 + 1] = htotal;
  233. sii_mode[2 * 5 + 1] = htotal >> 8;
  234. sii_mode[2 * 6 + 1] = vtotal;
  235. sii_mode[2 * 7 + 1] = vtotal >> 8;
  236. sii_mode[2 * 9 + 1] = hdmi;
  237. }
  238. u32 dump_vdma_status(XAxiVdma *InstancePtr) {
  239. u32 status = XAxiVdma_GetStatus(InstancePtr, XAXIVDMA_READ);
  240. xil_printf("Read channel dump\n\r");
  241. xil_printf("\tMM2S DMA Control Register: %x\r\n",
  242. XAxiVdma_ReadReg(InstancePtr->ReadChannel.ChanBase,
  243. XAXIVDMA_CR_OFFSET));
  244. xil_printf("\tMM2S DMA Status Register: %x\r\n",
  245. XAxiVdma_ReadReg(InstancePtr->ReadChannel.ChanBase,
  246. XAXIVDMA_SR_OFFSET));
  247. xil_printf("\tMM2S HI_FRMBUF Reg: %x\r\n",
  248. XAxiVdma_ReadReg(InstancePtr->ReadChannel.ChanBase,
  249. XAXIVDMA_HI_FRMBUF_OFFSET));
  250. xil_printf("\tFRMSTORE Reg: %d\r\n",
  251. XAxiVdma_ReadReg(InstancePtr->ReadChannel.ChanBase,
  252. XAXIVDMA_FRMSTORE_OFFSET));
  253. xil_printf("\tBUFTHRES Reg: %d\r\n",
  254. XAxiVdma_ReadReg(InstancePtr->ReadChannel.ChanBase,
  255. XAXIVDMA_BUFTHRES_OFFSET));
  256. xil_printf("\tMM2S Vertical Size Register: %d\r\n",
  257. XAxiVdma_ReadReg(InstancePtr->ReadChannel.ChanBase,
  258. XAXIVDMA_MM2S_ADDR_OFFSET + XAXIVDMA_VSIZE_OFFSET));
  259. xil_printf("\tMM2S Horizontal Size Register: %d\r\n",
  260. XAxiVdma_ReadReg(InstancePtr->ReadChannel.ChanBase,
  261. XAXIVDMA_MM2S_ADDR_OFFSET + XAXIVDMA_HSIZE_OFFSET));
  262. xil_printf("\tMM2S Frame Delay and Stride Register: %d\r\n",
  263. XAxiVdma_ReadReg(InstancePtr->ReadChannel.ChanBase,
  264. XAXIVDMA_MM2S_ADDR_OFFSET + XAXIVDMA_STRD_FRMDLY_OFFSET));
  265. xil_printf("\tMM2S Start Address 1: %x\r\n",
  266. XAxiVdma_ReadReg(InstancePtr->ReadChannel.ChanBase,
  267. XAXIVDMA_MM2S_ADDR_OFFSET + XAXIVDMA_START_ADDR_OFFSET));
  268. xil_printf("VDMA status: ");
  269. if (status & XAXIVDMA_SR_HALTED_MASK)
  270. xil_printf("halted\n");
  271. else
  272. xil_printf("running\n");
  273. if (status & XAXIVDMA_SR_IDLE_MASK)
  274. xil_printf("idle\n");
  275. if (status & XAXIVDMA_SR_ERR_INTERNAL_MASK)
  276. xil_printf("internal err\n");
  277. if (status & XAXIVDMA_SR_ERR_SLAVE_MASK)
  278. xil_printf("slave err\n");
  279. if (status & XAXIVDMA_SR_ERR_DECODE_MASK)
  280. xil_printf("decode err\n");
  281. if (status & XAXIVDMA_SR_ERR_FSZ_LESS_MASK)
  282. xil_printf("FSize Less Mismatch err\n");
  283. if (status & XAXIVDMA_SR_ERR_LSZ_LESS_MASK)
  284. xil_printf("LSize Less Mismatch err\n");
  285. if (status & XAXIVDMA_SR_ERR_SG_SLV_MASK)
  286. xil_printf("SG slave err\n");
  287. if (status & XAXIVDMA_SR_ERR_SG_DEC_MASK)
  288. xil_printf("SG decode err\n");
  289. if (status & XAXIVDMA_SR_ERR_FSZ_MORE_MASK)
  290. xil_printf("FSize More Mismatch err\n");
  291. return status;
  292. }
  293. void fb_fill(uint32_t offset) {
  294. memset(framebuffer + offset, 0, 1280 * 1024 * 4);
  295. }
  296. static XClk_Wiz clkwiz;
  297. void pixelclock_init(int mhz) {
  298. XClk_Wiz_Config conf;
  299. XClk_Wiz_CfgInitialize(&clkwiz, &conf, XPAR_CLK_WIZ_0_BASEADDR);
  300. u32 phase = XClk_Wiz_ReadReg(XPAR_CLK_WIZ_0_BASEADDR, 0x20C);
  301. u32 duty = XClk_Wiz_ReadReg(XPAR_CLK_WIZ_0_BASEADDR, 0x210);
  302. u32 divide = XClk_Wiz_ReadReg(XPAR_CLK_WIZ_0_BASEADDR, 0x208);
  303. u32 muldiv = XClk_Wiz_ReadReg(XPAR_CLK_WIZ_0_BASEADDR, 0x200);
  304. u32 mul = 11;
  305. u32 div = 1;
  306. u32 otherdiv = 11;
  307. // Multiply/divide 100mhz fabric clock to desired pixel clock
  308. if (mhz == 50) {
  309. mul = 15;
  310. div = 1;
  311. otherdiv = 30;
  312. } else if (mhz == 40) {
  313. mul = 14;
  314. div = 1;
  315. otherdiv = 35;
  316. } else if (mhz == 75) {
  317. mul = 15;
  318. div = 1;
  319. otherdiv = 20;
  320. } else if (mhz == 65) {
  321. mul = 13;
  322. div = 1;
  323. otherdiv = 20;
  324. } else if (mhz == 27) {
  325. mul = 27;
  326. div = 2;
  327. otherdiv = 50;
  328. } else if (mhz == 54) {
  329. mul = 27;
  330. div = 1;
  331. otherdiv = 50;
  332. } else if (mhz == 150) {
  333. mul = 15;
  334. div = 1;
  335. otherdiv = 10;
  336. } else if (mhz == 25) { // 25.205
  337. mul = 15;
  338. div = 1;
  339. otherdiv = 60;
  340. } else if (mhz == 108) {
  341. mul = 54;
  342. div = 5;
  343. otherdiv = 10;
  344. }
  345. XClk_Wiz_WriteReg(XPAR_CLK_WIZ_0_BASEADDR, 0x200, (mul << 8) | div);
  346. XClk_Wiz_WriteReg(XPAR_CLK_WIZ_0_BASEADDR, 0x208, otherdiv);
  347. // load configuration
  348. XClk_Wiz_WriteReg(XPAR_CLK_WIZ_0_BASEADDR, 0x25C, 0x00000003);
  349. //XClk_Wiz_WriteReg(XPAR_CLK_WIZ_0_BASEADDR, 0x25C, 0x00000001);
  350. phase = XClk_Wiz_ReadReg(XPAR_CLK_WIZ_0_BASEADDR, 0x20C);
  351. printf("CLK phase: %lu\n", phase);
  352. duty = XClk_Wiz_ReadReg(XPAR_CLK_WIZ_0_BASEADDR, 0x210);
  353. printf("CLK duty: %lu\n", duty);
  354. divide = XClk_Wiz_ReadReg(XPAR_CLK_WIZ_0_BASEADDR, 0x208);
  355. printf("CLK divide: %lu\n", divide);
  356. muldiv = XClk_Wiz_ReadReg(XPAR_CLK_WIZ_0_BASEADDR, 0x200);
  357. printf("CLK muldiv: %lu\n", muldiv);
  358. }
  359. // FIXME!
  360. #define MNTZ_BASE_ADDR 0x43C00000
  361. #define MNTZORRO_REG0 0
  362. #define MNTZORRO_REG1 4
  363. #define MNTZORRO_REG2 8
  364. #define MNTZORRO_REG3 12
  365. #define mntzorro_read(BaseAddress, RegOffset) \
  366. Xil_In32((BaseAddress) + (RegOffset))
  367. #define mntzorro_write(BaseAddress, RegOffset, Data) \
  368. Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
  369. void video_formatter_valign() {
  370. // vertical alignment
  371. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG3, 1);
  372. usleep(1);
  373. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG2, 0x80000000 + 0x5); // OP_VSYNC
  374. usleep(1);
  375. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG3, 0);
  376. usleep(1);
  377. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG2, 0x80000000); // NOP
  378. usleep(1);
  379. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG2, 0); // NOP
  380. usleep(1);
  381. }
  382. #define VF_DLY ;
  383. #define MNTVF_OP_UNUSED 12
  384. #define MNTVF_OP_SPRITE_XY 13
  385. #define MNTVF_OP_SPRITE_ADDR 14
  386. #define MNTVF_OP_SPRITE_DATA 15
  387. #define MNTVF_OP_MAX 6
  388. #define MNTVF_OP_HS 7
  389. #define MNTVF_OP_VS 8
  390. #define MNTVF_OP_POLARITY 10
  391. #define MNTVF_OP_SCALE 4
  392. #define MNTVF_OP_DIMENSIONS 2
  393. #define MNTVF_OP_COLORMODE 1
  394. void video_formatter_write(uint32_t data, uint16_t op) {
  395. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG3, data);
  396. VF_DLY;
  397. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG2, 0x80000000 | op); // OP_MAX (vmax | hmax)
  398. VF_DLY;
  399. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG2, 0x80000000); // NOP
  400. VF_DLY;
  401. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG2, 0); // clear
  402. VF_DLY;
  403. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG3, 0); // clear
  404. VF_DLY;
  405. }
  406. void video_formatter_init(int scalemode, int colormode, int width, int height,
  407. int htotal, int vtotal, int hss, int hse, int vss, int vse,
  408. int polarity) {
  409. video_formatter_write((vtotal << 16) | htotal, MNTVF_OP_MAX);
  410. video_formatter_write((height << 16) | width, MNTVF_OP_DIMENSIONS);
  411. video_formatter_write((hss << 16) | hse, MNTVF_OP_HS);
  412. video_formatter_write((vss << 16) | vse, MNTVF_OP_VS);
  413. video_formatter_write(polarity, MNTVF_OP_POLARITY);
  414. video_formatter_write(scalemode, MNTVF_OP_SCALE);
  415. video_formatter_write(colormode, MNTVF_OP_COLORMODE);
  416. video_formatter_valign();
  417. }
  418. void video_system_init(int hres, int vres, int htotal, int vtotal, int mhz,
  419. int vhz, int hdiv, int vdiv, int hdmi) {
  420. printf("VSI: %d x %d [%d x %d] %d MHz %d Hz, hdiv: %d vdiv: %d\n", hres,
  421. vres, htotal, vtotal, mhz, vhz, hdiv, vdiv);
  422. printf("pixelclock_init()...\n");
  423. pixelclock_init(mhz);
  424. printf("...done.\n");
  425. printf("hdmi_set_video_mode()...\n");
  426. hdmi_set_video_mode(hres, vres, mhz, vhz, hdmi);
  427. printf("hdmi_ctrl_init()...\n");
  428. hdmi_ctrl_init();
  429. printf("init_vdma()...\n");
  430. init_vdma(hres, vres, hdiv, vdiv);
  431. printf("...done.\n");
  432. //dump_vdma_status(&vdma);
  433. }
  434. // Our address space is relative to the autoconfig base address (for example, it could be 0x600000)
  435. #define MNT_REG_BASE 0x000000
  436. #define MNT_FB_BASE 0x010000
  437. #define MNT_BASE_MODE MNT_REG_BASE+0x02
  438. #define MNT_BASE_CONFIG MNT_REG_BASE+0x04
  439. #define MNT_BASE_SPRITEX MNT_REG_BASE+0x06
  440. #define MNT_BASE_SPRITEY MNT_REG_BASE+0x08
  441. #define MNT_BASE_PAN_HI MNT_REG_BASE+0x0a
  442. #define MNT_BASE_PAN_LO MNT_REG_BASE+0x0c
  443. #define MNT_BASE_UNUSED MNT_REG_BASE+0x0e
  444. #define MNT_BASE_RECTOP MNT_REG_BASE+0x10
  445. #define MNT_BASE_BLIT_SRC_HI MNT_REG_BASE+0x28
  446. #define MNT_BASE_BLIT_SRC_LO MNT_REG_BASE+0x2a
  447. #define MNT_BASE_BLIT_DST_HI MNT_REG_BASE+0x2c
  448. #define MNT_BASE_BLIT_DST_LO MNT_REG_BASE+0x2e
  449. #define MNT_BASE_BLITTER_COLORMODE MNT_REG_BASE+0x30
  450. #define MNT_BASE_BLIT_SRC_PITCH MNT_REG_BASE+0x32
  451. #define MNT_BASE_ETH_TX MNT_REG_BASE+0x80
  452. #define MNT_BASE_ETH_RX MNT_REG_BASE+0x82
  453. #define MNT_BASE_ETH_MAC_HI MNT_REG_BASE+0x84
  454. #define MNT_BASE_ETH_MAC_HI2 MNT_REG_BASE+0x86
  455. #define MNT_BASE_ETH_MAC_LO MNT_REG_BASE+0x88
  456. #define MNT_BASE_RUN_HI MNT_REG_BASE+0x90
  457. #define MNT_BASE_RUN_LO MNT_REG_BASE+0x92
  458. #define MNT_BASE_RUN_ARGC MNT_REG_BASE+0x94
  459. #define MNT_BASE_RUN_ARG0 MNT_REG_BASE+0x96
  460. #define MNT_BASE_RUN_ARG1 MNT_REG_BASE+0x98
  461. #define MNT_BASE_RUN_ARG2 MNT_REG_BASE+0x9a
  462. #define MNT_BASE_RUN_ARG3 MNT_REG_BASE+0x9c
  463. #define MNT_BASE_RUN_ARG4 MNT_REG_BASE+0x9e
  464. #define MNT_BASE_RUN_ARG5 MNT_REG_BASE+0xa0
  465. #define MNT_BASE_RUN_ARG6 MNT_REG_BASE+0xa2
  466. #define MNT_BASE_RUN_ARG7 MNT_REG_BASE+0xa4
  467. #define MNT_BASE_EVENT_SERIAL MNT_REG_BASE+0xb0
  468. #define MNT_BASE_EVENT_CODE MNT_REG_BASE+0xb2
  469. #define MNT_BASE_FW_VERSION MNT_REG_BASE+0xc0
  470. #define MNT_BASE_USBBLK_TX_HI MNT_REG_BASE+0xd0
  471. #define MNT_BASE_USBBLK_TX_LO MNT_REG_BASE+0xd2
  472. #define MNT_BASE_USBBLK_RX_HI MNT_REG_BASE+0xd4
  473. #define MNT_BASE_USBBLK_RX_LO MNT_REG_BASE+0xd6
  474. #define MNT_BASE_USB_STATUS MNT_REG_BASE+0xd8
  475. #define MNT_BASE_USB_BUFSEL MNT_REG_BASE+0xda
  476. #define MNT_BASE_USB_CAPACITY MNT_REG_BASE+0xdc
  477. #define REVISION_MAJOR 1
  478. #define REVISION_MINOR 5
  479. #define ZZVMODE_1280x720 0
  480. #define ZZVMODE_800x600 1
  481. #define ZZVMODE_640x480 2
  482. #define ZZVMODE_1024x768 3
  483. #define ZZVMODE_1280x1024 4
  484. #define ZZVMODE_1920x1080_60 5
  485. #define ZZVMODE_720x576 6 // 50hz
  486. #define ZZVMODE_1920x1080_50 7 // 50hz
  487. #define ZZVMODE_720x480 8
  488. #define ZZVMODE_640x512 9
  489. void video_mode_init(int mode, int scalemode, int colormode) {
  490. int hres, vres, hmax, vmax, hstart, hend, vstart, vend, polarity, mhz, vhz, hdmi;
  491. int hdiv = 1, vdiv = 1;
  492. if (scalemode & 1)
  493. hdiv = 2;
  494. if (scalemode & 2)
  495. vdiv = 2;
  496. if (colormode == 0)
  497. hdiv *= 4;
  498. if (colormode == 1)
  499. hdiv *= 2;
  500. switch (mode) {
  501. case ZZVMODE_1280x720:
  502. hres = 1280;
  503. vres = 720;
  504. hstart = 1390;
  505. hend = 1430;
  506. hmax = 1650;
  507. vstart = 725;
  508. vend = 730;
  509. vmax = 750;
  510. polarity = 0;
  511. mhz = 75;
  512. vhz = 60;
  513. hdmi = 0;
  514. break;
  515. case ZZVMODE_800x600:
  516. hres = 800;
  517. vres = 600;
  518. hstart = 840;
  519. hend = 968;
  520. hmax = 1056;
  521. vstart = 601;
  522. vend = 605;
  523. vmax = 628;
  524. polarity = 0;
  525. mhz = 40;
  526. vhz = 60;
  527. hdmi = 0;
  528. break;
  529. case ZZVMODE_640x480:
  530. hres = 640;
  531. vres = 480;
  532. hstart = 656;
  533. hend = 752;
  534. hmax = 800;
  535. vstart = 490;
  536. vend = 492;
  537. vmax = 525;
  538. polarity = 0;
  539. mhz = 25;
  540. vhz = 60;
  541. hdmi = 0;
  542. break;
  543. case ZZVMODE_640x512:
  544. hres = 640;
  545. vres = 512;
  546. hstart = 840;
  547. hend = 968;
  548. hmax = 1056;
  549. vstart = 601;
  550. vend = 605;
  551. vmax = 628;
  552. polarity = 0;
  553. mhz = 40;
  554. vhz = 60;
  555. hdmi = 0;
  556. break;
  557. case ZZVMODE_720x480:
  558. hres = 720;
  559. vres = 480;
  560. hstart = 720;
  561. hend = 752;
  562. hmax = 800;
  563. vstart = 490;
  564. vend = 492;
  565. vmax = 525;
  566. polarity = 0;
  567. mhz = 25;
  568. vhz = 60;
  569. hdmi = 0;
  570. break;
  571. case ZZVMODE_1024x768:
  572. hres = 1024;
  573. vres = 768;
  574. hstart = 1048;
  575. hend = 1184;
  576. hmax = 1344;
  577. vstart = 771;
  578. vend = 777;
  579. vmax = 806;
  580. polarity = 0;
  581. mhz = 65;
  582. vhz = 60;
  583. hdmi = 0;
  584. break;
  585. case ZZVMODE_1280x1024:
  586. hres = 1280;
  587. vres = 1024;
  588. hstart = 1328;
  589. hend = 1440;
  590. hmax = 1688;
  591. vstart = 1025;
  592. vend = 1028;
  593. vmax = 1066;
  594. polarity = 0;
  595. mhz = 108;
  596. vhz = 60;
  597. hdmi = 0;
  598. break;
  599. case ZZVMODE_1920x1080_50:
  600. hres = 1920;
  601. vres = 1080;
  602. hstart = 2448;
  603. hend = 2492;
  604. hmax = 2640;
  605. vstart = 1084;
  606. vend = 1089;
  607. vmax = 1125;
  608. polarity = 0;
  609. mhz = 150;
  610. vhz = 50;
  611. hdmi = 0;
  612. break;
  613. case ZZVMODE_1920x1080_60:
  614. hres = 1920;
  615. vres = 1080;
  616. hstart = 2008;
  617. hend = 2052;
  618. hmax = 2200;
  619. vstart = 1084;
  620. vend = 1089;
  621. vmax = 1125;
  622. polarity = 0;
  623. mhz = 150;
  624. vhz = 50;
  625. hdmi = 0;
  626. break;
  627. case ZZVMODE_720x576:
  628. hres = 720;
  629. vres = 576;
  630. hstart = 732;
  631. hend = 796;
  632. hmax = 864;
  633. vstart = 581;
  634. vend = 586;
  635. vmax = 625;
  636. polarity = 1;
  637. mhz = 27;
  638. vhz = 50;
  639. hdmi = 0;
  640. break;
  641. default:
  642. printf("Error: unknown mode\n");
  643. return;
  644. }
  645. video_system_init(hres, vres, hmax, vmax, mhz, vhz, hdiv, vdiv, hdmi);
  646. video_formatter_init(scalemode, colormode, hres, vres, hmax, vmax, hstart,
  647. hend, vstart, vend, polarity);
  648. vmode_hsize = hres;
  649. vmode_vsize = vres;
  650. vmode_vdiv = vdiv;
  651. vmode_hdiv = hdiv;
  652. }
  653. int16_t sprite_x = 0, sprite_x_adj = 0;
  654. int16_t sprite_y = 0, sprite_y_adj = 0;
  655. uint16_t sprite_enabled = 0;
  656. uint32_t sprite_buf[32 * 48];
  657. uint8_t sprite_clipped = 0;
  658. int16_t sprite_clip_x = 0, sprite_clip_y = 0;
  659. int8_t sprite_x_offset = 0;
  660. int8_t sprite_y_offset = 0;
  661. uint8_t sprite_width = 16;
  662. uint8_t sprite_height = 16;
  663. uint32_t sprite_colors[4] = { 0x00ff00ff, 0x00000000, 0x00000000, 0x00000000 };
  664. uint8_t sprite_template[16*16] = {
  665. 0,0,0,1,1,0,0,0,0,0,0,0,0,0,0,0,
  666. 0,0,0,3,3,1,1,0,0,0,0,0,0,0,0,0,
  667. 0,0,0,2,3,3,3,1,1,0,0,0,0,0,0,0,
  668. 0,0,0,2,3,3,3,3,3,1,1,0,0,0,0,0,
  669. 0,0,0,0,2,3,3,3,3,3,3,1,1,0,0,0,
  670. 0,0,0,0,2,3,3,3,3,3,3,3,3,1,1,0,
  671. 0,0,0,0,0,2,3,3,3,3,3,3,3,3,2,0,
  672. 0,0,0,0,0,2,3,3,3,3,3,3,3,2,2,0,
  673. 0,0,0,0,0,0,2,3,3,3,3,3,3,2,0,0,
  674. 0,0,0,0,0,0,2,3,3,3,3,3,3,1,0,0,
  675. 0,0,0,0,0,0,0,2,3,3,2,2,3,3,1,0,
  676. 0,0,0,0,0,0,0,2,3,2,2,2,2,3,3,1,
  677. 0,0,0,0,0,0,0,0,2,2,0,0,2,2,3,2,
  678. 0,0,0,0,0,0,0,0,2,0,0,0,0,2,2,2,
  679. 0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,
  680. 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
  681. };
  682. void sprite_hide() {
  683. sprite_x = 2000;
  684. sprite_y = 2000;
  685. sprite_enabled = 0;
  686. video_formatter_write((sprite_y << 16) | sprite_x, MNTVF_OP_SPRITE_XY);
  687. }
  688. void sprite_reset() {
  689. sprite_hide();
  690. for (int y=0; y<16; y++) {
  691. for (int x=0; x<16; x++) {
  692. uint8_t addr = y*16+x;
  693. uint32_t data = 0xff00ff;
  694. if (sprite_template[y*16+x]==1) {
  695. data = 0xffffff;
  696. } else if (sprite_template[y*16+x]==2) {
  697. data = 0x000000;
  698. } else if (sprite_template[y*16+x]==3) {
  699. data = (255-15*y)<<16;
  700. }
  701. video_formatter_write((addr << 24) | data, MNTVF_OP_SPRITE_DATA);
  702. }
  703. }
  704. }
  705. // this mode can be changed by amiga software to select a different resolution / framerate for
  706. // native video capture
  707. //static int videocap_video_mode = ZZVMODE_720x576;
  708. //static int video_mode = ZZVMODE_720x576|2<<12|MNTVA_COLOR_32BIT<<8;
  709. //static int default_pan_offset = 0x00e00000;
  710. // default to more compatible 60hz mode
  711. static int videocap_video_mode = ZZVMODE_800x600;
  712. static int video_mode = ZZVMODE_800x600 | 2 << 12 | MNTVA_COLOR_32BIT << 8;
  713. static int default_pan_offset = 0x00e00bf8;
  714. static char usb_storage_available = 0;
  715. static uint32_t usb_storage_read_block = 0;
  716. static uint32_t usb_storage_write_block = 0;
  717. // ethernet state
  718. uint16_t ethernet_send_result = 0;
  719. // usb state
  720. uint16_t usb_status = 0;
  721. // we can read or write a number of USB blocks at once, and amiga can select which one is mapped at the USB storage buffer area
  722. uint32_t usb_selected_buffer_block = 0;
  723. uint32_t usb_read_write_num_blocks = 1;
  724. void videocap_area_clear() {
  725. fb_fill(0x00e00000 / 4);
  726. }
  727. void reset_default_videocap_pan() {
  728. if (videocap_video_mode == ZZVMODE_800x600) {
  729. default_pan_offset = 0x00e00bf8;
  730. } else {
  731. default_pan_offset = 0x00e00000;
  732. }
  733. }
  734. void handle_amiga_reset() {
  735. reset_default_videocap_pan();
  736. framebuffer_pan_offset = default_pan_offset;
  737. videocap_area_clear();
  738. printf(" _______________ ___ ___ ___ \n");
  739. printf(" |___ /___ / _ \\ / _ \\ / _ \\ / _ \\ \n");
  740. printf(" / / / / (_) | | | | | | | | | |\n");
  741. printf(" / / / / \\__, | | | | | | | | | |\n");
  742. printf(" / /__ / /__ / /| |_| | |_| | |_| |\n");
  743. printf(" /_____/_____|/_/ \\___/ \\___/ \\___/ \n\n");
  744. usleep(10000);
  745. // scalemode 2 (vertical doubling)
  746. video_mode_init(videocap_video_mode, 2, MNTVA_COLOR_32BIT);
  747. video_mode = videocap_video_mode | 2 << 12 | MNTVA_COLOR_32BIT << 8;
  748. sprite_reset();
  749. ethernet_init();
  750. usb_storage_available = zz_usb_init();
  751. usb_status = 0;
  752. usb_selected_buffer_block = 0;
  753. usb_read_write_num_blocks = 1;
  754. ethernet_send_result = 0;
  755. // FIXME there should be more state to be reset
  756. }
  757. uint16_t arm_app_output_event_serial = 0;
  758. uint16_t arm_app_output_event_code = 0;
  759. char arm_app_output_event_ack = 0;
  760. uint16_t arm_app_output_events_blocking = 0;
  761. uint16_t arm_app_output_putchar_to_events = 0;
  762. uint16_t arm_app_input_event_serial = 0;
  763. uint16_t arm_app_input_event_code = 0;
  764. char arm_app_input_event_ack = 0;
  765. uint32_t arm_app_output_events_timeout = 100000;
  766. void arm_app_put_event_code(uint16_t code) {
  767. arm_app_output_event_code = code;
  768. arm_app_output_event_ack = 0;
  769. arm_app_output_event_serial++;
  770. }
  771. char arm_app_output_event_acked() {
  772. return arm_app_output_event_ack;
  773. }
  774. void arm_app_set_output_events_blocking(char blocking) {
  775. arm_app_output_events_blocking = blocking;
  776. }
  777. void arm_app_set_output_putchar_to_events(char putchar_enabled) {
  778. arm_app_output_putchar_to_events = putchar_enabled;
  779. }
  780. uint16_t arm_app_get_event_serial() {
  781. return arm_app_input_event_serial;
  782. }
  783. uint16_t arm_app_get_event_code() {
  784. arm_app_input_event_ack = 1;
  785. return arm_app_input_event_code;
  786. }
  787. int __attribute__ ((visibility ("default"))) _putchar(char c) {
  788. if (arm_app_output_putchar_to_events) {
  789. if (arm_app_output_events_blocking) {
  790. for (uint32_t i = 0; i < arm_app_output_events_timeout; i++) {
  791. usleep(1);
  792. if (arm_app_output_event_ack)
  793. break;
  794. }
  795. }
  796. arm_app_put_event_code(c);
  797. }
  798. return putchar(c);
  799. }
  800. struct ZZ9K_ENV {
  801. uint32_t api_version;
  802. uint32_t argv[8];
  803. uint32_t argc;
  804. int (*fn_putchar)(char);
  805. void (*fn_set_output_putchar_to_events)(char);
  806. void (*fn_set_output_events_blocking)(char);
  807. void (*fn_put_event_code)(uint16_t);
  808. uint16_t (*fn_get_event_serial)();
  809. uint16_t (*fn_get_event_code)();
  810. char (*fn_output_event_acked)();
  811. };
  812. void arm_exception_handler(void *callback);
  813. void arm_exception_handler_illinst(void *callback);
  814. volatile struct ZZ9K_ENV arm_run_env;
  815. volatile void (*core1_trampoline)(volatile struct ZZ9K_ENV* env);
  816. volatile int core2_execute = 0;
  817. #pragma GCC push_options
  818. #pragma GCC optimize ("O1")
  819. // core1_loop is executed on core1 (vs core0)
  820. void core1_loop() {
  821. asm("mov r0, r0");
  822. asm("mrc p15, 0, r1, c1, c0, 2");
  823. /* read cp access control register (CACR) into r1 */
  824. asm("orr r1, r1, #(0xf << 20)");
  825. /* enable full access for p10 & p11 */
  826. asm("mcr p15, 0, r1, c1, c0, 2");
  827. /* write back into CACR */
  828. // enable FPU
  829. asm("fmrx r1, FPEXC");
  830. /* read the exception register */
  831. asm("orr r1,r1, #0x40000000");
  832. /* set VFP enable bit, leave the others in orig state */
  833. asm("fmxr FPEXC, r1");
  834. /* write back the exception register */
  835. // enable flow prediction
  836. asm("mrc p15,0,r0,c1,c0,0");
  837. /* flow prediction enable */
  838. asm("orr r0, r0, #(0x01 << 11)");
  839. /* #0x8000 */
  840. asm("mcr p15,0,r0,c1,c0,0");
  841. asm("mrc p15,0,r0,c1,c0,1");
  842. /* read Auxiliary Control Register */
  843. asm("orr r0, r0, #(0x1 << 2)");
  844. /* enable Dside prefetch */
  845. asm("orr r0, r0, #(0x1 << 1)");
  846. /* enable L2 Prefetch hint */
  847. asm("mcr p15,0,r0,c1,c0,1");
  848. /* write Auxiliary Control Register */
  849. // stack
  850. asm("mov sp, #0x06000000");
  851. volatile uint32_t* addr = 0;
  852. addr[0] = 0xe3e0000f; // mvn r0, #15 -- loads 0xfffffff0
  853. addr[1] = 0xe590f000; // ldr pc, [r0] -- jumps to the address in that address
  854. // FIXME these don't seem to do anything useful yet
  855. Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_RESET,
  856. (Xil_ExceptionHandler) arm_exception_handler, NULL);
  857. Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_DATA_ABORT_INT,
  858. (Xil_ExceptionHandler) arm_exception_handler, NULL);
  859. Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_PREFETCH_ABORT_INT,
  860. (Xil_ExceptionHandler) arm_exception_handler, NULL);
  861. Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_UNDEFINED_INT,
  862. (Xil_ExceptionHandler) arm_exception_handler_illinst, NULL);
  863. while (1) {
  864. while (!core2_execute) {
  865. usleep(1);
  866. }
  867. core2_execute = 0;
  868. printf("[CPU1] executing at %p.\n", core1_trampoline);
  869. Xil_DCacheFlush();
  870. Xil_ICacheInvalidate();
  871. asm("push {r0-r12}");
  872. // FIXME HACK save our stack pointer in 0x10000
  873. asm("mov r0, #0x00010000");
  874. asm("str sp, [r0]");
  875. core1_trampoline(&arm_run_env);
  876. asm("mov r0, #0x00010000");
  877. asm("ldr sp, [r0]");
  878. asm("pop {r0-r12}");
  879. }
  880. }
  881. #pragma GCC pop_options
  882. int main() {
  883. const char* zstates[53] = { "RESET ", "Z2_CONF ", "Z2_IDLE ", "WAIT_WRI",
  884. "WAIT_WR2", "Z2WRIFIN", "WAIT_RD ", "WAIT_RD2", "WAIT_RD3",
  885. "CONFIGED", "CONF_CLR", "D_Z2_Z3 ", "Z3_IDLE ", "Z3_WRITE_UPP",
  886. "Z3_WRITE_LOW", "Z3_READ_UP", "Z3_READ_LOW", "Z3_READ_DLY",
  887. "Z3_READ_DLY1", "Z3_READ_DLY2", "Z3_WRITE_PRE", "Z3_WRITE_FIN",
  888. "Z3_ENDCYCLE", "Z3_DTACK", "Z3_CONFIG", "Z2_REGWRITE", "REGWRITE",
  889. "REGREAD", "Z2_REGR_POST", "Z3_REGR_POST", "Z3_REGWRITE",
  890. "Z2_REGREAD", "Z3_REGREAD", "NONE_33", "Z2_PRE_CONF", "Z2_ENDCYCLE",
  891. "NONE_36", "NONE_37", "NONE_38", "RESET_DVID", "COLD", "WR2B",
  892. "WR2C", "Z3DMA1", "Z3DMA2", "Z3_AUTOCONF_RD", "Z3_AUTOCONF_WR",
  893. "Z3_AUTOCONF_RD_DLY", "Z3_AUTOCONF_RD_DLY2", "Z3_REGWRITE_PRE",
  894. "Z3_REGREAD_PRE", "Z3_WRITE_PRE2", "UNDEF", };
  895. init_platform();
  896. Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_DATA_ABORT_INT,
  897. (Xil_ExceptionHandler) arm_exception_handler, NULL);
  898. Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_PREFETCH_ABORT_INT,
  899. (Xil_ExceptionHandler) arm_exception_handler, NULL);
  900. Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_UNDEFINED_INT,
  901. (Xil_ExceptionHandler) arm_exception_handler_illinst, NULL);
  902. disable_reset_out();
  903. // FIXME constant
  904. framebuffer = (u32*) 0x00200000;
  905. int need_req_ack = 0;
  906. u8* mem = (u8*) framebuffer;
  907. // blitter etc
  908. uint16_t rect_x1 = 0;
  909. uint16_t rect_x2 = 0;
  910. uint16_t rect_x3 = 0;
  911. uint16_t rect_y1 = 0;
  912. uint16_t rect_y2 = 0;
  913. uint16_t rect_y3 = 0;
  914. uint16_t blitter_dst_pitch = 640;
  915. uint32_t rect_rgb = 0;
  916. uint32_t rect_rgb2 = 0;
  917. uint32_t blitter_colormode = MNTVA_COLOR_32BIT;
  918. uint16_t blitter_src_pitch = 0;
  919. uint16_t blitter_user1 = 0;
  920. uint16_t blitter_user2 = 0;
  921. uint16_t blitter_user3 = 0;
  922. uint16_t blitter_user4 = 0;
  923. // ARM app run environment
  924. arm_run_env.api_version = 1;
  925. arm_run_env.fn_putchar = _putchar;
  926. arm_run_env.fn_get_event_code = arm_app_get_event_code;
  927. arm_run_env.fn_get_event_serial = arm_app_get_event_serial;
  928. arm_run_env.fn_output_event_acked = arm_app_output_event_acked;
  929. arm_run_env.fn_put_event_code = arm_app_put_event_code;
  930. arm_run_env.fn_set_output_events_blocking =
  931. arm_app_set_output_events_blocking;
  932. arm_run_env.fn_set_output_putchar_to_events =
  933. arm_app_set_output_putchar_to_events;
  934. arm_run_env.argc = 0;
  935. uint32_t arm_run_address = 0;
  936. // zorro state
  937. u32 zstate_raw;
  938. int interlace_old = 0;
  939. int videocap_ntsc_old = 0;
  940. handle_amiga_reset();
  941. printf("launch core1...\n");
  942. volatile uint32_t* core1_addr = (volatile uint32_t*) 0xFFFFFFF0;
  943. *core1_addr = (uint32_t) core1_loop;
  944. // Place some machine code in strategic positions that will catch core1 if it crashes
  945. // FIXME: clean this up and turn into a debug handler / monitor
  946. volatile uint32_t* core1_addr2 = (volatile uint32_t*) 0x140; // catch 1
  947. core1_addr2[0] = 0xe3e0000f; // mvn r0, #15 -- loads 0xfffffff0
  948. core1_addr2[1] = 0xe590f000; // ldr pc, [r0] -- jumps to the address in that address
  949. core1_addr2 = (volatile uint32_t*) 0x100; // catch 2
  950. core1_addr2[0] = 0xe3e0000f; // mvn r0, #15 -- loads 0xfffffff0
  951. core1_addr2[1] = 0xe590f000; // ldr pc, [r0] -- jumps to the address in that address
  952. asm("sev");
  953. printf("core1 now idling.\n");
  954. int cache_counter = 0;
  955. int videocap_enabled_old = 1;
  956. int scalemode = 0;
  957. int colormode = 0;
  958. uint32_t framebuffer_pan_offset_old = framebuffer_pan_offset;
  959. video_mode = 0x2200;
  960. int backlog_nag_counter = 0;
  961. int interrupt_enabled = 0;
  962. int request_video_align=0;
  963. int vblank=0;
  964. while (1) {
  965. u32 zstate = mntzorro_read(MNTZ_BASE_ADDR, MNTZORRO_REG3);
  966. zstate_raw = zstate;
  967. u32 writereq = (zstate & (1 << 31));
  968. u32 readreq = (zstate & (1 << 30));
  969. zstate = zstate & 0xff;
  970. if (zstate > 52) zstate = 52;
  971. if (writereq) {
  972. u32 zaddr = mntzorro_read(MNTZ_BASE_ADDR, MNTZORRO_REG0);
  973. u32 zdata = mntzorro_read(MNTZ_BASE_ADDR, MNTZORRO_REG1);
  974. u32 ds3 = (zstate_raw & (1 << 29));
  975. u32 ds2 = (zstate_raw & (1 << 28));
  976. u32 ds1 = (zstate_raw & (1 << 27));
  977. u32 ds0 = (zstate_raw & (1 << 26));
  978. //printf("WRTE: %08lx <- %08lx [%d%d%d%d]\n",zaddr,zdata,!!ds3,!!ds2,!!ds1,!!ds0);
  979. if (zaddr > 0x10000000) {
  980. printf("ERRW illegal address %08lx\n", zaddr);
  981. } else if (zaddr >= MNT_FB_BASE || zaddr >= MNT_REG_BASE + 0x2000) {
  982. u8* ptr = mem;
  983. if (zaddr >= MNT_FB_BASE) {
  984. ptr = mem + zaddr - MNT_FB_BASE;
  985. } else if (zaddr < MNT_REG_BASE + 0x8000) {
  986. // FIXME remove
  987. ptr = (u8*) (RX_FRAME_ADDRESS + zaddr - (MNT_REG_BASE + 0x2000));
  988. //printf("ERXF write: %08lx\n", (u32) ptr);
  989. } else if (zaddr < MNT_REG_BASE + 0xa000) {
  990. ptr = (u8*) (TX_FRAME_ADDRESS + zaddr - (MNT_REG_BASE + 0x8000));
  991. } else if (zaddr < MNT_REG_BASE + 0x10000) {
  992. // 0xa000-0xafff: write to block device (usb storage)
  993. // TODO: this should be moved to DMA space?
  994. ptr = (u8*) (USB_BLOCK_STORAGE_ADDRESS + zaddr - (MNT_REG_BASE + 0xa000) + usb_selected_buffer_block * 512);
  995. }
  996. // FIXME cache this
  997. u32 z3 = (zstate_raw & (1 << 25));
  998. if (z3) {
  999. if (ds3) ptr[0] = zdata >> 24;
  1000. if (ds2) ptr[1] = zdata >> 16;
  1001. if (ds1) ptr[2] = zdata >> 8;
  1002. if (ds0) ptr[3] = zdata;
  1003. } else {
  1004. // swap bytes
  1005. if (ds1) ptr[0] = zdata >> 8;
  1006. if (ds0) ptr[1] = zdata;
  1007. }
  1008. } else if (zaddr >= MNT_REG_BASE && zaddr < MNT_FB_BASE) {
  1009. // register area
  1010. //printf("REGW: %08lx <- %08lx [%d%d%d%d]\n",zaddr,zdata,!!ds3,!!ds2,!!ds1,!!ds0);
  1011. u32 z3 = (zstate_raw & (1 << 25));
  1012. if (z3) {
  1013. // convert 32bit to 16bit addresses
  1014. if (ds3 && ds2) {
  1015. zdata = zdata >> 16;
  1016. } else if (ds1 && ds0) {
  1017. zdata = zdata & 0xffff;
  1018. zaddr += 2;
  1019. } else {
  1020. zaddr = 0; // cancel
  1021. }
  1022. }
  1023. //printf("CONV: %08lx <- %08lx\n",zaddr,zdata);
  1024. switch (zaddr) {
  1025. // Various blitter/video registers
  1026. case MNT_BASE_PAN_HI:
  1027. framebuffer_pan_offset = zdata << 16;
  1028. break;
  1029. case MNT_BASE_PAN_LO:
  1030. framebuffer_pan_offset |= zdata;
  1031. if (framebuffer_pan_offset != framebuffer_pan_offset_old) {
  1032. // VDMA will be reinitialized on the next vertical blank
  1033. request_video_align = 1;
  1034. framebuffer_pan_offset_old = framebuffer_pan_offset;
  1035. }
  1036. break;
  1037. case MNT_BASE_BLIT_SRC_HI:
  1038. blitter_src_offset = zdata << 16;
  1039. break;
  1040. case MNT_BASE_BLIT_SRC_LO:
  1041. blitter_src_offset |= zdata;
  1042. break;
  1043. case MNT_BASE_BLIT_DST_HI:
  1044. blitter_dst_offset = zdata << 16;
  1045. break;
  1046. case MNT_BASE_BLIT_DST_LO:
  1047. blitter_dst_offset |= zdata;
  1048. break;
  1049. case MNT_BASE_BLITTER_COLORMODE:
  1050. blitter_colormode = zdata;
  1051. break;
  1052. case MNT_BASE_CONFIG:
  1053. // enable/disable INT6, currently used to signal incoming ethernet packets
  1054. interrupt_enabled = zdata & 1;
  1055. break;
  1056. case MNT_BASE_MODE:
  1057. printf("mode change: %lx\n", zdata);
  1058. if (video_mode != zdata) {
  1059. int mode = zdata & 0xff;
  1060. colormode = (zdata & 0xf00) >> 8;
  1061. scalemode = (zdata & 0xf000) >> 12;
  1062. printf("mode: %d color: %d scale: %d\n", mode,
  1063. colormode, scalemode);
  1064. video_mode_init(mode, scalemode, colormode);
  1065. }
  1066. // remember selected video mode
  1067. video_mode = zdata;
  1068. break;
  1069. case MNT_BASE_SPRITEX:
  1070. case MNT_BASE_SPRITEY:
  1071. if (!sprite_enabled)
  1072. break;
  1073. if (zaddr == MNT_BASE_SPRITEX) {
  1074. // The "+#" offset at the end is dependent on implementation timing slack, and needs
  1075. // to be adjusted based on the sprite X offset produced by the current run.
  1076. sprite_x = (int16_t)zdata + sprite_x_offset + 3;
  1077. sprite_x_adj = sprite_x;
  1078. // horizontally doubled mode
  1079. if (scalemode&1) sprite_x*=2;
  1080. }
  1081. else {
  1082. sprite_y = (int16_t)zdata + sprite_y_offset;
  1083. sprite_y_adj = sprite_y;
  1084. // vertically doubled mode
  1085. if (scalemode&2) sprite_y*=2;
  1086. if (sprite_x < 0 || sprite_y < 0) {
  1087. if (sprite_clip_x != sprite_x || sprite_clip_y != sprite_y) {
  1088. clip_hw_sprite((sprite_x < 0) ? sprite_x : 0, (sprite_y < 0) ? sprite_y : 0);
  1089. }
  1090. sprite_clipped = 1;
  1091. if (sprite_x < 0) {
  1092. sprite_x_adj = 0;
  1093. sprite_clip_x = sprite_x;
  1094. }
  1095. if (sprite_y < 0) {
  1096. sprite_y_adj = 0;
  1097. sprite_clip_y = sprite_y;
  1098. }
  1099. }
  1100. else if (sprite_clipped && sprite_x >= 0 && sprite_y >= 0) {
  1101. clip_hw_sprite(0, 0);
  1102. sprite_clipped = 0;
  1103. }
  1104. video_formatter_write((sprite_y_adj << 16) | sprite_x_adj, MNTVF_OP_SPRITE_XY);
  1105. }
  1106. break;
  1107. case MNT_BASE_RECTOP + 0x38: { // SPRITE_BITMAP
  1108. if (zdata == 1) { // Hardware sprite enabled
  1109. sprite_enabled = 1;
  1110. break;
  1111. }
  1112. else if (zdata == 2) { // Hardware sprite disabled
  1113. sprite_hide();
  1114. break;
  1115. }
  1116. uint8_t* bmp_data = (uint8_t*) ((u32) framebuffer
  1117. + blitter_src_offset);
  1118. clear_hw_sprite();
  1119. sprite_x_offset = rect_x1;
  1120. sprite_y_offset = rect_y1;
  1121. sprite_width = rect_x2;
  1122. sprite_height = rect_y2;
  1123. update_hw_sprite(bmp_data, sprite_colors, sprite_width, sprite_height);
  1124. break;
  1125. }
  1126. case MNT_BASE_RECTOP + 0x3a: { // SPRITE_COLORS
  1127. sprite_colors[zdata] = (blitter_user1 << 16) | blitter_user2;
  1128. if (sprite_colors[zdata] == 0xff00ff) sprite_colors[zdata] = 0xfe00fe;
  1129. break;
  1130. }
  1131. case MNT_BASE_BLIT_SRC_PITCH:
  1132. blitter_src_pitch = zdata;
  1133. break;
  1134. case MNT_BASE_RECTOP:
  1135. rect_x1 = zdata;
  1136. break;
  1137. case MNT_BASE_RECTOP + 2:
  1138. rect_y1 = zdata;
  1139. break;
  1140. case MNT_BASE_RECTOP + 4:
  1141. rect_x2 = zdata;
  1142. break;
  1143. case MNT_BASE_RECTOP + 6:
  1144. rect_y2 = zdata;
  1145. break;
  1146. case MNT_BASE_RECTOP + 8:
  1147. blitter_dst_pitch = zdata;
  1148. break;
  1149. case MNT_BASE_RECTOP + 0xa:
  1150. rect_x3 = zdata;
  1151. break;
  1152. case MNT_BASE_RECTOP + 0xc:
  1153. rect_y3 = zdata;
  1154. break;
  1155. case MNT_BASE_RECTOP + 0x30:
  1156. blitter_user1 = zdata;
  1157. break;
  1158. case MNT_BASE_RECTOP + 0x32:
  1159. blitter_user2 = zdata;
  1160. break;
  1161. case MNT_BASE_RECTOP + 0x34:
  1162. blitter_user3 = zdata;
  1163. break;
  1164. case MNT_BASE_RECTOP + 0x36:
  1165. blitter_user4 = zdata;
  1166. break;
  1167. case MNT_BASE_RECTOP + 0xe:
  1168. rect_rgb &= 0xffff0000;
  1169. rect_rgb |= (((zdata & 0xff) << 8) | zdata >> 8);
  1170. break;
  1171. case MNT_BASE_RECTOP + 0x10:
  1172. rect_rgb &= 0x0000ffff;
  1173. rect_rgb |= (((zdata & 0xff) << 8) | zdata >> 8) << 16;
  1174. break;
  1175. case MNT_BASE_RECTOP + 0x24:
  1176. rect_rgb2 &= 0xffff0000;
  1177. rect_rgb2 |= (((zdata & 0xff) << 8) | zdata >> 8);
  1178. break;
  1179. case MNT_BASE_RECTOP + 0x26:
  1180. rect_rgb2 &= 0x0000ffff;
  1181. rect_rgb2 |= (((zdata & 0xff) << 8) | zdata >> 8) << 16;
  1182. break;
  1183. // RTG rendering
  1184. case MNT_BASE_RECTOP + 0x12:
  1185. // fill rectangle
  1186. set_fb((uint32_t*) ((u32) framebuffer + blitter_dst_offset),
  1187. blitter_dst_pitch);
  1188. uint8_t mask = zdata;
  1189. if (mask == 0xFF)
  1190. fill_rect_solid(rect_x1, rect_y1, rect_x2, rect_y2,
  1191. rect_rgb, blitter_colormode);
  1192. else
  1193. fill_rect(rect_x1, rect_y1, rect_x2, rect_y2, rect_rgb,
  1194. blitter_colormode, mask);
  1195. break;
  1196. case MNT_BASE_RECTOP + 0x14: {
  1197. // copy rectangle
  1198. set_fb((uint32_t*) ((u32) framebuffer + blitter_dst_offset),
  1199. blitter_dst_pitch);
  1200. mask = (blitter_colormode >> 8);
  1201. switch (zdata) {
  1202. case 1: // Regular BlitRect
  1203. if (mask == 0xFF || (mask != 0xFF && (blitter_colormode & 0x0F)) != MNTVA_COLOR_8BIT)
  1204. copy_rect_nomask(rect_x1, rect_y1, rect_x2, rect_y2, rect_x3,
  1205. rect_y3, blitter_colormode & 0x0F,
  1206. (uint32_t*) ((u32) framebuffer
  1207. + blitter_dst_offset),
  1208. blitter_dst_pitch, MINTERM_SRC);
  1209. else
  1210. copy_rect(rect_x1, rect_y1, rect_x2, rect_y2, rect_x3,
  1211. rect_y3, blitter_colormode & 0x0F,
  1212. (uint32_t*) ((u32) framebuffer
  1213. + blitter_dst_offset),
  1214. blitter_dst_pitch, mask);
  1215. break;
  1216. case 2: // BlitRectNoMaskComplete
  1217. copy_rect_nomask(rect_x1, rect_y1, rect_x2, rect_y2, rect_x3,
  1218. rect_y3, blitter_colormode & 0x0F,
  1219. (uint32_t*) ((u32) framebuffer
  1220. + blitter_src_offset),
  1221. blitter_src_pitch, mask); // Mask in this case is minterm/opcode.
  1222. break;
  1223. }
  1224. break;
  1225. }
  1226. case MNT_BASE_RECTOP + 0x16: {
  1227. uint8_t draw_mode = blitter_colormode >> 8;
  1228. uint8_t* tmpl_data = (uint8_t*) ((u32) framebuffer
  1229. + blitter_src_offset);
  1230. set_fb((uint32_t*) ((u32) framebuffer + blitter_dst_offset),
  1231. blitter_dst_pitch);
  1232. uint8_t bpp = 2 * (blitter_colormode & 0xff);
  1233. if (bpp == 0)
  1234. bpp = 1;
  1235. uint16_t loop_rows = 0;
  1236. mask = zdata;
  1237. if (zdata & 0x8000) {
  1238. // pattern mode
  1239. // TODO yoffset
  1240. loop_rows = zdata & 0xff;
  1241. mask = blitter_user1;
  1242. blitter_src_pitch = 16;
  1243. pattern_fill_rect((blitter_colormode & 0x0F), rect_x1,
  1244. rect_y1, rect_x2, rect_y2, draw_mode, mask,
  1245. rect_rgb, rect_rgb2, rect_x3, rect_y3, tmpl_data,
  1246. blitter_src_pitch, loop_rows);
  1247. }
  1248. else {
  1249. template_fill_rect((blitter_colormode & 0x0F), rect_x1,
  1250. rect_y1, rect_x2, rect_y2, draw_mode, mask,
  1251. rect_rgb, rect_rgb2, rect_x3, rect_y3, tmpl_data,
  1252. blitter_src_pitch);
  1253. }
  1254. break;
  1255. }
  1256. case MNT_BASE_RECTOP + 0x28: {
  1257. // Rect P2C
  1258. uint8_t draw_mode = blitter_colormode >> 8;
  1259. uint8_t planes = (zdata & 0xFF00) >> 8;
  1260. uint8_t mask = (zdata & 0xFF);
  1261. uint16_t num_rows = blitter_user1;
  1262. uint8_t layer_mask = blitter_user2;
  1263. uint8_t* bmp_data = (uint8_t*) ((u32) framebuffer
  1264. + blitter_src_offset);
  1265. set_fb((uint32_t*) ((u32) framebuffer + blitter_dst_offset),
  1266. blitter_dst_pitch);
  1267. p2c_rect(rect_x1, 0, rect_x2, rect_y2, rect_x3,
  1268. rect_y3, num_rows, draw_mode, planes, mask,
  1269. layer_mask, blitter_src_pitch, bmp_data);
  1270. break;
  1271. }
  1272. case MNT_BASE_RECTOP + 0x2c: {
  1273. // Rect P2D
  1274. uint8_t draw_mode = blitter_colormode >> 8;
  1275. uint8_t planes = (zdata & 0xFF00) >> 8;
  1276. uint8_t mask = (zdata & 0xFF);
  1277. uint16_t num_rows = blitter_user1;
  1278. uint8_t layer_mask = blitter_user2;
  1279. uint8_t* bmp_data = (uint8_t*) ((u32) framebuffer
  1280. + blitter_src_offset);
  1281. set_fb((uint32_t*) ((u32) framebuffer + blitter_dst_offset),
  1282. blitter_dst_pitch);
  1283. p2d_rect(rect_x1, 0, rect_x2, rect_y2, rect_x3,
  1284. rect_y3, num_rows, draw_mode, planes, mask, layer_mask, rect_rgb,
  1285. blitter_src_pitch, bmp_data, (blitter_colormode & 0x0F));
  1286. break;
  1287. }
  1288. case MNT_BASE_RECTOP + 0x2a: {
  1289. // DrawLine
  1290. uint8_t draw_mode = blitter_colormode >> 8;
  1291. set_fb((uint32_t*) ((u32) framebuffer + blitter_dst_offset),
  1292. blitter_dst_pitch);
  1293. // rect_x3 contains the pattern. if all bits are set for both the mask and the pattern,
  1294. // there's no point in passing non-essential data to the pattern/mask aware function.
  1295. if (rect_x3 == 0xFFFF && zdata == 0xFF)
  1296. draw_line_solid(rect_x1, rect_y1, rect_x2, rect_y2,
  1297. blitter_user1, rect_rgb,
  1298. (blitter_colormode & 0x0F));
  1299. else
  1300. draw_line(rect_x1, rect_y1, rect_x2, rect_y2,
  1301. blitter_user1, rect_x3, rect_y3, rect_rgb,
  1302. rect_rgb2, (blitter_colormode & 0x0F), zdata,
  1303. draw_mode);
  1304. break;
  1305. }
  1306. case MNT_BASE_RECTOP + 0x2e:
  1307. // InvertRect
  1308. set_fb((uint32_t*) ((u32) framebuffer + blitter_dst_offset),
  1309. blitter_dst_pitch);
  1310. invert_rect(rect_x1, rect_y1, rect_x2, rect_y2,
  1311. zdata & 0xFF, blitter_colormode);
  1312. break;
  1313. // Ethernet
  1314. case MNT_BASE_ETH_TX:
  1315. ethernet_send_result = ethernet_send_frame(zdata);
  1316. //printf("SEND frame sz: %ld res: %d\n",zdata,ethernet_send_result);
  1317. break;
  1318. case MNT_BASE_ETH_RX:
  1319. //printf("RECV eth frame sz: %ld\n",zdata);
  1320. ethernet_receive_frame();
  1321. break;
  1322. case MNT_BASE_ETH_MAC_HI: {
  1323. uint8_t* mac = ethernet_get_mac_address_ptr();
  1324. mac[0] = (zdata & 0xff00) >> 8;
  1325. mac[1] = (zdata & 0x00ff);
  1326. break;
  1327. }
  1328. case MNT_BASE_ETH_MAC_HI2: {
  1329. uint8_t* mac = ethernet_get_mac_address_ptr();
  1330. mac[2] = (zdata & 0xff00) >> 8;
  1331. mac[3] = (zdata & 0x00ff);
  1332. break;
  1333. }
  1334. case MNT_BASE_ETH_MAC_LO: {
  1335. uint8_t* mac = ethernet_get_mac_address_ptr();
  1336. mac[4] = (zdata & 0xff00) >> 8;
  1337. mac[5] = (zdata & 0x00ff);
  1338. ethernet_update_mac_address();
  1339. break;
  1340. }
  1341. case MNT_BASE_USBBLK_TX_HI: {
  1342. usb_storage_write_block = ((u32) zdata) << 16;
  1343. break;
  1344. }
  1345. case MNT_BASE_USBBLK_TX_LO: {
  1346. usb_storage_write_block |= zdata;
  1347. if (usb_storage_available) {
  1348. usb_status = zz_usb_write_blocks(0, usb_storage_write_block, usb_read_write_num_blocks, (void*)USB_BLOCK_STORAGE_ADDRESS);
  1349. } else {
  1350. printf("[USB] TX but no storage available!\n");
  1351. }
  1352. break;
  1353. }
  1354. case MNT_BASE_USBBLK_RX_HI: {
  1355. usb_storage_read_block = ((u32) zdata) << 16;
  1356. break;
  1357. }
  1358. case MNT_BASE_USBBLK_RX_LO: {
  1359. usb_storage_read_block |= zdata;
  1360. if (usb_storage_available) {
  1361. usb_status = zz_usb_read_blocks(0, usb_storage_read_block, usb_read_write_num_blocks, (void*)USB_BLOCK_STORAGE_ADDRESS);
  1362. } else {
  1363. printf("[USB] RX but no storage available!\n");
  1364. }
  1365. break;
  1366. }
  1367. case MNT_BASE_USB_STATUS: {
  1368. //printf("[USB] write to status/blocknum register: %d\n", zdata);
  1369. if (zdata==0) {
  1370. // reset USB
  1371. // FIXME memory leaks?
  1372. //usb_storage_available = zz_usb_init();
  1373. } else {
  1374. // set number of blocks to read/write at once
  1375. usb_read_write_num_blocks = zdata;
  1376. }
  1377. }
  1378. case MNT_BASE_USB_BUFSEL: {
  1379. //printf("[USB] select buffer: %d\n", zdata);
  1380. usb_selected_buffer_block = zdata;
  1381. }
  1382. // ARM core 2 execution
  1383. case MNT_BASE_RUN_HI:
  1384. arm_run_address = ((u32) zdata) << 16;
  1385. break;
  1386. case MNT_BASE_RUN_LO:
  1387. // TODO checksum?
  1388. arm_run_address |= zdata;
  1389. *core1_addr = (uint32_t) core1_loop;
  1390. core1_addr2[0] = 0xe3e0000f; // mvn r0, #15 -- loads 0xfffffff0
  1391. core1_addr2[1] = 0xe590f000; // ldr pc, [r0] -- jumps to the address in that address
  1392. printf("[ARM_RUN] %lx\n", arm_run_address);
  1393. if (arm_run_address > 0) {
  1394. core1_trampoline = (volatile void (*)(
  1395. volatile struct ZZ9K_ENV*)) arm_run_address;
  1396. printf("[ARM_RUN] signaling second core.\n");
  1397. Xil_DCacheFlush();
  1398. Xil_ICacheInvalidate();
  1399. core2_execute = 1;
  1400. Xil_DCacheFlush();
  1401. Xil_ICacheInvalidate();
  1402. } else {
  1403. core1_trampoline = 0;
  1404. core2_execute = 0;
  1405. }
  1406. // FIXME move this out of here
  1407. // sequence to reset cpu1 taken from https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842504/XAPP1079+Latest+Information
  1408. Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
  1409. uint32_t RegVal = Xil_In32(A9_CPU_RST_CTRL);
  1410. RegVal |= A9_RST1_MASK;
  1411. Xil_Out32(A9_CPU_RST_CTRL, RegVal);
  1412. RegVal |= A9_CLKSTOP1_MASK;
  1413. Xil_Out32(A9_CPU_RST_CTRL, RegVal);
  1414. RegVal &= ~A9_RST1_MASK;
  1415. Xil_Out32(A9_CPU_RST_CTRL, RegVal);
  1416. RegVal &= ~A9_CLKSTOP1_MASK;
  1417. Xil_Out32(A9_CPU_RST_CTRL, RegVal);
  1418. Xil_Out32(XSLCR_LOCK_ADDR, XSLCR_LOCK_CODE);
  1419. dmb();
  1420. dsb();
  1421. isb();
  1422. asm("sev");
  1423. break;
  1424. case MNT_BASE_RUN_ARGC:
  1425. arm_run_env.argc = zdata;
  1426. break;
  1427. case MNT_BASE_RUN_ARG0:
  1428. arm_run_env.argv[0] = ((u32) zdata) << 16;
  1429. break;
  1430. case MNT_BASE_RUN_ARG1:
  1431. arm_run_env.argv[0] |= zdata;
  1432. printf("ARG0 set: %lx\n", arm_run_env.argv[0]);
  1433. break;
  1434. case MNT_BASE_RUN_ARG2:
  1435. arm_run_env.argv[1] = ((u32) zdata) << 16;
  1436. break;
  1437. case MNT_BASE_RUN_ARG3:
  1438. arm_run_env.argv[1] |= zdata;
  1439. printf("ARG1 set: %lx\n", arm_run_env.argv[1]);
  1440. break;
  1441. case MNT_BASE_RUN_ARG4:
  1442. arm_run_env.argv[2] = ((u32) zdata) << 16;
  1443. break;
  1444. case MNT_BASE_RUN_ARG5:
  1445. arm_run_env.argv[2] |= zdata;
  1446. printf("ARG2 set: %lx\n", arm_run_env.argv[2]);
  1447. break;
  1448. case MNT_BASE_RUN_ARG6:
  1449. arm_run_env.argv[3] = ((u32) zdata) << 16;
  1450. break;
  1451. case MNT_BASE_RUN_ARG7:
  1452. arm_run_env.argv[3] |= zdata;
  1453. printf("ARG3 set: %lx\n", arm_run_env.argv[3]);
  1454. break;
  1455. case MNT_BASE_EVENT_CODE:
  1456. arm_app_input_event_code = zdata;
  1457. arm_app_input_event_serial++;
  1458. arm_app_input_event_ack = 0;
  1459. break;
  1460. }
  1461. }
  1462. // ack the write, set bit 31 in register 0
  1463. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG0, (1 << 31));
  1464. need_req_ack = 1;
  1465. } else if (readreq) {
  1466. uint32_t zaddr = mntzorro_read(MNTZ_BASE_ADDR, MNTZORRO_REG0);
  1467. //printf("READ: %08lx\n",zaddr);
  1468. u32 z3 = (zstate_raw & (1 << 25)); // TODO cache
  1469. if (zaddr > 0x10000000) {
  1470. printf("ERRR: illegal address %08lx\n", zaddr);
  1471. }
  1472. if (zaddr >= MNT_FB_BASE || zaddr >= MNT_REG_BASE + 0x2000) {
  1473. u8* ptr = mem;
  1474. if (zaddr >= MNT_FB_BASE) {
  1475. // read from framebuffer / generic memory
  1476. ptr = mem + zaddr - MNT_FB_BASE;
  1477. } else if (zaddr < MNT_REG_BASE + 0x8000) {
  1478. // 0x2000-0x7fff: FIXME: waste of address space
  1479. // read from ethernet RX frame
  1480. // disable INT6 interrupt
  1481. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG2, (1 << 30) | 0);
  1482. ptr = (u8*) (ethernet_current_receive_ptr() + zaddr - (MNT_REG_BASE + 0x2000));
  1483. } else if (zaddr < MNT_REG_BASE + 0xa000) {
  1484. // 0x8000-0x9fff: read from TX frame (unusual)
  1485. ptr = (u8*) (TX_FRAME_ADDRESS + zaddr - (MNT_REG_BASE + 0x8000));
  1486. //printf("ETXF read: %08lx\n", (u32) ptr);
  1487. } else if (zaddr < MNT_REG_BASE + 0x10000) {
  1488. // 0xa000-0xafff: read from block device (usb storage)
  1489. // TODO: this should be moved to DMA space?
  1490. ptr = (u8*) (USB_BLOCK_STORAGE_ADDRESS + zaddr - (MNT_REG_BASE + 0xa000) + usb_selected_buffer_block * 512);
  1491. }
  1492. if (z3) {
  1493. u32 b1 = ptr[0] << 24;
  1494. u32 b2 = ptr[1] << 16;
  1495. u32 b3 = ptr[2] << 8;
  1496. u32 b4 = ptr[3];
  1497. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG1,
  1498. b1 | b2 | b3 | b4);
  1499. } else {
  1500. u16 ubyte = ptr[0] << 8;
  1501. u16 lbyte = ptr[1];
  1502. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG1,
  1503. ubyte | lbyte);
  1504. }
  1505. } else if (zaddr >= MNT_REG_BASE) {
  1506. // read ARM "register"
  1507. uint32_t data = 0;
  1508. uint32_t zaddr32 = zaddr & 0xffffffc;
  1509. if (zaddr32 == MNT_BASE_EVENT_SERIAL) {
  1510. data = (arm_app_output_event_serial << 16)
  1511. | arm_app_output_event_code;
  1512. arm_app_output_event_ack = 1;
  1513. } else if (zaddr32 == MNT_BASE_ETH_MAC_HI) {
  1514. uint8_t* mac = ethernet_get_mac_address_ptr();
  1515. data = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3];
  1516. } else if (zaddr32 == MNT_BASE_ETH_MAC_LO) {
  1517. uint8_t* mac = ethernet_get_mac_address_ptr();
  1518. data = mac[4] << 24 | mac[5] << 16;
  1519. } else if (zaddr32 == MNT_BASE_ETH_TX) {
  1520. // FIXME this is probably wrong (doesn't need swapping?)
  1521. data = (ethernet_send_result & 0xff) << 24
  1522. | (ethernet_send_result & 0xff00) << 16;
  1523. } else if (zaddr32 == MNT_BASE_FW_VERSION) {
  1524. data = (REVISION_MAJOR << 24 | REVISION_MINOR << 16);
  1525. } else if (zaddr32 == MNT_BASE_USB_STATUS) {
  1526. data = usb_status << 16;
  1527. } else if (zaddr32 == MNT_BASE_USB_CAPACITY) {
  1528. if (usb_storage_available) {
  1529. printf("[USB] query capacity: %lx\n",zz_usb_storage_capacity(0));
  1530. data = zz_usb_storage_capacity(0);
  1531. } else {
  1532. printf("[USB] query capacity: no device.\n");
  1533. data = 0;
  1534. }
  1535. }
  1536. if (z3) {
  1537. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG1, data);
  1538. } else {
  1539. if (zaddr & 2) {
  1540. // lower 16 bit
  1541. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG1, data);
  1542. } else {
  1543. // upper 16 bit
  1544. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG1, data >> 16);
  1545. }
  1546. }
  1547. }
  1548. // ack the read, set bit 30 in register 0
  1549. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG0, (1 << 30));
  1550. need_req_ack = 2;
  1551. } else {
  1552. // there are no read/write requests, we can do other housekeeping
  1553. // we flush the cache at regular intervals to avoid too much visible cache activity on the screen
  1554. // FIXME make this adjustable for user
  1555. if (cache_counter > 25000) {
  1556. Xil_DCacheFlush();
  1557. cache_counter = 0;
  1558. }
  1559. cache_counter++;
  1560. int videocap_enabled = (zstate_raw & (1 << 23));
  1561. int videocap_ntsc = (zstate_raw & (1<<22));
  1562. // FIXME magic constant
  1563. if (videocap_enabled && framebuffer_pan_offset >= 0xe00000) {
  1564. if (sprite_enabled) {
  1565. sprite_hide();
  1566. }
  1567. if (!videocap_enabled_old) {
  1568. videocap_area_clear();
  1569. if (!videocap_ntsc) {
  1570. // remember current video mode as desired video capture video mode for PAL
  1571. videocap_video_mode = video_mode & 0xff;
  1572. }
  1573. videocap_ntsc_old = 0;
  1574. }
  1575. if (videocap_ntsc != videocap_ntsc_old) {
  1576. // change between ntsc+pal
  1577. videocap_area_clear();
  1578. if (videocap_ntsc) {
  1579. framebuffer_pan_offset = 0x00e00000;
  1580. video_mode_init(ZZVMODE_720x480, 2, MNTVA_COLOR_32BIT);
  1581. } else {
  1582. // PAL
  1583. reset_default_videocap_pan();
  1584. framebuffer_pan_offset = default_pan_offset;
  1585. video_mode_init(videocap_video_mode, 2, MNTVA_COLOR_32BIT);
  1586. }
  1587. }
  1588. videocap_ntsc_old = videocap_ntsc;
  1589. int interlace = !!(zstate_raw & (1 << 24));
  1590. if (interlace != interlace_old) {
  1591. // interlace has changed, we need to reconfigure vdma for the new screen height
  1592. int vdiv = 2;
  1593. if (interlace) {
  1594. vdiv = 1;
  1595. }
  1596. videocap_area_clear();
  1597. init_vdma(vmode_hsize, vmode_vsize, 1, vdiv);
  1598. video_formatter_valign();
  1599. printf("videocap interlace mode changed.\n");
  1600. }
  1601. interlace_old = interlace;
  1602. }
  1603. else {
  1604. if(!sprite_enabled)
  1605. sprite_enabled = 1;
  1606. }
  1607. if (videocap_enabled_old != videocap_enabled) {
  1608. if (framebuffer_pan_offset >= 0xe00000) {
  1609. videocap_area_clear();
  1610. }
  1611. videocap_enabled_old = videocap_enabled;
  1612. }
  1613. if (zstate == 0) {
  1614. // RESET
  1615. handle_amiga_reset();
  1616. }
  1617. }
  1618. // re-init VDMA if requested
  1619. if (request_video_align) {
  1620. vblank = (zstate_raw & (1<<21));
  1621. if (vblank) {
  1622. request_video_align = 0;
  1623. init_vdma(vmode_hsize, vmode_vsize, vmode_hdiv, vmode_vdiv);
  1624. }
  1625. }
  1626. // TODO: potential hang, timeout?
  1627. if (need_req_ack) {
  1628. while (1) {
  1629. // 1. fpga needs to respond to flag bit 31 or 30 going high (signals request fulfilled)
  1630. // 2. it does that by clearing the request bit
  1631. // 3. we read register 3 until request bit (31:write, 30:read) goes to 0 again
  1632. //
  1633. u32 zstate = mntzorro_read(MNTZ_BASE_ADDR, MNTZORRO_REG3);
  1634. u32 writereq = (zstate & (1 << 31));
  1635. u32 readreq = (zstate & (1 << 30));
  1636. if (need_req_ack == 1 && !writereq)
  1637. break;
  1638. if (need_req_ack == 2 && !readreq)
  1639. break;
  1640. if ((zstate & 0xff) == 0)
  1641. break; // reset
  1642. }
  1643. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG0, 0);
  1644. need_req_ack = 0;
  1645. }
  1646. // check for queued up ethernet frames
  1647. int ethernet_backlog = ethernet_get_backlog();
  1648. if (ethernet_backlog > 0 && backlog_nag_counter > 5000) {
  1649. // interrupt amiga (trigger int6/2)
  1650. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG2, (1 << 30) | 1);
  1651. usleep(1);
  1652. mntzorro_write(MNTZ_BASE_ADDR, MNTZORRO_REG2, (1 << 30) | 0);
  1653. backlog_nag_counter = 0;
  1654. }
  1655. if (interrupt_enabled && ethernet_backlog > 0) {
  1656. backlog_nag_counter++;
  1657. }
  1658. }
  1659. cleanup_platform();
  1660. return 0;
  1661. }
  1662. void arm_exception_handler(void *callback) {
  1663. printf("arm_exception_handler()!\n");
  1664. while (1) {
  1665. }
  1666. }
  1667. void arm_exception_handler_illinst(void *callback) {
  1668. printf("arm_exception_handler_illinst()!\n");
  1669. while (1) {
  1670. }
  1671. }