Firmware for MNT ZZ9000 graphics and ARM coprocessor card for Amiga computers.
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zz9000_ps.tcl 51KB

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  1. ################################################################
  2. # This is a generated script based on design: zz9000_ps
  3. #
  4. # Though there are limitations about the generated script,
  5. # the main purpose of this utility is to make learning
  6. # IP Integrator Tcl commands easier.
  7. ################################################################
  8. namespace eval _tcl {
  9. proc get_script_folder {} {
  10. set script_path [file normalize [info script]]
  11. set script_folder [file dirname $script_path]
  12. return $script_folder
  13. }
  14. }
  15. variable script_folder
  16. set script_folder [_tcl::get_script_folder]
  17. ################################################################
  18. # Check if script is running in correct Vivado version.
  19. ################################################################
  20. set scripts_vivado_version 2018.3
  21. set current_vivado_version [version -short]
  22. if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
  23. puts ""
  24. catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
  25. return 1
  26. }
  27. ################################################################
  28. # START
  29. ################################################################
  30. # To test this script, run the following commands from Vivado Tcl console:
  31. # source zz9000_ps_script.tcl
  32. # The design that will be created by this Tcl script contains the following
  33. # module references:
  34. # MNTZorro_v0_1_S00_AXI, video_formatter
  35. # Please add the sources of those modules before sourcing this Tcl script.
  36. # If there is no project opened, this script will create a
  37. # project, but make sure you do not have an existing project
  38. # <./myproj/project_1.xpr> in the current working folder.
  39. set list_projs [get_projects -quiet]
  40. if { $list_projs eq "" } {
  41. create_project project_1 myproj -part xc7z020clg400-1
  42. }
  43. # CHANGE DESIGN NAME HERE
  44. variable design_name
  45. set design_name zz9000_ps
  46. # If you do not already have an existing IP Integrator design open,
  47. # you can create a design using the following command:
  48. # create_bd_design $design_name
  49. # Creating design if needed
  50. set errMsg ""
  51. set nRet 0
  52. set cur_design [current_bd_design -quiet]
  53. set list_cells [get_bd_cells -quiet]
  54. if { ${design_name} eq "" } {
  55. # USE CASES:
  56. # 1) Design_name not set
  57. set errMsg "Please set the variable <design_name> to a non-empty value."
  58. set nRet 1
  59. } elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
  60. # USE CASES:
  61. # 2): Current design opened AND is empty AND names same.
  62. # 3): Current design opened AND is empty AND names diff; design_name NOT in project.
  63. # 4): Current design opened AND is empty AND names diff; design_name exists in project.
  64. if { $cur_design ne $design_name } {
  65. common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
  66. set design_name [get_property NAME $cur_design]
  67. }
  68. common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
  69. } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
  70. # USE CASES:
  71. # 5) Current design opened AND has components AND same names.
  72. set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
  73. set nRet 1
  74. } elseif { [get_files -quiet ${design_name}.bd] ne "" } {
  75. # USE CASES:
  76. # 6) Current opened design, has components, but diff names, design_name exists in project.
  77. # 7) No opened design, design_name exists in project.
  78. set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
  79. set nRet 2
  80. } else {
  81. # USE CASES:
  82. # 8) No opened design, design_name not in project.
  83. # 9) Current opened design, has components, but diff names, design_name not in project.
  84. common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
  85. create_bd_design $design_name
  86. common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
  87. current_bd_design $design_name
  88. }
  89. common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
  90. if { $nRet != 0 } {
  91. catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
  92. return $nRet
  93. }
  94. set bCheckIPsPassed 1
  95. ##################################################################
  96. # CHECK IPs
  97. ##################################################################
  98. set bCheckIPs 1
  99. if { $bCheckIPs == 1 } {
  100. set list_check_ips "\
  101. xilinx.com:ip:axi_protocol_converter:2.1\
  102. xilinx.com:ip:axi_register_slice:2.1\
  103. xilinx.com:ip:clk_wiz:6.0\
  104. xilinx.com:ip:proc_sys_reset:5.0\
  105. xilinx.com:ip:processing_system7:5.5\
  106. xilinx.com:ip:xlslice:1.0\
  107. xilinx.com:ip:axi_vdma:6.3\
  108. xilinx.com:ip:axis_data_fifo:2.0\
  109. "
  110. set list_ips_missing ""
  111. common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
  112. foreach ip_vlnv $list_check_ips {
  113. set ip_obj [get_ipdefs -all $ip_vlnv]
  114. if { $ip_obj eq "" } {
  115. lappend list_ips_missing $ip_vlnv
  116. }
  117. }
  118. if { $list_ips_missing ne "" } {
  119. catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
  120. set bCheckIPsPassed 0
  121. }
  122. }
  123. ##################################################################
  124. # CHECK Modules
  125. ##################################################################
  126. set bCheckModules 1
  127. if { $bCheckModules == 1 } {
  128. set list_check_mods "\
  129. MNTZorro_v0_1_S00_AXI\
  130. video_formatter\
  131. "
  132. set list_mods_missing ""
  133. common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
  134. foreach mod_vlnv $list_check_mods {
  135. if { [can_resolve_reference $mod_vlnv] == 0 } {
  136. lappend list_mods_missing $mod_vlnv
  137. }
  138. }
  139. if { $list_mods_missing ne "" } {
  140. catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
  141. common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above."
  142. set bCheckIPsPassed 0
  143. }
  144. }
  145. if { $bCheckIPsPassed != 1 } {
  146. common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
  147. return 3
  148. }
  149. ##################################################################
  150. # DESIGN PROCs
  151. ##################################################################
  152. # Hierarchical cell: video
  153. proc create_hier_cell_video { parentCell nameHier } {
  154. variable script_folder
  155. if { $parentCell eq "" || $nameHier eq "" } {
  156. catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_video() - Empty argument(s)!"}
  157. return
  158. }
  159. # Get object for parentCell
  160. set parentObj [get_bd_cells $parentCell]
  161. if { $parentObj == "" } {
  162. catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
  163. return
  164. }
  165. # Make sure parentObj is hier blk
  166. set parentType [get_property TYPE $parentObj]
  167. if { $parentType ne "hier" } {
  168. catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
  169. return
  170. }
  171. # Save current instance; Restore later
  172. set oldCurInst [current_bd_instance .]
  173. # Set parent object as current
  174. current_bd_instance $parentObj
  175. # Create cell and set as current instance
  176. set hier_obj [create_bd_cell -type hier $nameHier]
  177. current_bd_instance $hier_obj
  178. # Create interface pins
  179. create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_MM2S
  180. create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_LITE
  181. # Create pins
  182. create_bd_pin -dir O VGA_DE
  183. create_bd_pin -dir O VGA_HS
  184. create_bd_pin -dir I -type clk VGA_PCLK
  185. create_bd_pin -dir O VGA_VS
  186. create_bd_pin -dir I -type rst aresetn
  187. create_bd_pin -dir I -type rst axi_resetn
  188. create_bd_pin -dir I -from 31 -to 0 control_data
  189. create_bd_pin -dir I control_interlace
  190. create_bd_pin -dir I -from 7 -to 0 control_op
  191. create_bd_pin -dir O -from 31 -to 0 dvi_rgb
  192. create_bd_pin -dir I -type clk m_axi_mm2s_aclk
  193. create_bd_pin -dir I -type clk s_axi_lite_aclk
  194. # Create instance: axi_vdma_0, and set properties
  195. set axi_vdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.3 axi_vdma_0 ]
  196. set_property -dict [ list \
  197. CONFIG.c_include_mm2s_dre {0} \
  198. CONFIG.c_include_s2mm {0} \
  199. CONFIG.c_m_axi_mm2s_data_width {32} \
  200. CONFIG.c_mm2s_genlock_mode {0} \
  201. CONFIG.c_mm2s_linebuffer_depth {2048} \
  202. CONFIG.c_mm2s_max_burst_length {128} \
  203. CONFIG.c_num_fstores {1} \
  204. CONFIG.c_s2mm_genlock_mode {0} \
  205. ] $axi_vdma_0
  206. # Create instance: axis_data_fifo_0, and set properties
  207. set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
  208. set_property -dict [ list \
  209. CONFIG.FIFO_DEPTH {32} \
  210. ] $axis_data_fifo_0
  211. # Create instance: video_formatter_0, and set properties
  212. set block_name video_formatter
  213. set block_cell_name video_formatter_0
  214. if { [catch {set video_formatter_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
  215. catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
  216. return 1
  217. } elseif { $video_formatter_0 eq "" } {
  218. catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
  219. return 1
  220. }
  221. # Create interface connections
  222. connect_bd_intf_net -intf_net axi_vdma_0_M_AXIS_MM2S [get_bd_intf_pins axi_vdma_0/M_AXIS_MM2S] [get_bd_intf_pins axis_data_fifo_0/S_AXIS]
  223. connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axis_data_fifo_0/M_AXIS] [get_bd_intf_pins video_formatter_0/m_axis_vid]
  224. connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins S_AXI_LITE] [get_bd_intf_pins axi_vdma_0/S_AXI_LITE]
  225. connect_bd_intf_net -intf_net video_subsystem_M_AXI_MM2S [get_bd_intf_pins M_AXI_MM2S] [get_bd_intf_pins axi_vdma_0/M_AXI_MM2S]
  226. # Create port connections
  227. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_data [get_bd_pins control_data] [get_bd_pins video_formatter_0/control_data]
  228. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_interlace [get_bd_pins control_interlace] [get_bd_pins video_formatter_0/control_interlace]
  229. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_op [get_bd_pins control_op] [get_bd_pins video_formatter_0/control_op]
  230. connect_bd_net -net clk_1 [get_bd_pins VGA_PCLK] [get_bd_pins video_formatter_0/dvi_clk]
  231. connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins video_formatter_0/aresetn]
  232. connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins m_axi_mm2s_aclk] [get_bd_pins axi_vdma_0/m_axi_mm2s_aclk] [get_bd_pins axi_vdma_0/m_axis_mm2s_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins video_formatter_0/m_axis_vid_aclk]
  233. connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_pins s_axi_lite_aclk] [get_bd_pins axi_vdma_0/s_axi_lite_aclk]
  234. connect_bd_net -net rst_ps7_0_25M_peripheral_aresetn [get_bd_pins axi_resetn] [get_bd_pins axi_vdma_0/axi_resetn]
  235. connect_bd_net -net v_axi4s_vid_out_0_vid_data [get_bd_pins dvi_rgb] [get_bd_pins video_formatter_0/dvi_rgb]
  236. connect_bd_net -net video_subsystem_VGA_DE [get_bd_pins VGA_DE] [get_bd_pins video_formatter_0/dvi_active_video]
  237. connect_bd_net -net video_subsystem_VGA_HS [get_bd_pins VGA_HS] [get_bd_pins video_formatter_0/dvi_hsync]
  238. connect_bd_net -net video_subsystem_VGA_VS [get_bd_pins VGA_VS] [get_bd_pins video_formatter_0/dvi_vsync]
  239. # Restore current instance
  240. current_bd_instance $oldCurInst
  241. }
  242. # Procedure to create entire design; Provide argument to make
  243. # procedure reusable. If parentCell is "", will use root.
  244. proc create_root_design { parentCell } {
  245. variable script_folder
  246. variable design_name
  247. if { $parentCell eq "" } {
  248. set parentCell [get_bd_cells /]
  249. }
  250. # Get object for parentCell
  251. set parentObj [get_bd_cells $parentCell]
  252. if { $parentObj == "" } {
  253. catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
  254. return
  255. }
  256. # Make sure parentObj is hier blk
  257. set parentType [get_property TYPE $parentObj]
  258. if { $parentType ne "hier" } {
  259. catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
  260. return
  261. }
  262. # Save current instance; Restore later
  263. set oldCurInst [current_bd_instance .]
  264. # Set parent object as current
  265. current_bd_instance $parentObj
  266. # Create interface ports
  267. set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
  268. set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
  269. # Create ports
  270. set VCAP_B0 [ create_bd_port -dir I VCAP_B0 ]
  271. set VCAP_B1 [ create_bd_port -dir I VCAP_B1 ]
  272. set VCAP_B2 [ create_bd_port -dir I VCAP_B2 ]
  273. set VCAP_B3 [ create_bd_port -dir I VCAP_B3 ]
  274. set VCAP_B4 [ create_bd_port -dir I VCAP_B4 ]
  275. set VCAP_B5 [ create_bd_port -dir I VCAP_B5 ]
  276. set VCAP_B6 [ create_bd_port -dir I VCAP_B6 ]
  277. set VCAP_B7 [ create_bd_port -dir I VCAP_B7 ]
  278. set VCAP_G0 [ create_bd_port -dir I VCAP_G0 ]
  279. set VCAP_G1 [ create_bd_port -dir I VCAP_G1 ]
  280. set VCAP_G2 [ create_bd_port -dir I VCAP_G2 ]
  281. set VCAP_G3 [ create_bd_port -dir I VCAP_G3 ]
  282. set VCAP_G4 [ create_bd_port -dir I VCAP_G4 ]
  283. set VCAP_G5 [ create_bd_port -dir I VCAP_G5 ]
  284. set VCAP_G6 [ create_bd_port -dir I VCAP_G6 ]
  285. set VCAP_G7 [ create_bd_port -dir I VCAP_G7 ]
  286. set VCAP_HSYNC [ create_bd_port -dir I VCAP_HSYNC ]
  287. set VCAP_R0 [ create_bd_port -dir I VCAP_R0 ]
  288. set VCAP_R1 [ create_bd_port -dir I VCAP_R1 ]
  289. set VCAP_R2 [ create_bd_port -dir I VCAP_R2 ]
  290. set VCAP_R3 [ create_bd_port -dir I VCAP_R3 ]
  291. set VCAP_R4 [ create_bd_port -dir I VCAP_R4 ]
  292. set VCAP_R5 [ create_bd_port -dir I VCAP_R5 ]
  293. set VCAP_R6 [ create_bd_port -dir I VCAP_R6 ]
  294. set VCAP_R7 [ create_bd_port -dir I VCAP_R7 ]
  295. set VCAP_VSYNC [ create_bd_port -dir I VCAP_VSYNC ]
  296. set VGA_B [ create_bd_port -dir O -from 7 -to 0 VGA_B ]
  297. set VGA_DE [ create_bd_port -dir O VGA_DE ]
  298. set VGA_G [ create_bd_port -dir O -from 7 -to 0 VGA_G ]
  299. set VGA_HS [ create_bd_port -dir O VGA_HS ]
  300. set VGA_PCLK [ create_bd_port -dir O -type clk VGA_PCLK ]
  301. set VGA_R [ create_bd_port -dir O -from 7 -to 0 VGA_R ]
  302. set VGA_VS [ create_bd_port -dir O VGA_VS ]
  303. set ZORRO_ADDR [ create_bd_port -dir IO -from 22 -to 0 ZORRO_ADDR ]
  304. set ZORRO_ADDRDIR [ create_bd_port -dir O ZORRO_ADDRDIR ]
  305. set ZORRO_ADDRDIR2 [ create_bd_port -dir O ZORRO_ADDRDIR2 ]
  306. set ZORRO_C28D [ create_bd_port -dir I ZORRO_C28D ]
  307. set ZORRO_DATA [ create_bd_port -dir IO -from 15 -to 0 ZORRO_DATA ]
  308. set ZORRO_DATADIR [ create_bd_port -dir O ZORRO_DATADIR ]
  309. set ZORRO_DOE [ create_bd_port -dir I ZORRO_DOE ]
  310. set ZORRO_E7M [ create_bd_port -dir I ZORRO_E7M ]
  311. set ZORRO_INT6 [ create_bd_port -dir O ZORRO_INT6 ]
  312. set ZORRO_NBGN [ create_bd_port -dir I ZORRO_NBGN ]
  313. set ZORRO_NBRN [ create_bd_port -dir O ZORRO_NBRN ]
  314. set ZORRO_NCCS [ create_bd_port -dir I ZORRO_NCCS ]
  315. set ZORRO_NCFGIN [ create_bd_port -dir I ZORRO_NCFGIN ]
  316. set ZORRO_NCFGOUT [ create_bd_port -dir O ZORRO_NCFGOUT ]
  317. set ZORRO_NCINH [ create_bd_port -dir O ZORRO_NCINH ]
  318. set ZORRO_NDS0 [ create_bd_port -dir I ZORRO_NDS0 ]
  319. set ZORRO_NDS1 [ create_bd_port -dir I ZORRO_NDS1 ]
  320. set ZORRO_NDTACK [ create_bd_port -dir O ZORRO_NDTACK ]
  321. set ZORRO_NFCS [ create_bd_port -dir I ZORRO_NFCS ]
  322. set ZORRO_NIORST [ create_bd_port -dir I ZORRO_NIORST ]
  323. set ZORRO_NLDS [ create_bd_port -dir I ZORRO_NLDS ]
  324. set ZORRO_NSLAVE [ create_bd_port -dir O ZORRO_NSLAVE ]
  325. set ZORRO_NUDS [ create_bd_port -dir I ZORRO_NUDS ]
  326. set ZORRO_READ [ create_bd_port -dir I ZORRO_READ ]
  327. # Create instance: MNTZorro_v0_1_S00_AXI_0, and set properties
  328. set block_name MNTZorro_v0_1_S00_AXI
  329. set block_cell_name MNTZorro_v0_1_S00_AXI_0
  330. if { [catch {set MNTZorro_v0_1_S00_AXI_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
  331. catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
  332. return 1
  333. } elseif { $MNTZorro_v0_1_S00_AXI_0 eq "" } {
  334. catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
  335. return 1
  336. }
  337. # Create instance: axi_protocol_convert_0, and set properties
  338. set axi_protocol_convert_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_converter:2.1 axi_protocol_convert_0 ]
  339. # Create instance: axi_protocol_convert_1, and set properties
  340. set axi_protocol_convert_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_converter:2.1 axi_protocol_convert_1 ]
  341. set_property -dict [ list \
  342. CONFIG.TRANSLATION_MODE {2} \
  343. ] $axi_protocol_convert_1
  344. # Create instance: axi_protocol_convert_2, and set properties
  345. set axi_protocol_convert_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_converter:2.1 axi_protocol_convert_2 ]
  346. # Create instance: axi_register_slice_0, and set properties
  347. set axi_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 ]
  348. # Create instance: axi_register_slice_1, and set properties
  349. set axi_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_1 ]
  350. # Create instance: axi_register_slice_2, and set properties
  351. set axi_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_2 ]
  352. # Create instance: axi_register_slice_3, and set properties
  353. set axi_register_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_3 ]
  354. # Create instance: clk_wiz_0, and set properties
  355. set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
  356. set_property -dict [ list \
  357. CONFIG.CLKOUT1_DRIVES {BUFG} \
  358. CONFIG.CLKOUT1_JITTER {272.433} \
  359. CONFIG.CLKOUT1_PHASE_ERROR {261.747} \
  360. CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {75} \
  361. CONFIG.CLKOUT2_DRIVES {BUFG} \
  362. CONFIG.CLKOUT3_DRIVES {BUFG} \
  363. CONFIG.CLKOUT4_DRIVES {BUFG} \
  364. CONFIG.CLKOUT5_DRIVES {BUFG} \
  365. CONFIG.CLKOUT6_DRIVES {BUFG} \
  366. CONFIG.CLKOUT7_DRIVES {BUFG} \
  367. CONFIG.MMCM_CLKFBOUT_MULT_F {33} \
  368. CONFIG.MMCM_CLKOUT0_DIVIDE_F {11} \
  369. CONFIG.MMCM_COMPENSATION {ZHOLD} \
  370. CONFIG.MMCM_DIVCLK_DIVIDE {4} \
  371. CONFIG.PRIMITIVE {PLL} \
  372. CONFIG.PRIM_SOURCE {Single_ended_clock_capable_pin} \
  373. CONFIG.SECONDARY_SOURCE {Single_ended_clock_capable_pin} \
  374. CONFIG.USE_DYN_RECONFIG {true} \
  375. CONFIG.USE_PHASE_ALIGNMENT {false} \
  376. ] $clk_wiz_0
  377. # Create instance: proc_sys_reset_0, and set properties
  378. set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
  379. # Create instance: processing_system7_0, and set properties
  380. set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
  381. set_property -dict [ list \
  382. CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
  383. CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
  384. CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
  385. CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
  386. CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
  387. CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
  388. CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {25.000000} \
  389. CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
  390. CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
  391. CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
  392. CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {10.000000} \
  393. CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {25.000000} \
  394. CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
  395. CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
  396. CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
  397. CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
  398. CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
  399. CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
  400. CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
  401. CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
  402. CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
  403. CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
  404. CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
  405. CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
  406. CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {666.666} \
  407. CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
  408. CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
  409. CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
  410. CONFIG.PCW_CLK0_FREQ {100000000} \
  411. CONFIG.PCW_CLK1_FREQ {25000000} \
  412. CONFIG.PCW_CLK2_FREQ {10000000} \
  413. CONFIG.PCW_CLK3_FREQ {10000000} \
  414. CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
  415. CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
  416. CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
  417. CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
  418. CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
  419. CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
  420. CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
  421. CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
  422. CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
  423. CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \
  424. CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
  425. CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
  426. CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
  427. CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
  428. CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
  429. CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
  430. CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
  431. CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
  432. CONFIG.PCW_ENET0_RESET_ENABLE {0} \
  433. CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \
  434. CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
  435. CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
  436. CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
  437. CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
  438. CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
  439. CONFIG.PCW_ENET1_RESET_ENABLE {0} \
  440. CONFIG.PCW_ENET_RESET_ENABLE {0} \
  441. CONFIG.PCW_ENET_RESET_SELECT {<Select>} \
  442. CONFIG.PCW_EN_CLK0_PORT {1} \
  443. CONFIG.PCW_EN_CLK1_PORT {1} \
  444. CONFIG.PCW_EN_DDR {1} \
  445. CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \
  446. CONFIG.PCW_EN_EMIO_ENET0 {0} \
  447. CONFIG.PCW_EN_EMIO_ENET1 {0} \
  448. CONFIG.PCW_EN_EMIO_GPIO {0} \
  449. CONFIG.PCW_EN_EMIO_I2C0 {0} \
  450. CONFIG.PCW_EN_EMIO_TTC0 {0} \
  451. CONFIG.PCW_EN_EMIO_WDT {0} \
  452. CONFIG.PCW_EN_ENET0 {1} \
  453. CONFIG.PCW_EN_ENET1 {0} \
  454. CONFIG.PCW_EN_GPIO {1} \
  455. CONFIG.PCW_EN_I2C0 {1} \
  456. CONFIG.PCW_EN_RST0_PORT {1} \
  457. CONFIG.PCW_EN_RST1_PORT {0} \
  458. CONFIG.PCW_EN_SDIO0 {1} \
  459. CONFIG.PCW_EN_TTC0 {0} \
  460. CONFIG.PCW_EN_UART1 {1} \
  461. CONFIG.PCW_EN_WDT {0} \
  462. CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \
  463. CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
  464. CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \
  465. CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {8} \
  466. CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {5} \
  467. CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
  468. CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
  469. CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
  470. CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
  471. CONFIG.PCW_FCLK_CLK0_BUF {FALSE} \
  472. CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \
  473. CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
  474. CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {25} \
  475. CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
  476. CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \
  477. CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
  478. CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
  479. CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \
  480. CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \
  481. CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
  482. CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
  483. CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \
  484. CONFIG.PCW_I2C0_GRP_INT_IO {<Select>} \
  485. CONFIG.PCW_I2C0_I2C0_IO {MIO 50 .. 51} \
  486. CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
  487. CONFIG.PCW_I2C0_RESET_ENABLE {0} \
  488. CONFIG.PCW_I2C0_RESET_IO {<Select>} \
  489. CONFIG.PCW_I2C1_RESET_ENABLE {0} \
  490. CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {111.111115} \
  491. CONFIG.PCW_I2C_RESET_ENABLE {0} \
  492. CONFIG.PCW_I2C_RESET_SELECT {<Select>} \
  493. CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
  494. CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
  495. CONFIG.PCW_MIO_0_DIRECTION {inout} \
  496. CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
  497. CONFIG.PCW_MIO_0_PULLUP {enabled} \
  498. CONFIG.PCW_MIO_0_SLEW {slow} \
  499. CONFIG.PCW_MIO_10_DIRECTION {inout} \
  500. CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
  501. CONFIG.PCW_MIO_10_PULLUP {enabled} \
  502. CONFIG.PCW_MIO_10_SLEW {slow} \
  503. CONFIG.PCW_MIO_11_DIRECTION {inout} \
  504. CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
  505. CONFIG.PCW_MIO_11_PULLUP {enabled} \
  506. CONFIG.PCW_MIO_11_SLEW {slow} \
  507. CONFIG.PCW_MIO_12_DIRECTION {inout} \
  508. CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
  509. CONFIG.PCW_MIO_12_PULLUP {enabled} \
  510. CONFIG.PCW_MIO_12_SLEW {slow} \
  511. CONFIG.PCW_MIO_13_DIRECTION {inout} \
  512. CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
  513. CONFIG.PCW_MIO_13_PULLUP {enabled} \
  514. CONFIG.PCW_MIO_13_SLEW {slow} \
  515. CONFIG.PCW_MIO_14_DIRECTION {inout} \
  516. CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
  517. CONFIG.PCW_MIO_14_PULLUP {enabled} \
  518. CONFIG.PCW_MIO_14_SLEW {slow} \
  519. CONFIG.PCW_MIO_15_DIRECTION {inout} \
  520. CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
  521. CONFIG.PCW_MIO_15_PULLUP {enabled} \
  522. CONFIG.PCW_MIO_15_SLEW {slow} \
  523. CONFIG.PCW_MIO_16_DIRECTION {out} \
  524. CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
  525. CONFIG.PCW_MIO_16_PULLUP {enabled} \
  526. CONFIG.PCW_MIO_16_SLEW {slow} \
  527. CONFIG.PCW_MIO_17_DIRECTION {out} \
  528. CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
  529. CONFIG.PCW_MIO_17_PULLUP {enabled} \
  530. CONFIG.PCW_MIO_17_SLEW {slow} \
  531. CONFIG.PCW_MIO_18_DIRECTION {out} \
  532. CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
  533. CONFIG.PCW_MIO_18_PULLUP {enabled} \
  534. CONFIG.PCW_MIO_18_SLEW {slow} \
  535. CONFIG.PCW_MIO_19_DIRECTION {out} \
  536. CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
  537. CONFIG.PCW_MIO_19_PULLUP {enabled} \
  538. CONFIG.PCW_MIO_19_SLEW {slow} \
  539. CONFIG.PCW_MIO_1_DIRECTION {inout} \
  540. CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
  541. CONFIG.PCW_MIO_1_PULLUP {enabled} \
  542. CONFIG.PCW_MIO_1_SLEW {slow} \
  543. CONFIG.PCW_MIO_20_DIRECTION {out} \
  544. CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
  545. CONFIG.PCW_MIO_20_PULLUP {enabled} \
  546. CONFIG.PCW_MIO_20_SLEW {slow} \
  547. CONFIG.PCW_MIO_21_DIRECTION {out} \
  548. CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
  549. CONFIG.PCW_MIO_21_PULLUP {enabled} \
  550. CONFIG.PCW_MIO_21_SLEW {slow} \
  551. CONFIG.PCW_MIO_22_DIRECTION {in} \
  552. CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
  553. CONFIG.PCW_MIO_22_PULLUP {enabled} \
  554. CONFIG.PCW_MIO_22_SLEW {slow} \
  555. CONFIG.PCW_MIO_23_DIRECTION {in} \
  556. CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
  557. CONFIG.PCW_MIO_23_PULLUP {enabled} \
  558. CONFIG.PCW_MIO_23_SLEW {slow} \
  559. CONFIG.PCW_MIO_24_DIRECTION {in} \
  560. CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
  561. CONFIG.PCW_MIO_24_PULLUP {enabled} \
  562. CONFIG.PCW_MIO_24_SLEW {slow} \
  563. CONFIG.PCW_MIO_25_DIRECTION {in} \
  564. CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
  565. CONFIG.PCW_MIO_25_PULLUP {enabled} \
  566. CONFIG.PCW_MIO_25_SLEW {slow} \
  567. CONFIG.PCW_MIO_26_DIRECTION {in} \
  568. CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
  569. CONFIG.PCW_MIO_26_PULLUP {enabled} \
  570. CONFIG.PCW_MIO_26_SLEW {slow} \
  571. CONFIG.PCW_MIO_27_DIRECTION {in} \
  572. CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
  573. CONFIG.PCW_MIO_27_PULLUP {enabled} \
  574. CONFIG.PCW_MIO_27_SLEW {slow} \
  575. CONFIG.PCW_MIO_28_DIRECTION {inout} \
  576. CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
  577. CONFIG.PCW_MIO_28_PULLUP {enabled} \
  578. CONFIG.PCW_MIO_28_SLEW {slow} \
  579. CONFIG.PCW_MIO_29_DIRECTION {inout} \
  580. CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
  581. CONFIG.PCW_MIO_29_PULLUP {enabled} \
  582. CONFIG.PCW_MIO_29_SLEW {slow} \
  583. CONFIG.PCW_MIO_2_DIRECTION {inout} \
  584. CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
  585. CONFIG.PCW_MIO_2_PULLUP {disabled} \
  586. CONFIG.PCW_MIO_2_SLEW {slow} \
  587. CONFIG.PCW_MIO_30_DIRECTION {inout} \
  588. CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
  589. CONFIG.PCW_MIO_30_PULLUP {enabled} \
  590. CONFIG.PCW_MIO_30_SLEW {slow} \
  591. CONFIG.PCW_MIO_31_DIRECTION {inout} \
  592. CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
  593. CONFIG.PCW_MIO_31_PULLUP {enabled} \
  594. CONFIG.PCW_MIO_31_SLEW {slow} \
  595. CONFIG.PCW_MIO_32_DIRECTION {inout} \
  596. CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
  597. CONFIG.PCW_MIO_32_PULLUP {enabled} \
  598. CONFIG.PCW_MIO_32_SLEW {slow} \
  599. CONFIG.PCW_MIO_33_DIRECTION {inout} \
  600. CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
  601. CONFIG.PCW_MIO_33_PULLUP {enabled} \
  602. CONFIG.PCW_MIO_33_SLEW {slow} \
  603. CONFIG.PCW_MIO_34_DIRECTION {inout} \
  604. CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
  605. CONFIG.PCW_MIO_34_PULLUP {enabled} \
  606. CONFIG.PCW_MIO_34_SLEW {slow} \
  607. CONFIG.PCW_MIO_35_DIRECTION {inout} \
  608. CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
  609. CONFIG.PCW_MIO_35_PULLUP {enabled} \
  610. CONFIG.PCW_MIO_35_SLEW {slow} \
  611. CONFIG.PCW_MIO_36_DIRECTION {inout} \
  612. CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
  613. CONFIG.PCW_MIO_36_PULLUP {enabled} \
  614. CONFIG.PCW_MIO_36_SLEW {slow} \
  615. CONFIG.PCW_MIO_37_DIRECTION {inout} \
  616. CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
  617. CONFIG.PCW_MIO_37_PULLUP {enabled} \
  618. CONFIG.PCW_MIO_37_SLEW {slow} \
  619. CONFIG.PCW_MIO_38_DIRECTION {inout} \
  620. CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
  621. CONFIG.PCW_MIO_38_PULLUP {enabled} \
  622. CONFIG.PCW_MIO_38_SLEW {slow} \
  623. CONFIG.PCW_MIO_39_DIRECTION {inout} \
  624. CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
  625. CONFIG.PCW_MIO_39_PULLUP {enabled} \
  626. CONFIG.PCW_MIO_39_SLEW {slow} \
  627. CONFIG.PCW_MIO_3_DIRECTION {inout} \
  628. CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
  629. CONFIG.PCW_MIO_3_PULLUP {disabled} \
  630. CONFIG.PCW_MIO_3_SLEW {slow} \
  631. CONFIG.PCW_MIO_40_DIRECTION {inout} \
  632. CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
  633. CONFIG.PCW_MIO_40_PULLUP {enabled} \
  634. CONFIG.PCW_MIO_40_SLEW {slow} \
  635. CONFIG.PCW_MIO_41_DIRECTION {inout} \
  636. CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
  637. CONFIG.PCW_MIO_41_PULLUP {enabled} \
  638. CONFIG.PCW_MIO_41_SLEW {slow} \
  639. CONFIG.PCW_MIO_42_DIRECTION {inout} \
  640. CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
  641. CONFIG.PCW_MIO_42_PULLUP {enabled} \
  642. CONFIG.PCW_MIO_42_SLEW {slow} \
  643. CONFIG.PCW_MIO_43_DIRECTION {inout} \
  644. CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
  645. CONFIG.PCW_MIO_43_PULLUP {enabled} \
  646. CONFIG.PCW_MIO_43_SLEW {slow} \
  647. CONFIG.PCW_MIO_44_DIRECTION {inout} \
  648. CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
  649. CONFIG.PCW_MIO_44_PULLUP {enabled} \
  650. CONFIG.PCW_MIO_44_SLEW {slow} \
  651. CONFIG.PCW_MIO_45_DIRECTION {inout} \
  652. CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
  653. CONFIG.PCW_MIO_45_PULLUP {enabled} \
  654. CONFIG.PCW_MIO_45_SLEW {slow} \
  655. CONFIG.PCW_MIO_46_DIRECTION {inout} \
  656. CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
  657. CONFIG.PCW_MIO_46_PULLUP {enabled} \
  658. CONFIG.PCW_MIO_46_SLEW {slow} \
  659. CONFIG.PCW_MIO_47_DIRECTION {inout} \
  660. CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
  661. CONFIG.PCW_MIO_47_PULLUP {enabled} \
  662. CONFIG.PCW_MIO_47_SLEW {slow} \
  663. CONFIG.PCW_MIO_48_DIRECTION {out} \
  664. CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
  665. CONFIG.PCW_MIO_48_PULLUP {enabled} \
  666. CONFIG.PCW_MIO_48_SLEW {slow} \
  667. CONFIG.PCW_MIO_49_DIRECTION {in} \
  668. CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
  669. CONFIG.PCW_MIO_49_PULLUP {enabled} \
  670. CONFIG.PCW_MIO_49_SLEW {slow} \
  671. CONFIG.PCW_MIO_4_DIRECTION {inout} \
  672. CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
  673. CONFIG.PCW_MIO_4_PULLUP {disabled} \
  674. CONFIG.PCW_MIO_4_SLEW {slow} \
  675. CONFIG.PCW_MIO_50_DIRECTION {inout} \
  676. CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
  677. CONFIG.PCW_MIO_50_PULLUP {enabled} \
  678. CONFIG.PCW_MIO_50_SLEW {slow} \
  679. CONFIG.PCW_MIO_51_DIRECTION {inout} \
  680. CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
  681. CONFIG.PCW_MIO_51_PULLUP {enabled} \
  682. CONFIG.PCW_MIO_51_SLEW {slow} \
  683. CONFIG.PCW_MIO_52_DIRECTION {out} \
  684. CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
  685. CONFIG.PCW_MIO_52_PULLUP {enabled} \
  686. CONFIG.PCW_MIO_52_SLEW {slow} \
  687. CONFIG.PCW_MIO_53_DIRECTION {inout} \
  688. CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
  689. CONFIG.PCW_MIO_53_PULLUP {enabled} \
  690. CONFIG.PCW_MIO_53_SLEW {slow} \
  691. CONFIG.PCW_MIO_5_DIRECTION {inout} \
  692. CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
  693. CONFIG.PCW_MIO_5_PULLUP {disabled} \
  694. CONFIG.PCW_MIO_5_SLEW {slow} \
  695. CONFIG.PCW_MIO_6_DIRECTION {inout} \
  696. CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
  697. CONFIG.PCW_MIO_6_PULLUP {disabled} \
  698. CONFIG.PCW_MIO_6_SLEW {slow} \
  699. CONFIG.PCW_MIO_7_DIRECTION {out} \
  700. CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
  701. CONFIG.PCW_MIO_7_PULLUP {disabled} \
  702. CONFIG.PCW_MIO_7_SLEW {slow} \
  703. CONFIG.PCW_MIO_8_DIRECTION {out} \
  704. CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
  705. CONFIG.PCW_MIO_8_PULLUP {disabled} \
  706. CONFIG.PCW_MIO_8_SLEW {slow} \
  707. CONFIG.PCW_MIO_9_DIRECTION {inout} \
  708. CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
  709. CONFIG.PCW_MIO_9_PULLUP {enabled} \
  710. CONFIG.PCW_MIO_9_SLEW {slow} \
  711. CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO#GPIO#UART 1#UART 1#I2C 0#I2C 0#Enet 0#Enet 0} \
  712. CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#gpio[1]#gpio[2]#gpio[3]#gpio[4]#gpio[5]#gpio[6]#gpio[7]#gpio[8]#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#gpio[28]#gpio[29]#gpio[30]#gpio[31]#gpio[32]#gpio[33]#gpio[34]#gpio[35]#gpio[36]#gpio[37]#gpio[38]#gpio[39]#clk#cmd#data[0]#data[1]#data[2]#data[3]#gpio[46]#gpio[47]#tx#rx#scl#sda#mdc#mdio} \
  713. CONFIG.PCW_P2F_ENET0_INTR {1} \
  714. CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
  715. CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
  716. CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {1} \
  717. CONFIG.PCW_SD0_GRP_CD_ENABLE {0} \
  718. CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
  719. CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
  720. CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
  721. CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
  722. CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
  723. CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {40} \
  724. CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {25} \
  725. CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
  726. CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
  727. CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
  728. CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {32} \
  729. CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {32} \
  730. CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
  731. CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
  732. CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
  733. CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
  734. CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0} \
  735. CONFIG.PCW_TTC0_TTC0_IO {<Select>} \
  736. CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \
  737. CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
  738. CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
  739. CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
  740. CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
  741. CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
  742. CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
  743. CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
  744. CONFIG.PCW_UIPARAM_DDR_AL {0} \
  745. CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
  746. CONFIG.PCW_UIPARAM_DDR_BL {8} \
  747. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.271} \
  748. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.259} \
  749. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.219} \
  750. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.207} \
  751. CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} \
  752. CONFIG.PCW_UIPARAM_DDR_CL {7} \
  753. CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
  754. CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
  755. CONFIG.PCW_UIPARAM_DDR_CWL {6} \
  756. CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
  757. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.229} \
  758. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.250} \
  759. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.121} \
  760. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.146} \
  761. CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
  762. CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
  763. CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
  764. CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333} \
  765. CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
  766. CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \
  767. CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \
  768. CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
  769. CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
  770. CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
  771. CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
  772. CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
  773. CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
  774. CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
  775. CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \
  776. CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
  777. CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
  778. CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
  779. CONFIG.PCW_USB0_RESET_ENABLE {0} \
  780. CONFIG.PCW_USB1_RESET_ENABLE {0} \
  781. CONFIG.PCW_USB_RESET_ENABLE {0} \
  782. CONFIG.PCW_USE_AXI_NONSECURE {0} \
  783. CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \
  784. CONFIG.PCW_USE_M_AXI_GP0 {1} \
  785. CONFIG.PCW_USE_M_AXI_GP1 {1} \
  786. CONFIG.PCW_USE_S_AXI_GP0 {0} \
  787. CONFIG.PCW_USE_S_AXI_HP0 {1} \
  788. CONFIG.PCW_USE_S_AXI_HP1 {1} \
  789. CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \
  790. CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \
  791. CONFIG.PCW_WDT_WDT_IO {<Select>} \
  792. ] $processing_system7_0
  793. # Create instance: ps7_0_axi_periph, and set properties
  794. set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
  795. set_property -dict [ list \
  796. CONFIG.M00_HAS_DATA_FIFO {0} \
  797. CONFIG.M00_HAS_REGSLICE {3} \
  798. CONFIG.M01_HAS_DATA_FIFO {0} \
  799. CONFIG.M01_HAS_REGSLICE {3} \
  800. CONFIG.NUM_MI {2} \
  801. CONFIG.S00_HAS_DATA_FIFO {1} \
  802. CONFIG.S00_HAS_REGSLICE {4} \
  803. ] $ps7_0_axi_periph
  804. # Create instance: rst_ps7_0_25M, and set properties
  805. set rst_ps7_0_25M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_25M ]
  806. set_property -dict [ list \
  807. CONFIG.C_NUM_INTERCONNECT_ARESETN {1} \
  808. CONFIG.C_NUM_PERP_ARESETN {1} \
  809. ] $rst_ps7_0_25M
  810. # Create instance: video
  811. create_hier_cell_video [current_bd_instance .] video
  812. # Create instance: xlslice_0, and set properties
  813. set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ]
  814. set_property -dict [ list \
  815. CONFIG.DIN_FROM {23} \
  816. CONFIG.DIN_TO {16} \
  817. CONFIG.DIN_WIDTH {32} \
  818. CONFIG.DOUT_WIDTH {8} \
  819. ] $xlslice_0
  820. # Create instance: xlslice_1, and set properties
  821. set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ]
  822. set_property -dict [ list \
  823. CONFIG.DIN_FROM {15} \
  824. CONFIG.DIN_TO {8} \
  825. CONFIG.DIN_WIDTH {32} \
  826. CONFIG.DOUT_WIDTH {8} \
  827. ] $xlslice_1
  828. # Create instance: xlslice_2, and set properties
  829. set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ]
  830. set_property -dict [ list \
  831. CONFIG.DIN_FROM {7} \
  832. CONFIG.DIN_TO {0} \
  833. CONFIG.DIN_WIDTH {32} \
  834. CONFIG.DOUT_WIDTH {8} \
  835. ] $xlslice_2
  836. # Create interface connections
  837. connect_bd_intf_net -intf_net MNTZorro_v0_1_S00_AXI_0_m00_axi [get_bd_intf_pins MNTZorro_v0_1_S00_AXI_0/m00_axi] [get_bd_intf_pins axi_protocol_convert_2/S_AXI]
  838. connect_bd_intf_net -intf_net axi_protocol_convert_0_M_AXI [get_bd_intf_pins MNTZorro_v0_1_S00_AXI_0/S_AXI] [get_bd_intf_pins axi_protocol_convert_0/M_AXI]
  839. connect_bd_intf_net -intf_net axi_protocol_convert_1_M_AXI [get_bd_intf_pins axi_protocol_convert_1/M_AXI] [get_bd_intf_pins axi_register_slice_1/S_AXI]
  840. connect_bd_intf_net -intf_net axi_protocol_convert_2_M_AXI [get_bd_intf_pins axi_protocol_convert_2/M_AXI] [get_bd_intf_pins axi_register_slice_3/S_AXI]
  841. connect_bd_intf_net -intf_net axi_register_slice_0_M_AXI [get_bd_intf_pins axi_register_slice_0/M_AXI] [get_bd_intf_pins axi_register_slice_2/S_AXI]
  842. connect_bd_intf_net -intf_net axi_register_slice_1_M_AXI [get_bd_intf_pins axi_register_slice_1/M_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0]
  843. connect_bd_intf_net -intf_net axi_register_slice_2_M_AXI [get_bd_intf_pins axi_protocol_convert_1/S_AXI] [get_bd_intf_pins axi_register_slice_2/M_AXI]
  844. connect_bd_intf_net -intf_net axi_register_slice_3_M_AXI [get_bd_intf_pins axi_register_slice_3/M_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP1]
  845. connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
  846. connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
  847. connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins axi_protocol_convert_0/S_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
  848. connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP1 [get_bd_intf_pins processing_system7_0/M_AXI_GP1] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
  849. connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins clk_wiz_0/s_axi_lite] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI]
  850. connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] [get_bd_intf_pins video/S_AXI_LITE]
  851. connect_bd_intf_net -intf_net video_subsystem_M_AXI_MM2S [get_bd_intf_pins axi_register_slice_0/S_AXI] [get_bd_intf_pins video/M_AXI_MM2S]
  852. # Create port connections
  853. connect_bd_net -net M00_ARESETN_1 [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_25M/interconnect_aresetn]
  854. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_ADDRDIR [get_bd_ports ZORRO_ADDRDIR] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_ADDRDIR]
  855. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_ADDRDIR2 [get_bd_ports ZORRO_ADDRDIR2] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_ADDRDIR2]
  856. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_DATADIR [get_bd_ports ZORRO_DATADIR] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_DATADIR]
  857. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_INT6 [get_bd_ports ZORRO_INT6] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_INT6]
  858. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_NBRN [get_bd_ports ZORRO_NBRN] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NBRN]
  859. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_NCFGOUT [get_bd_ports ZORRO_NCFGOUT] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NCFGOUT]
  860. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_NCINH [get_bd_ports ZORRO_NCINH] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NCINH]
  861. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_NDTACK [get_bd_ports ZORRO_NDTACK] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NDTACK]
  862. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_NSLAVE [get_bd_ports ZORRO_NSLAVE] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NSLAVE]
  863. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_data [get_bd_pins MNTZorro_v0_1_S00_AXI_0/video_control_data] [get_bd_pins video/control_data]
  864. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_interlace [get_bd_pins MNTZorro_v0_1_S00_AXI_0/video_control_interlace] [get_bd_pins video/control_interlace]
  865. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_op [get_bd_pins MNTZorro_v0_1_S00_AXI_0/video_control_op] [get_bd_pins video/control_op]
  866. connect_bd_net -net Net [get_bd_ports ZORRO_ADDR] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_ADDR]
  867. connect_bd_net -net Net1 [get_bd_ports ZORRO_DATA] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_DATA]
  868. connect_bd_net -net VCAP_B0_0_1 [get_bd_ports VCAP_B0] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B0]
  869. connect_bd_net -net VCAP_B1_0_1 [get_bd_ports VCAP_B1] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B1]
  870. connect_bd_net -net VCAP_B2_0_1 [get_bd_ports VCAP_B2] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B2]
  871. connect_bd_net -net VCAP_B3_0_1 [get_bd_ports VCAP_B3] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B3]
  872. connect_bd_net -net VCAP_B4_0_1 [get_bd_ports VCAP_B4] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B4]
  873. connect_bd_net -net VCAP_B5_0_1 [get_bd_ports VCAP_B5] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B5]
  874. connect_bd_net -net VCAP_B6_0_1 [get_bd_ports VCAP_B6] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B6]
  875. connect_bd_net -net VCAP_B7_0_1 [get_bd_ports VCAP_B7] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B7]
  876. connect_bd_net -net VCAP_G0_0_1 [get_bd_ports VCAP_G0] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_G0]
  877. connect_bd_net -net VCAP_G1_0_1 [get_bd_ports VCAP_G1] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_G1]
  878. connect_bd_net -net VCAP_G2_0_1 [get_bd_ports VCAP_G2] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_G2]
  879. connect_bd_net -net VCAP_G3_0_1 [get_bd_ports VCAP_G3] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_G3]
  880. connect_bd_net -net VCAP_G4_0_1 [get_bd_ports VCAP_G4] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_G4]
  881. connect_bd_net -net VCAP_G5_0_1 [get_bd_ports VCAP_G5] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_G5]
  882. connect_bd_net -net VCAP_G6_0_1 [get_bd_ports VCAP_G6] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_G6]
  883. connect_bd_net -net VCAP_G7_0_1 [get_bd_ports VCAP_G7] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_G7]
  884. connect_bd_net -net VCAP_HSYNC_0_1 [get_bd_ports VCAP_HSYNC] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_HSYNC]
  885. connect_bd_net -net VCAP_R0_0_1 [get_bd_ports VCAP_R0] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_R0]
  886. connect_bd_net -net VCAP_R1_0_1 [get_bd_ports VCAP_R1] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_R1]
  887. connect_bd_net -net VCAP_R2_0_1 [get_bd_ports VCAP_R2] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_R2]
  888. connect_bd_net -net VCAP_R3_0_1 [get_bd_ports VCAP_R3] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_R3]
  889. connect_bd_net -net VCAP_R4_0_1 [get_bd_ports VCAP_R4] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_R4]
  890. connect_bd_net -net VCAP_R5_0_1 [get_bd_ports VCAP_R5] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_R5]
  891. connect_bd_net -net VCAP_R6_0_1 [get_bd_ports VCAP_R6] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_R6]
  892. connect_bd_net -net VCAP_R7_0_1 [get_bd_ports VCAP_R7] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_R7]
  893. connect_bd_net -net VCAP_VSYNC_0_1 [get_bd_ports VCAP_VSYNC] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_VSYNC]
  894. connect_bd_net -net ZORRO_C28D_0_1 [get_bd_ports ZORRO_C28D] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_C28D]
  895. connect_bd_net -net ZORRO_DOE_1 [get_bd_ports ZORRO_DOE] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_DOE]
  896. connect_bd_net -net ZORRO_E7M_1 [get_bd_ports ZORRO_E7M] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_E7M]
  897. connect_bd_net -net ZORRO_NBGN_0_1 [get_bd_ports ZORRO_NBGN] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NBGN]
  898. connect_bd_net -net ZORRO_NCCS_1 [get_bd_ports ZORRO_NCCS] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NCCS]
  899. connect_bd_net -net ZORRO_NCFGIN_1 [get_bd_ports ZORRO_NCFGIN] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NCFGIN]
  900. connect_bd_net -net ZORRO_NDS0_1 [get_bd_ports ZORRO_NDS0] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NDS0]
  901. connect_bd_net -net ZORRO_NDS1_1 [get_bd_ports ZORRO_NDS1] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NDS1]
  902. connect_bd_net -net ZORRO_NFCS_1 [get_bd_ports ZORRO_NFCS] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NFCS]
  903. connect_bd_net -net ZORRO_NIORST_1 [get_bd_ports ZORRO_NIORST] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NIORST]
  904. connect_bd_net -net ZORRO_NLDS_1 [get_bd_ports ZORRO_NLDS] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NLDS]
  905. connect_bd_net -net ZORRO_NUDS_1 [get_bd_ports ZORRO_NUDS] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NUDS]
  906. connect_bd_net -net ZORRO_READ_1 [get_bd_ports ZORRO_READ] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_READ]
  907. connect_bd_net -net clk_1 [get_bd_ports VGA_PCLK] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins video/VGA_PCLK]
  908. connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins MNTZorro_v0_1_S00_AXI_0/S_AXI_ARESETN] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/m00_axi_aresetn] [get_bd_pins axi_protocol_convert_0/aresetn] [get_bd_pins axi_protocol_convert_1/aresetn] [get_bd_pins axi_protocol_convert_2/aresetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins axi_register_slice_1/aresetn] [get_bd_pins axi_register_slice_2/aresetn] [get_bd_pins axi_register_slice_3/aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins video/aresetn]
  909. connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins MNTZorro_v0_1_S00_AXI_0/S_AXI_ACLK] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/m00_axi_aclk] [get_bd_pins axi_protocol_convert_0/aclk] [get_bd_pins axi_protocol_convert_1/aclk] [get_bd_pins axi_protocol_convert_2/aclk] [get_bd_pins axi_register_slice_0/aclk] [get_bd_pins axi_register_slice_1/aclk] [get_bd_pins axi_register_slice_2/aclk] [get_bd_pins axi_register_slice_3/aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins video/m_axi_mm2s_aclk]
  910. connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_pins clk_wiz_0/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK1] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_25M/slowest_sync_clk] [get_bd_pins video/s_axi_lite_aclk]
  911. connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_25M/ext_reset_in]
  912. connect_bd_net -net rst_ps7_0_25M_peripheral_aresetn [get_bd_pins clk_wiz_0/s_axi_aresetn] [get_bd_pins rst_ps7_0_25M/peripheral_aresetn] [get_bd_pins video/axi_resetn]
  913. connect_bd_net -net v_axi4s_vid_out_0_vid_data [get_bd_pins video/dvi_rgb] [get_bd_pins xlslice_0/Din] [get_bd_pins xlslice_1/Din] [get_bd_pins xlslice_2/Din]
  914. connect_bd_net -net video_subsystem_VGA_DE [get_bd_ports VGA_DE] [get_bd_pins video/VGA_DE]
  915. connect_bd_net -net video_subsystem_VGA_HS [get_bd_ports VGA_HS] [get_bd_pins video/VGA_HS]
  916. connect_bd_net -net video_subsystem_VGA_VS [get_bd_ports VGA_VS] [get_bd_pins video/VGA_VS]
  917. connect_bd_net -net xlslice_0_Dout [get_bd_ports VGA_R] [get_bd_pins xlslice_0/Dout]
  918. connect_bd_net -net xlslice_1_Dout [get_bd_ports VGA_G] [get_bd_pins xlslice_1/Dout]
  919. connect_bd_net -net xlslice_2_Dout [get_bd_ports VGA_B] [get_bd_pins xlslice_2/Dout]
  920. # Create address segments
  921. create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces MNTZorro_v0_1_S00_AXI_0/m00_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
  922. create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs MNTZorro_v0_1_S00_AXI_0/S_AXI/reg0] SEG_MNTZorro_v0_1_S00_AXI_0_reg0
  923. create_bd_addr_seg -range 0x00010000 -offset 0x83000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs video/axi_vdma_0/S_AXI_LITE/Reg] SEG_axi_vdma_0_Reg
  924. create_bd_addr_seg -range 0x00010000 -offset 0x83C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs clk_wiz_0/s_axi_lite/Reg] SEG_clk_wiz_0_Reg
  925. create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces video/axi_vdma_0/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM
  926. # Restore current instance
  927. current_bd_instance $oldCurInst
  928. validate_bd_design
  929. save_bd_design
  930. }
  931. # End of create_root_design()
  932. ##################################################################
  933. # MAIN FLOW
  934. ##################################################################
  935. create_root_design ""