zz9000-firmware/zz9000_project.tcl

#*****************************************************************************************
# Vivado (TM) v2018.3 (64-bit)
#
# zz9000_project.tcl: Tcl script for re-creating project 'ZZ9000_proto'
#
# Generated by Vivado on Sun Jan 05 20:23:52 CET 2020
# IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
# file in the Vivado Tcl Shell.
#
# * Note that the runs in the created project will be configured the same way as the
#   original project, however they will not be launched automatically. To regenerate the
#   run results please launch the synthesis/implementation runs as needed.
#
#*****************************************************************************************
# NOTE: In order to use this script for source control purposes, please make sure that the
#       following files are added to the source control system:-
#
# 1. This project restoration tcl script (zz9000_project.tcl) that was generated.
#
# 2. The following source(s) files that were local or imported into the original project.
#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
#
#    "/home/mntmn/code/ZZ9000_proto/mntzorro.v"
#    "/home/mntmn/code/ZZ9000_proto/video_formatter.v"
#    "/home/mntmn/code/ZZ9000_proto/ZZ9000_proto.srcs/sources_1/bd/zz9000_ps/hdl/zz9000_ps_wrapper.v"
#    "/home/mntmn/code/ZZ9000_proto/ZZ9000_proto.srcs/constrs_1/new/zz9000.xdc"
#
# 3. The following remote source files that were added to the original project:-
#
#    <none>
#
#*****************************************************************************************

# Set the reference directory for source file relative paths (by default the value is script directory path)
set origin_dir "."

# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } {
  set origin_dir $::origin_dir_loc
}

# Set the project name
set _xil_proj_name_ "ZZ9000_proto"

# Use project name variable, if specified in the tcl shell
if { [info exists ::user_project_name] } {
  set _xil_proj_name_ $::user_project_name
}

variable script_file
set script_file "zz9000_project.tcl"

# Help information for this script
proc print_help {} {
  variable script_file
  puts "\nDescription:"
  puts "Recreate a Vivado project from this script. The created project will be"
  puts "functionally equivalent to the original project for which this script was"
  puts "generated. The script contains commands for creating a project, filesets,"
  puts "runs, adding/importing sources and setting properties on various objects.\n"
  puts "Syntax:"
  puts "$script_file"
  puts "$script_file -tclargs \[--origin_dir <path>\]"
  puts "$script_file -tclargs \[--project_name <name>\]"
  puts "$script_file -tclargs \[--help\]\n"
  puts "Usage:"
  puts "Name                   Description"
  puts "-------------------------------------------------------------------------"
  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
  puts "                       origin_dir path value is \".\", otherwise, the value"
  puts "                       that was set with the \"-paths_relative_to\" switch"
  puts "                       when this script was generated.\n"
  puts "\[--project_name <name>\] Create project with the specified name. Default"
  puts "                       name is the name of the project from where this"
  puts "                       script was generated.\n"
  puts "\[--help\]               Print help information for this script"
  puts "-------------------------------------------------------------------------\n"
  exit 0
}

if { $::argc > 0 } {
  for {set i 0} {$i < $::argc} {incr i} {
    set option [string trim [lindex $::argv $i]]
    switch -regexp -- $option {
      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
      "--help"         { print_help }
      default {
        if { [regexp {^-} $option] } {
          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
          return 1
        }
      }
    }
  }
}

# Set the directory path for the original project from where this script was exported
set orig_proj_dir "[file normalize "$origin_dir/"]"

# Create project
create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg400-1

# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]

# Set project properties
set obj [current_project]
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj
set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj
set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj
set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj
set_property -name "dsa.emu_dir" -value "emu" -objects $obj
set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj
set_property -name "dsa.flash_offset_address" -value "0" -objects $obj
set_property -name "dsa.flash_size" -value "1024" -objects $obj
set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj
set_property -name "dsa.host_interface" -value "pcie" -objects $obj
set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj
set_property -name "dsa.vendor" -value "xilinx" -objects $obj
set_property -name "dsa.version" -value "0.0" -objects $obj
set_property -name "enable_vhdl_2008" -value "1" -objects $obj
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
set_property -name "part" -value "xc7z020clg400-1" -objects $obj
set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "webtalk.activehdl_export_sim" -value "21" -objects $obj
set_property -name "webtalk.ies_export_sim" -value "21" -objects $obj
set_property -name "webtalk.modelsim_export_sim" -value "21" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "21" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "21" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "21" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "21" -objects $obj
set_property -name "webtalk.xsim_launch_sim" -value "38" -objects $obj
set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj

# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
  create_fileset -srcset sources_1
}

# Set IP repository paths
set obj [get_filesets sources_1]
set_property "ip_repo_paths" "[file normalize "$origin_dir/../ip_repo/MNTZorro_1.0"]" $obj

# Rebuild user ip_repo's index before adding any source files
update_ip_catalog -rebuild

# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
# Import local files from the original project
set files [list \
 [file normalize "${origin_dir}/mntzorro.v" ]\
 [file normalize "${origin_dir}/video_formatter.v" ]\
 [file normalize "${origin_dir}/ZZ9000_proto.srcs/sources_1/bd/zz9000_ps/hdl/zz9000_ps_wrapper.v" ]\
]
set imported_files [import_files -fileset sources_1 $files]

# Set 'sources_1' fileset file properties for remote files
# None

# Set 'sources_1' fileset file properties for local files
set file "mntzorro.v"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "path_mode" -value "RelativeOnly" -objects $file_obj


# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
set_property -name "top" -value "zz9000_ps_wrapper" -objects $obj

# Create 'constrs_1' fileset (if not found)
if {[string equal [get_filesets -quiet constrs_1] ""]} {
  create_fileset -constrset constrs_1
}

# Set 'constrs_1' fileset object
set obj [get_filesets constrs_1]

# Add/Import constrs file and set constrs file properties
set file "[file normalize "$origin_dir/ZZ9000_proto.srcs/constrs_1/new/zz9000.xdc"]"
set file_imported [import_files -fileset constrs_1 [list $file]]
set file "new/zz9000.xdc"
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
set_property -name "file_type" -value "XDC" -objects $file_obj

# Set 'constrs_1' fileset properties
set obj [get_filesets constrs_1]
set_property -name "target_constrs_file" -value "[get_files *new/zz9000.xdc]" -objects $obj
set_property -name "target_part" -value "xc7z020clg400-1" -objects $obj
set_property -name "target_ucf" -value "[get_files *new/zz9000.xdc]" -objects $obj

# Create 'sim_1' fileset (if not found)
if {[string equal [get_filesets -quiet sim_1] ""]} {
  create_fileset -simset sim_1
}

# Set 'sim_1' fileset object
set obj [get_filesets sim_1]
# Empty (no sources present)

# Set 'sim_1' fileset properties
set obj [get_filesets sim_1]
set_property -name "nl.mode" -value "funcsim" -objects $obj
set_property -name "sim_mode" -value "post-synthesis" -objects $obj
set_property -name "top" -value "zz9000_ps_wrapper" -objects $obj
set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
set_property -name "xsim.elaborate.mt_level" -value "off" -objects $obj
set_property -name "xsim.elaborate.xelab.more_options" -value "-v 1" -objects $obj

# Set 'utils_1' fileset object
set obj [get_filesets utils_1]
# Empty (no sources present)

# Set 'utils_1' fileset properties
set obj [get_filesets utils_1]


# Adding sources referenced in BDs, if not already added
if { [get_files mntzorro.v] == "" } {
  import_files -quiet -fileset sources_1 mntzorro.v
}
if { [get_files video_formatter.v] == "" } {
  import_files -quiet -fileset sources_1 video_formatter.v
}


# Proc to create BD zz9000_ps
proc cr_bd_zz9000_ps { parentCell } {
# The design that will be created by this Tcl proc contains the following 
# module references:
# MNTZorro_v0_1_S00_AXI, video_formatter



  # CHANGE DESIGN NAME HERE
  set design_name zz9000_ps

  common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."

  create_bd_design $design_name

  set bCheckIPsPassed 1
  ##################################################################
  # CHECK IPs
  ##################################################################
  set bCheckIPs 1
  if { $bCheckIPs == 1 } {
     set list_check_ips "\ 
  xilinx.com:ip:axi_dwidth_converter:2.1\
  xilinx.com:ip:axi_protocol_converter:2.1\
  xilinx.com:ip:axi_register_slice:2.1\
  xilinx.com:ip:clk_wiz:6.0\
  xilinx.com:ip:proc_sys_reset:5.0\
  xilinx.com:ip:processing_system7:5.5\
  xilinx.com:ip:xlslice:1.0\
  xilinx.com:ip:axi_vdma:6.3\
  xilinx.com:ip:axis_data_fifo:2.0\
  "

   set list_ips_missing ""
   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."

   foreach ip_vlnv $list_check_ips {
      set ip_obj [get_ipdefs -all $ip_vlnv]
      if { $ip_obj eq "" } {
         lappend list_ips_missing $ip_vlnv
      }
   }

   if { $list_ips_missing ne "" } {
      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
      set bCheckIPsPassed 0
   }

  }

  ##################################################################
  # CHECK Modules
  ##################################################################
  set bCheckModules 1
  if { $bCheckModules == 1 } {
     set list_check_mods "\ 
  MNTZorro_v0_1_S00_AXI\
  video_formatter\
  "

   set list_mods_missing ""
   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."

   foreach mod_vlnv $list_check_mods {
      if { [can_resolve_reference $mod_vlnv] == 0 } {
         lappend list_mods_missing $mod_vlnv
      }
   }

   if { $list_mods_missing ne "" } {
      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
      common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above."
      set bCheckIPsPassed 0
   }
}

  if { $bCheckIPsPassed != 1 } {
    common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
    return 3
  }

  
# Hierarchical cell: video
proc create_hier_cell_video { parentCell nameHier } {

  variable script_folder

  if { $parentCell eq "" || $nameHier eq "" } {
     catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_video() - Empty argument(s)!"}
     return
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj

  # Create cell and set as current instance
  set hier_obj [create_bd_cell -type hier $nameHier]
  current_bd_instance $hier_obj

  # Create interface pins
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_MM2S
  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_LITE

  # Create pins
  create_bd_pin -dir O VGA_DE
  create_bd_pin -dir O VGA_HS
  create_bd_pin -dir I -type clk VGA_PCLK
  create_bd_pin -dir O VGA_VS
  create_bd_pin -dir I -type rst aresetn
  create_bd_pin -dir I -type rst axi_resetn
  create_bd_pin -dir I -from 31 -to 0 control_data
  create_bd_pin -dir I control_interlace
  create_bd_pin -dir I -from 7 -to 0 control_op
  create_bd_pin -dir O control_vblank
  create_bd_pin -dir O -from 31 -to 0 dvi_rgb
  create_bd_pin -dir I -type clk m_axi_mm2s_aclk
  create_bd_pin -dir I -type clk s_axi_lite_aclk

  # Create instance: axi_vdma_0, and set properties
  set axi_vdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.3 axi_vdma_0 ]
  set_property -dict [ list \
   CONFIG.c_include_mm2s_dre {0} \
   CONFIG.c_include_s2mm {0} \
   CONFIG.c_m_axi_mm2s_data_width {32} \
   CONFIG.c_mm2s_genlock_mode {0} \
   CONFIG.c_mm2s_linebuffer_depth {2048} \
   CONFIG.c_mm2s_max_burst_length {128} \
   CONFIG.c_num_fstores {1} \
   CONFIG.c_s2mm_genlock_mode {0} \
 ] $axi_vdma_0

  # Create instance: axis_data_fifo_0, and set properties
  set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
  set_property -dict [ list \
   CONFIG.FIFO_DEPTH {32} \
 ] $axis_data_fifo_0

  # Create instance: video_formatter_0, and set properties
  set block_name video_formatter
  set block_cell_name video_formatter_0
  if { [catch {set video_formatter_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $video_formatter_0 eq "" } {
     catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create interface connections
  connect_bd_intf_net -intf_net axi_vdma_0_M_AXIS_MM2S [get_bd_intf_pins axi_vdma_0/M_AXIS_MM2S] [get_bd_intf_pins axis_data_fifo_0/S_AXIS]
  connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axis_data_fifo_0/M_AXIS] [get_bd_intf_pins video_formatter_0/m_axis_vid]
  connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins S_AXI_LITE] [get_bd_intf_pins axi_vdma_0/S_AXI_LITE]
  connect_bd_intf_net -intf_net video_subsystem_M_AXI_MM2S [get_bd_intf_pins M_AXI_MM2S] [get_bd_intf_pins axi_vdma_0/M_AXI_MM2S]

  # Create port connections
  connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_data [get_bd_pins control_data] [get_bd_pins video_formatter_0/control_data]
  connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_interlace [get_bd_pins control_interlace] [get_bd_pins video_formatter_0/control_interlace]
  connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_op [get_bd_pins control_op] [get_bd_pins video_formatter_0/control_op]
  connect_bd_net -net clk_1 [get_bd_pins VGA_PCLK] [get_bd_pins video_formatter_0/dvi_clk]
  connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins video_formatter_0/aresetn]
  connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins m_axi_mm2s_aclk] [get_bd_pins axi_vdma_0/m_axi_mm2s_aclk] [get_bd_pins axi_vdma_0/m_axis_mm2s_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins video_formatter_0/m_axis_vid_aclk]
  connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_pins s_axi_lite_aclk] [get_bd_pins axi_vdma_0/s_axi_lite_aclk]
  connect_bd_net -net rst_ps7_0_25M_peripheral_aresetn [get_bd_pins axi_resetn] [get_bd_pins axi_vdma_0/axi_resetn]
  connect_bd_net -net v_axi4s_vid_out_0_vid_data [get_bd_pins dvi_rgb] [get_bd_pins video_formatter_0/dvi_rgb]
  connect_bd_net -net video_formatter_0_control_vblank [get_bd_pins control_vblank] [get_bd_pins video_formatter_0/control_vblank]
  connect_bd_net -net video_subsystem_VGA_DE [get_bd_pins VGA_DE] [get_bd_pins video_formatter_0/dvi_active_video]
  connect_bd_net -net video_subsystem_VGA_HS [get_bd_pins VGA_HS] [get_bd_pins video_formatter_0/dvi_hsync]
  connect_bd_net -net video_subsystem_VGA_VS [get_bd_pins VGA_VS] [get_bd_pins video_formatter_0/dvi_vsync]

  # Restore current instance
  current_bd_instance $oldCurInst
}
  variable script_folder

  if { $parentCell eq "" } {
     set parentCell [get_bd_cells /]
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj


  # Create interface ports
  set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
  set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]

  # Create ports
  set VCAP_B0 [ create_bd_port -dir I VCAP_B0 ]
  set VCAP_B1 [ create_bd_port -dir I VCAP_B1 ]
  set VCAP_B2 [ create_bd_port -dir I VCAP_B2 ]
  set VCAP_B3 [ create_bd_port -dir I VCAP_B3 ]
  set VCAP_B4 [ create_bd_port -dir I VCAP_B4 ]
  set VCAP_B5 [ create_bd_port -dir I VCAP_B5 ]
  set VCAP_B6 [ create_bd_port -dir I VCAP_B6 ]
  set VCAP_B7 [ create_bd_port -dir I VCAP_B7 ]
  set VCAP_G0 [ create_bd_port -dir I VCAP_G0 ]
  set VCAP_G1 [ create_bd_port -dir I VCAP_G1 ]
  set VCAP_G2 [ create_bd_port -dir I VCAP_G2 ]
  set VCAP_G3 [ create_bd_port -dir I VCAP_G3 ]
  set VCAP_G4 [ create_bd_port -dir I VCAP_G4 ]
  set VCAP_G5 [ create_bd_port -dir I VCAP_G5 ]
  set VCAP_G6 [ create_bd_port -dir I VCAP_G6 ]
  set VCAP_G7 [ create_bd_port -dir I VCAP_G7 ]
  set VCAP_HSYNC [ create_bd_port -dir I VCAP_HSYNC ]
  set VCAP_R0 [ create_bd_port -dir I VCAP_R0 ]
  set VCAP_R1 [ create_bd_port -dir I VCAP_R1 ]
  set VCAP_R2 [ create_bd_port -dir I VCAP_R2 ]
  set VCAP_R3 [ create_bd_port -dir I VCAP_R3 ]
  set VCAP_R4 [ create_bd_port -dir I VCAP_R4 ]
  set VCAP_R5 [ create_bd_port -dir I VCAP_R5 ]
  set VCAP_R6 [ create_bd_port -dir I VCAP_R6 ]
  set VCAP_R7 [ create_bd_port -dir I VCAP_R7 ]
  set VCAP_VSYNC [ create_bd_port -dir I VCAP_VSYNC ]
  set VGA_B [ create_bd_port -dir O -from 7 -to 0 VGA_B ]
  set VGA_DE [ create_bd_port -dir O VGA_DE ]
  set VGA_G [ create_bd_port -dir O -from 7 -to 0 VGA_G ]
  set VGA_HS [ create_bd_port -dir O VGA_HS ]
  set VGA_PCLK [ create_bd_port -dir O -type clk VGA_PCLK ]
  set VGA_R [ create_bd_port -dir O -from 7 -to 0 VGA_R ]
  set VGA_VS [ create_bd_port -dir O VGA_VS ]
  set ZORRO_ADDR [ create_bd_port -dir IO -from 22 -to 0 ZORRO_ADDR ]
  set ZORRO_ADDRDIR [ create_bd_port -dir O ZORRO_ADDRDIR ]
  set ZORRO_ADDRDIR2 [ create_bd_port -dir O ZORRO_ADDRDIR2 ]
  set ZORRO_C28D [ create_bd_port -dir I ZORRO_C28D ]
  set ZORRO_DATA [ create_bd_port -dir IO -from 15 -to 0 ZORRO_DATA ]
  set ZORRO_DATADIR [ create_bd_port -dir O ZORRO_DATADIR ]
  set ZORRO_DOE [ create_bd_port -dir I ZORRO_DOE ]
  set ZORRO_E7M [ create_bd_port -dir I ZORRO_E7M ]
  set ZORRO_INT6 [ create_bd_port -dir O ZORRO_INT6 ]
  set ZORRO_NBGN [ create_bd_port -dir I ZORRO_NBGN ]
  set ZORRO_NBRN [ create_bd_port -dir O ZORRO_NBRN ]
  set ZORRO_NCCS [ create_bd_port -dir I ZORRO_NCCS ]
  set ZORRO_NCFGIN [ create_bd_port -dir I ZORRO_NCFGIN ]
  set ZORRO_NCFGOUT [ create_bd_port -dir O ZORRO_NCFGOUT ]
  set ZORRO_NCINH [ create_bd_port -dir O ZORRO_NCINH ]
  set ZORRO_NDS0 [ create_bd_port -dir I ZORRO_NDS0 ]
  set ZORRO_NDS1 [ create_bd_port -dir I ZORRO_NDS1 ]
  set ZORRO_NDTACK [ create_bd_port -dir O ZORRO_NDTACK ]
  set ZORRO_NFCS [ create_bd_port -dir I ZORRO_NFCS ]
  set ZORRO_NIORST [ create_bd_port -dir I ZORRO_NIORST ]
  set ZORRO_NLDS [ create_bd_port -dir I ZORRO_NLDS ]
  set ZORRO_NSLAVE [ create_bd_port -dir O ZORRO_NSLAVE ]
  set ZORRO_NUDS [ create_bd_port -dir I ZORRO_NUDS ]
  set ZORRO_READ [ create_bd_port -dir I ZORRO_READ ]

  # Create instance: MNTZorro_v0_1_S00_AXI_0, and set properties
  set block_name MNTZorro_v0_1_S00_AXI
  set block_cell_name MNTZorro_v0_1_S00_AXI_0
  if { [catch {set MNTZorro_v0_1_S00_AXI_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $MNTZorro_v0_1_S00_AXI_0 eq "" } {
     catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create instance: axi_dwidth_converter_0, and set properties
  set axi_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_0 ]

  # Create instance: axi_mem_intercon, and set properties
  set axi_mem_intercon [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon ]
  set_property -dict [ list \
   CONFIG.NUM_MI {1} \
 ] $axi_mem_intercon

  # Create instance: axi_protocol_convert_0, and set properties
  set axi_protocol_convert_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_converter:2.1 axi_protocol_convert_0 ]

  # Create instance: axi_protocol_convert_1, and set properties
  set axi_protocol_convert_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_converter:2.1 axi_protocol_convert_1 ]
  set_property -dict [ list \
   CONFIG.TRANSLATION_MODE {2} \
 ] $axi_protocol_convert_1

  # Create instance: axi_protocol_convert_2, and set properties
  set axi_protocol_convert_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_converter:2.1 axi_protocol_convert_2 ]

  # Create instance: axi_register_slice_0, and set properties
  set axi_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 ]

  # Create instance: axi_register_slice_1, and set properties
  set axi_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_1 ]

  # Create instance: axi_register_slice_2, and set properties
  set axi_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_2 ]

  # Create instance: axi_register_slice_3, and set properties
  set axi_register_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_3 ]

  # Create instance: clk_wiz_0, and set properties
  set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
  set_property -dict [ list \
   CONFIG.CLKOUT1_DRIVES {BUFG} \
   CONFIG.CLKOUT1_JITTER {272.433} \
   CONFIG.CLKOUT1_PHASE_ERROR {261.747} \
   CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {75} \
   CONFIG.CLKOUT2_DRIVES {BUFG} \
   CONFIG.CLKOUT3_DRIVES {BUFG} \
   CONFIG.CLKOUT4_DRIVES {BUFG} \
   CONFIG.CLKOUT5_DRIVES {BUFG} \
   CONFIG.CLKOUT6_DRIVES {BUFG} \
   CONFIG.CLKOUT7_DRIVES {BUFG} \
   CONFIG.MMCM_CLKFBOUT_MULT_F {33} \
   CONFIG.MMCM_CLKOUT0_DIVIDE_F {11} \
   CONFIG.MMCM_COMPENSATION {ZHOLD} \
   CONFIG.MMCM_DIVCLK_DIVIDE {4} \
   CONFIG.PRIMITIVE {PLL} \
   CONFIG.PRIM_SOURCE {Single_ended_clock_capable_pin} \
   CONFIG.SECONDARY_SOURCE {Single_ended_clock_capable_pin} \
   CONFIG.USE_DYN_RECONFIG {true} \
   CONFIG.USE_PHASE_ALIGNMENT {false} \
 ] $clk_wiz_0

  # Create instance: proc_sys_reset_0, and set properties
  set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]

  # Create instance: processing_system7_0, and set properties
  set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
  set_property -dict [ list \
   CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
   CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
   CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
   CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
   CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
   CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
   CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {25.000000} \
   CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
   CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
   CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
   CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {10.000000} \
   CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {25.000000} \
   CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
   CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
   CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
   CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
   CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
   CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
   CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
   CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
   CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
   CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
   CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
   CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
   CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {666.666} \
   CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
   CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
   CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
   CONFIG.PCW_CLK0_FREQ {100000000} \
   CONFIG.PCW_CLK1_FREQ {25000000} \
   CONFIG.PCW_CLK2_FREQ {10000000} \
   CONFIG.PCW_CLK3_FREQ {10000000} \
   CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
   CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
   CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
   CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
   CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
   CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
   CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
   CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
   CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
   CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \
   CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
   CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
   CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
   CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
   CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
   CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
   CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
   CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
   CONFIG.PCW_ENET0_RESET_ENABLE {0} \
   CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \
   CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
   CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
   CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
   CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
   CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
   CONFIG.PCW_ENET1_RESET_ENABLE {0} \
   CONFIG.PCW_ENET_RESET_ENABLE {0} \
   CONFIG.PCW_ENET_RESET_SELECT {<Select>} \
   CONFIG.PCW_EN_CLK0_PORT {1} \
   CONFIG.PCW_EN_CLK1_PORT {1} \
   CONFIG.PCW_EN_DDR {1} \
   CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \
   CONFIG.PCW_EN_EMIO_ENET0 {0} \
   CONFIG.PCW_EN_EMIO_ENET1 {0} \
   CONFIG.PCW_EN_EMIO_GPIO {0} \
   CONFIG.PCW_EN_EMIO_I2C0 {0} \
   CONFIG.PCW_EN_EMIO_TTC0 {0} \
   CONFIG.PCW_EN_EMIO_WDT {0} \
   CONFIG.PCW_EN_ENET0 {1} \
   CONFIG.PCW_EN_ENET1 {0} \
   CONFIG.PCW_EN_GPIO {1} \
   CONFIG.PCW_EN_I2C0 {1} \
   CONFIG.PCW_EN_RST0_PORT {1} \
   CONFIG.PCW_EN_RST1_PORT {0} \
   CONFIG.PCW_EN_SDIO0 {1} \
   CONFIG.PCW_EN_TTC0 {0} \
   CONFIG.PCW_EN_UART1 {1} \
   CONFIG.PCW_EN_USB0 {1} \
   CONFIG.PCW_EN_WDT {0} \
   CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \
   CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
   CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \
   CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {8} \
   CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {5} \
   CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
   CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
   CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
   CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
   CONFIG.PCW_FCLK_CLK0_BUF {FALSE} \
   CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \
   CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
   CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {25} \
   CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
   CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \
   CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
   CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
   CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \
   CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \
   CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
   CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
   CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \
   CONFIG.PCW_I2C0_GRP_INT_IO {<Select>} \
   CONFIG.PCW_I2C0_I2C0_IO {MIO 50 .. 51} \
   CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
   CONFIG.PCW_I2C0_RESET_ENABLE {0} \
   CONFIG.PCW_I2C0_RESET_IO {<Select>} \
   CONFIG.PCW_I2C1_RESET_ENABLE {0} \
   CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {111.111115} \
   CONFIG.PCW_I2C_RESET_ENABLE {0} \
   CONFIG.PCW_I2C_RESET_SELECT {<Select>} \
   CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
   CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
   CONFIG.PCW_MIO_0_DIRECTION {inout} \
   CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_0_PULLUP {enabled} \
   CONFIG.PCW_MIO_0_SLEW {slow} \
   CONFIG.PCW_MIO_10_DIRECTION {inout} \
   CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_10_PULLUP {enabled} \
   CONFIG.PCW_MIO_10_SLEW {slow} \
   CONFIG.PCW_MIO_11_DIRECTION {inout} \
   CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_11_PULLUP {enabled} \
   CONFIG.PCW_MIO_11_SLEW {slow} \
   CONFIG.PCW_MIO_12_DIRECTION {inout} \
   CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_12_PULLUP {enabled} \
   CONFIG.PCW_MIO_12_SLEW {slow} \
   CONFIG.PCW_MIO_13_DIRECTION {inout} \
   CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_13_PULLUP {enabled} \
   CONFIG.PCW_MIO_13_SLEW {slow} \
   CONFIG.PCW_MIO_14_DIRECTION {inout} \
   CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_14_PULLUP {enabled} \
   CONFIG.PCW_MIO_14_SLEW {slow} \
   CONFIG.PCW_MIO_15_DIRECTION {inout} \
   CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_15_PULLUP {enabled} \
   CONFIG.PCW_MIO_15_SLEW {slow} \
   CONFIG.PCW_MIO_16_DIRECTION {out} \
   CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_16_PULLUP {enabled} \
   CONFIG.PCW_MIO_16_SLEW {slow} \
   CONFIG.PCW_MIO_17_DIRECTION {out} \
   CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_17_PULLUP {enabled} \
   CONFIG.PCW_MIO_17_SLEW {slow} \
   CONFIG.PCW_MIO_18_DIRECTION {out} \
   CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_18_PULLUP {enabled} \
   CONFIG.PCW_MIO_18_SLEW {slow} \
   CONFIG.PCW_MIO_19_DIRECTION {out} \
   CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_19_PULLUP {enabled} \
   CONFIG.PCW_MIO_19_SLEW {slow} \
   CONFIG.PCW_MIO_1_DIRECTION {inout} \
   CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_1_PULLUP {enabled} \
   CONFIG.PCW_MIO_1_SLEW {slow} \
   CONFIG.PCW_MIO_20_DIRECTION {out} \
   CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_20_PULLUP {enabled} \
   CONFIG.PCW_MIO_20_SLEW {slow} \
   CONFIG.PCW_MIO_21_DIRECTION {out} \
   CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_21_PULLUP {enabled} \
   CONFIG.PCW_MIO_21_SLEW {slow} \
   CONFIG.PCW_MIO_22_DIRECTION {in} \
   CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_22_PULLUP {enabled} \
   CONFIG.PCW_MIO_22_SLEW {slow} \
   CONFIG.PCW_MIO_23_DIRECTION {in} \
   CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_23_PULLUP {enabled} \
   CONFIG.PCW_MIO_23_SLEW {slow} \
   CONFIG.PCW_MIO_24_DIRECTION {in} \
   CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_24_PULLUP {enabled} \
   CONFIG.PCW_MIO_24_SLEW {slow} \
   CONFIG.PCW_MIO_25_DIRECTION {in} \
   CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_25_PULLUP {enabled} \
   CONFIG.PCW_MIO_25_SLEW {slow} \
   CONFIG.PCW_MIO_26_DIRECTION {in} \
   CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_26_PULLUP {enabled} \
   CONFIG.PCW_MIO_26_SLEW {slow} \
   CONFIG.PCW_MIO_27_DIRECTION {in} \
   CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_27_PULLUP {enabled} \
   CONFIG.PCW_MIO_27_SLEW {slow} \
   CONFIG.PCW_MIO_28_DIRECTION {inout} \
   CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_28_PULLUP {enabled} \
   CONFIG.PCW_MIO_28_SLEW {slow} \
   CONFIG.PCW_MIO_29_DIRECTION {in} \
   CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_29_PULLUP {enabled} \
   CONFIG.PCW_MIO_29_SLEW {slow} \
   CONFIG.PCW_MIO_2_DIRECTION {inout} \
   CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_2_PULLUP {disabled} \
   CONFIG.PCW_MIO_2_SLEW {slow} \
   CONFIG.PCW_MIO_30_DIRECTION {out} \
   CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_30_PULLUP {enabled} \
   CONFIG.PCW_MIO_30_SLEW {slow} \
   CONFIG.PCW_MIO_31_DIRECTION {in} \
   CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_31_PULLUP {enabled} \
   CONFIG.PCW_MIO_31_SLEW {slow} \
   CONFIG.PCW_MIO_32_DIRECTION {inout} \
   CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_32_PULLUP {enabled} \
   CONFIG.PCW_MIO_32_SLEW {slow} \
   CONFIG.PCW_MIO_33_DIRECTION {inout} \
   CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_33_PULLUP {enabled} \
   CONFIG.PCW_MIO_33_SLEW {slow} \
   CONFIG.PCW_MIO_34_DIRECTION {inout} \
   CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_34_PULLUP {enabled} \
   CONFIG.PCW_MIO_34_SLEW {slow} \
   CONFIG.PCW_MIO_35_DIRECTION {inout} \
   CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_35_PULLUP {enabled} \
   CONFIG.PCW_MIO_35_SLEW {slow} \
   CONFIG.PCW_MIO_36_DIRECTION {in} \
   CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_36_PULLUP {enabled} \
   CONFIG.PCW_MIO_36_SLEW {slow} \
   CONFIG.PCW_MIO_37_DIRECTION {inout} \
   CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_37_PULLUP {enabled} \
   CONFIG.PCW_MIO_37_SLEW {slow} \
   CONFIG.PCW_MIO_38_DIRECTION {inout} \
   CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_38_PULLUP {enabled} \
   CONFIG.PCW_MIO_38_SLEW {slow} \
   CONFIG.PCW_MIO_39_DIRECTION {inout} \
   CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_39_PULLUP {enabled} \
   CONFIG.PCW_MIO_39_SLEW {slow} \
   CONFIG.PCW_MIO_3_DIRECTION {inout} \
   CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_3_PULLUP {disabled} \
   CONFIG.PCW_MIO_3_SLEW {slow} \
   CONFIG.PCW_MIO_40_DIRECTION {inout} \
   CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_40_PULLUP {enabled} \
   CONFIG.PCW_MIO_40_SLEW {slow} \
   CONFIG.PCW_MIO_41_DIRECTION {inout} \
   CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_41_PULLUP {enabled} \
   CONFIG.PCW_MIO_41_SLEW {slow} \
   CONFIG.PCW_MIO_42_DIRECTION {inout} \
   CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_42_PULLUP {enabled} \
   CONFIG.PCW_MIO_42_SLEW {slow} \
   CONFIG.PCW_MIO_43_DIRECTION {inout} \
   CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_43_PULLUP {enabled} \
   CONFIG.PCW_MIO_43_SLEW {slow} \
   CONFIG.PCW_MIO_44_DIRECTION {inout} \
   CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_44_PULLUP {enabled} \
   CONFIG.PCW_MIO_44_SLEW {slow} \
   CONFIG.PCW_MIO_45_DIRECTION {inout} \
   CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_45_PULLUP {enabled} \
   CONFIG.PCW_MIO_45_SLEW {slow} \
   CONFIG.PCW_MIO_46_DIRECTION {inout} \
   CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_46_PULLUP {enabled} \
   CONFIG.PCW_MIO_46_SLEW {slow} \
   CONFIG.PCW_MIO_47_DIRECTION {inout} \
   CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_47_PULLUP {enabled} \
   CONFIG.PCW_MIO_47_SLEW {slow} \
   CONFIG.PCW_MIO_48_DIRECTION {out} \
   CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_48_PULLUP {enabled} \
   CONFIG.PCW_MIO_48_SLEW {slow} \
   CONFIG.PCW_MIO_49_DIRECTION {in} \
   CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_49_PULLUP {enabled} \
   CONFIG.PCW_MIO_49_SLEW {slow} \
   CONFIG.PCW_MIO_4_DIRECTION {inout} \
   CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_4_PULLUP {disabled} \
   CONFIG.PCW_MIO_4_SLEW {slow} \
   CONFIG.PCW_MIO_50_DIRECTION {inout} \
   CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_50_PULLUP {enabled} \
   CONFIG.PCW_MIO_50_SLEW {slow} \
   CONFIG.PCW_MIO_51_DIRECTION {inout} \
   CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_51_PULLUP {enabled} \
   CONFIG.PCW_MIO_51_SLEW {slow} \
   CONFIG.PCW_MIO_52_DIRECTION {out} \
   CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_52_PULLUP {enabled} \
   CONFIG.PCW_MIO_52_SLEW {slow} \
   CONFIG.PCW_MIO_53_DIRECTION {inout} \
   CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
   CONFIG.PCW_MIO_53_PULLUP {enabled} \
   CONFIG.PCW_MIO_53_SLEW {slow} \
   CONFIG.PCW_MIO_5_DIRECTION {inout} \
   CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_5_PULLUP {disabled} \
   CONFIG.PCW_MIO_5_SLEW {slow} \
   CONFIG.PCW_MIO_6_DIRECTION {inout} \
   CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_6_PULLUP {disabled} \
   CONFIG.PCW_MIO_6_SLEW {slow} \
   CONFIG.PCW_MIO_7_DIRECTION {out} \
   CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_7_PULLUP {disabled} \
   CONFIG.PCW_MIO_7_SLEW {slow} \
   CONFIG.PCW_MIO_8_DIRECTION {out} \
   CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_8_PULLUP {disabled} \
   CONFIG.PCW_MIO_8_SLEW {slow} \
   CONFIG.PCW_MIO_9_DIRECTION {inout} \
   CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
   CONFIG.PCW_MIO_9_PULLUP {enabled} \
   CONFIG.PCW_MIO_9_SLEW {slow} \
   CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO#GPIO#UART 1#UART 1#I2C 0#I2C 0#Enet 0#Enet 0} \
   CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#gpio[1]#gpio[2]#gpio[3]#gpio[4]#gpio[5]#gpio[6]#gpio[7]#gpio[8]#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#gpio[46]#gpio[47]#tx#rx#scl#sda#mdc#mdio} \
   CONFIG.PCW_P2F_ENET0_INTR {1} \
   CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
   CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
   CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {1} \
   CONFIG.PCW_SD0_GRP_CD_ENABLE {0} \
   CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
   CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
   CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
   CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
   CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
   CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {40} \
   CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {25} \
   CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
   CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
   CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
   CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {32} \
   CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {32} \
   CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
   CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
   CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
   CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
   CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0} \
   CONFIG.PCW_TTC0_TTC0_IO {<Select>} \
   CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \
   CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
   CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
   CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
   CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
   CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
   CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
   CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
   CONFIG.PCW_UIPARAM_DDR_AL {0} \
   CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
   CONFIG.PCW_UIPARAM_DDR_BL {8} \
   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.271} \
   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.259} \
   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.219} \
   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.207} \
   CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} \
   CONFIG.PCW_UIPARAM_DDR_CL {7} \
   CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
   CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
   CONFIG.PCW_UIPARAM_DDR_CWL {6} \
   CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.229} \
   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.250} \
   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.121} \
   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.146} \
   CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
   CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
   CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
   CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333} \
   CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
   CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \
   CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \
   CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
   CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
   CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
   CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
   CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
   CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
   CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
   CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \
   CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
   CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
   CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
   CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
   CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
   CONFIG.PCW_USB0_RESET_ENABLE {0} \
   CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
   CONFIG.PCW_USB1_RESET_ENABLE {0} \
   CONFIG.PCW_USB_RESET_ENABLE {0} \
   CONFIG.PCW_USE_AXI_NONSECURE {0} \
   CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {1} \
   CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \
   CONFIG.PCW_USE_M_AXI_GP0 {1} \
   CONFIG.PCW_USE_M_AXI_GP1 {1} \
   CONFIG.PCW_USE_S_AXI_ACP {1} \
   CONFIG.PCW_USE_S_AXI_GP0 {0} \
   CONFIG.PCW_USE_S_AXI_HP0 {1} \
   CONFIG.PCW_USE_S_AXI_HP1 {1} \
   CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \
   CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \
   CONFIG.PCW_WDT_WDT_IO {<Select>} \
 ] $processing_system7_0

  # Create instance: ps7_0_axi_periph, and set properties
  set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
  set_property -dict [ list \
   CONFIG.M00_HAS_DATA_FIFO {0} \
   CONFIG.M00_HAS_REGSLICE {3} \
   CONFIG.M01_HAS_DATA_FIFO {0} \
   CONFIG.M01_HAS_REGSLICE {3} \
   CONFIG.NUM_MI {2} \
   CONFIG.S00_HAS_DATA_FIFO {1} \
   CONFIG.S00_HAS_REGSLICE {4} \
 ] $ps7_0_axi_periph

  # Create instance: rst_ps7_0_25M, and set properties
  set rst_ps7_0_25M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_25M ]
  set_property -dict [ list \
   CONFIG.C_NUM_INTERCONNECT_ARESETN {1} \
   CONFIG.C_NUM_PERP_ARESETN {1} \
 ] $rst_ps7_0_25M

  # Create instance: video
  create_hier_cell_video [current_bd_instance .] video

  # Create instance: xlslice_0, and set properties
  set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ]
  set_property -dict [ list \
   CONFIG.DIN_FROM {23} \
   CONFIG.DIN_TO {16} \
   CONFIG.DIN_WIDTH {32} \
   CONFIG.DOUT_WIDTH {8} \
 ] $xlslice_0

  # Create instance: xlslice_1, and set properties
  set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ]
  set_property -dict [ list \
   CONFIG.DIN_FROM {15} \
   CONFIG.DIN_TO {8} \
   CONFIG.DIN_WIDTH {32} \
   CONFIG.DOUT_WIDTH {8} \
 ] $xlslice_1

  # Create instance: xlslice_2, and set properties
  set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ]
  set_property -dict [ list \
   CONFIG.DIN_FROM {7} \
   CONFIG.DIN_TO {0} \
   CONFIG.DIN_WIDTH {32} \
   CONFIG.DOUT_WIDTH {8} \
 ] $xlslice_2

  # Create interface connections
  connect_bd_intf_net -intf_net MNTZorro_v0_1_S00_AXI_0_m00_axi [get_bd_intf_pins MNTZorro_v0_1_S00_AXI_0/m00_axi] [get_bd_intf_pins axi_protocol_convert_2/S_AXI]
  connect_bd_intf_net -intf_net MNTZorro_v0_1_S00_AXI_0_m01_axi [get_bd_intf_pins MNTZorro_v0_1_S00_AXI_0/m01_axi] [get_bd_intf_pins axi_mem_intercon/S00_AXI]
  connect_bd_intf_net -intf_net axi_dwidth_converter_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/M_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_ACP]
  connect_bd_intf_net -intf_net axi_mem_intercon_M00_AXI [get_bd_intf_pins axi_mem_intercon/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP1]
  connect_bd_intf_net -intf_net axi_protocol_convert_0_M_AXI [get_bd_intf_pins MNTZorro_v0_1_S00_AXI_0/S_AXI] [get_bd_intf_pins axi_protocol_convert_0/M_AXI]
  connect_bd_intf_net -intf_net axi_protocol_convert_1_M_AXI [get_bd_intf_pins axi_protocol_convert_1/M_AXI] [get_bd_intf_pins axi_register_slice_1/S_AXI]
  connect_bd_intf_net -intf_net axi_protocol_convert_2_M_AXI [get_bd_intf_pins axi_protocol_convert_2/M_AXI] [get_bd_intf_pins axi_register_slice_3/S_AXI]
  connect_bd_intf_net -intf_net axi_register_slice_0_M_AXI [get_bd_intf_pins axi_register_slice_0/M_AXI] [get_bd_intf_pins axi_register_slice_2/S_AXI]
  connect_bd_intf_net -intf_net axi_register_slice_1_M_AXI [get_bd_intf_pins axi_register_slice_1/M_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0]
  connect_bd_intf_net -intf_net axi_register_slice_2_M_AXI [get_bd_intf_pins axi_protocol_convert_1/S_AXI] [get_bd_intf_pins axi_register_slice_2/M_AXI]
  connect_bd_intf_net -intf_net axi_register_slice_3_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/S_AXI] [get_bd_intf_pins axi_register_slice_3/M_AXI]
  connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
  connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
  connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins axi_protocol_convert_0/S_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
  connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP1 [get_bd_intf_pins processing_system7_0/M_AXI_GP1] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
  connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins clk_wiz_0/s_axi_lite] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI]
  connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] [get_bd_intf_pins video/S_AXI_LITE]
  connect_bd_intf_net -intf_net video_subsystem_M_AXI_MM2S [get_bd_intf_pins axi_register_slice_0/S_AXI] [get_bd_intf_pins video/M_AXI_MM2S]

  # Create port connections
  connect_bd_net -net M00_ARESETN_1 [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_25M/interconnect_aresetn]
  connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_ADDRDIR [get_bd_ports ZORRO_ADDRDIR] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_ADDRDIR]
  connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_ADDRDIR2 [get_bd_ports ZORRO_ADDRDIR2] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_ADDRDIR2]
  connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_DATADIR [get_bd_ports ZORRO_DATADIR] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_DATADIR]
  connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_INT6 [get_bd_ports ZORRO_INT6] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_INT6]
  connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_NBRN [get_bd_ports ZORRO_NBRN] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NBRN]
  connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_NCFGOUT [get_bd_ports ZORRO_NCFGOUT] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NCFGOUT]
  connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_NCINH [get_bd_ports ZORRO_NCINH] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NCINH]
  connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_NDTACK [get_bd_ports ZORRO_NDTACK] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NDTACK]
  connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_NSLAVE [get_bd_ports ZORRO_NSLAVE] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NSLAVE]
  connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_data [get_bd_pins MNTZorro_v0_1_S00_AXI_0/video_control_data] [get_bd_pins video/control_data]
  connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_interlace [get_bd_pins MNTZorro_v0_1_S00_AXI_0/video_control_interlace] [get_bd_pins video/control_interlace]
  connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_op [get_bd_pins MNTZorro_v0_1_S00_AXI_0/video_control_op] [get_bd_pins video/control_op]
  connect_bd_net -net Net [get_bd_ports ZORRO_ADDR] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_ADDR]
  connect_bd_net -net Net1 [get_bd_ports ZORRO_DATA] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_DATA]
  connect_bd_net -net VCAP_B0_0_1 [get_bd_ports VCAP_B0] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B0]
  connect_bd_net -net VCAP_B1_0_1 [get_bd_ports VCAP_B1] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B1]
  connect_bd_net -net VCAP_B2_0_1 [get_bd_ports VCAP_B2] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B2]
  connect_bd_net -net VCAP_B3_0_1 [get_bd_ports VCAP_B3] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B3]
  connect_bd_net -net VCAP_B4_0_1 [get_bd_ports VCAP_B4] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B4]
  connect_bd_net -net VCAP_B5_0_1 [get_bd_ports VCAP_B5] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B5]
  connect_bd_net -net VCAP_B6_0_1 [get_bd_ports VCAP_B6] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B6]
  connect_bd_net -net VCAP_B7_0_1 [get_bd_ports VCAP_B7] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B7]
  connect_bd_net -net VCAP_G0_0_1 [get_bd_ports VCAP_G0] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_G0]
  connect_bd_net -net VCAP_G1_0_1 [get_bd_ports VCAP_G1] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_G1]
  connect_bd_net -net VCAP_G2_0_1 [get_bd_ports VCAP_G2] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_G2]
  connect_bd_net -net VCAP_G3_0_1 [get_bd_ports VCAP_G3] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_G3]
  connect_bd_net -net VCAP_G4_0_1 [get_bd_ports VCAP_G4] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_G4]
  connect_bd_net -net VCAP_G5_0_1 [get_bd_ports VCAP_G5] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_G5]
  connect_bd_net -net VCAP_G6_0_1 [get_bd_ports VCAP_G6] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_G6]
  connect_bd_net -net VCAP_G7_0_1 [get_bd_ports VCAP_G7] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_G7]
  connect_bd_net -net VCAP_HSYNC_0_1 [get_bd_ports VCAP_HSYNC] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_HSYNC]
  connect_bd_net -net VCAP_R0_0_1 [get_bd_ports VCAP_R0] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_R0]
  connect_bd_net -net VCAP_R1_0_1 [get_bd_ports VCAP_R1] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_R1]
  connect_bd_net -net VCAP_R2_0_1 [get_bd_ports VCAP_R2] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_R2]
  connect_bd_net -net VCAP_R3_0_1 [get_bd_ports VCAP_R3] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_R3]
  connect_bd_net -net VCAP_R4_0_1 [get_bd_ports VCAP_R4] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_R4]
  connect_bd_net -net VCAP_R5_0_1 [get_bd_ports VCAP_R5] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_R5]
  connect_bd_net -net VCAP_R6_0_1 [get_bd_ports VCAP_R6] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_R6]
  connect_bd_net -net VCAP_R7_0_1 [get_bd_ports VCAP_R7] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_R7]
  connect_bd_net -net VCAP_VSYNC_0_1 [get_bd_ports VCAP_VSYNC] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_VSYNC]
  connect_bd_net -net ZORRO_C28D_0_1 [get_bd_ports ZORRO_C28D] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_C28D]
  connect_bd_net -net ZORRO_DOE_1 [get_bd_ports ZORRO_DOE] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_DOE]
  connect_bd_net -net ZORRO_E7M_1 [get_bd_ports ZORRO_E7M] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_E7M]
  connect_bd_net -net ZORRO_NBGN_0_1 [get_bd_ports ZORRO_NBGN] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NBGN]
  connect_bd_net -net ZORRO_NCCS_1 [get_bd_ports ZORRO_NCCS] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NCCS]
  connect_bd_net -net ZORRO_NCFGIN_1 [get_bd_ports ZORRO_NCFGIN] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NCFGIN]
  connect_bd_net -net ZORRO_NDS0_1 [get_bd_ports ZORRO_NDS0] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NDS0]
  connect_bd_net -net ZORRO_NDS1_1 [get_bd_ports ZORRO_NDS1] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NDS1]
  connect_bd_net -net ZORRO_NFCS_1 [get_bd_ports ZORRO_NFCS] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NFCS]
  connect_bd_net -net ZORRO_NIORST_1 [get_bd_ports ZORRO_NIORST] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NIORST]
  connect_bd_net -net ZORRO_NLDS_1 [get_bd_ports ZORRO_NLDS] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NLDS]
  connect_bd_net -net ZORRO_NUDS_1 [get_bd_ports ZORRO_NUDS] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NUDS]
  connect_bd_net -net ZORRO_READ_1 [get_bd_ports ZORRO_READ] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_READ]
  connect_bd_net -net clk_1 [get_bd_ports VGA_PCLK] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins video/VGA_PCLK]
  connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins MNTZorro_v0_1_S00_AXI_0/S_AXI_ARESETN] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/m00_axi_aresetn] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/m01_axi_aresetn] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn] [get_bd_pins axi_mem_intercon/ARESETN] [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins axi_protocol_convert_0/aresetn] [get_bd_pins axi_protocol_convert_1/aresetn] [get_bd_pins axi_protocol_convert_2/aresetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins axi_register_slice_1/aresetn] [get_bd_pins axi_register_slice_2/aresetn] [get_bd_pins axi_register_slice_3/aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins video/aresetn]
  connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins MNTZorro_v0_1_S00_AXI_0/S_AXI_ACLK] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/m00_axi_aclk] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/m01_axi_aclk] [get_bd_pins axi_dwidth_converter_0/s_axi_aclk] [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axi_protocol_convert_0/aclk] [get_bd_pins axi_protocol_convert_1/aclk] [get_bd_pins axi_protocol_convert_2/aclk] [get_bd_pins axi_register_slice_0/aclk] [get_bd_pins axi_register_slice_1/aclk] [get_bd_pins axi_register_slice_2/aclk] [get_bd_pins axi_register_slice_3/aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_ACP_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins video/m_axi_mm2s_aclk]
  connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_pins clk_wiz_0/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK1] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_25M/slowest_sync_clk] [get_bd_pins video/s_axi_lite_aclk]
  connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_25M/ext_reset_in]
  connect_bd_net -net rst_ps7_0_25M_peripheral_aresetn [get_bd_pins clk_wiz_0/s_axi_aresetn] [get_bd_pins rst_ps7_0_25M/peripheral_aresetn] [get_bd_pins video/axi_resetn]
  connect_bd_net -net v_axi4s_vid_out_0_vid_data [get_bd_pins video/dvi_rgb] [get_bd_pins xlslice_0/Din] [get_bd_pins xlslice_1/Din] [get_bd_pins xlslice_2/Din]
  connect_bd_net -net video_control_vblank [get_bd_pins MNTZorro_v0_1_S00_AXI_0/video_control_vblank] [get_bd_pins video/control_vblank]
  connect_bd_net -net video_subsystem_VGA_DE [get_bd_ports VGA_DE] [get_bd_pins video/VGA_DE]
  connect_bd_net -net video_subsystem_VGA_HS [get_bd_ports VGA_HS] [get_bd_pins video/VGA_HS]
  connect_bd_net -net video_subsystem_VGA_VS [get_bd_ports VGA_VS] [get_bd_pins video/VGA_VS]
  connect_bd_net -net xlslice_0_Dout [get_bd_ports VGA_R] [get_bd_pins xlslice_0/Dout]
  connect_bd_net -net xlslice_1_Dout [get_bd_ports VGA_G] [get_bd_pins xlslice_1/Dout]
  connect_bd_net -net xlslice_2_Dout [get_bd_ports VGA_B] [get_bd_pins xlslice_2/Dout]

  # Create address segments
  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces MNTZorro_v0_1_S00_AXI_0/m00_axi] [get_bd_addr_segs processing_system7_0/S_AXI_ACP/ACP_DDR_LOWOCM] SEG_processing_system7_0_ACP_DDR_LOWOCM
  create_bd_addr_seg -range 0x00400000 -offset 0xE0000000 [get_bd_addr_spaces MNTZorro_v0_1_S00_AXI_0/m00_axi] [get_bd_addr_segs processing_system7_0/S_AXI_ACP/ACP_IOP] SEG_processing_system7_0_ACP_IOP
  create_bd_addr_seg -range 0x40000000 -offset 0x40000000 [get_bd_addr_spaces MNTZorro_v0_1_S00_AXI_0/m00_axi] [get_bd_addr_segs processing_system7_0/S_AXI_ACP/ACP_M_AXI_GP0] SEG_processing_system7_0_ACP_M_AXI_GP0
  create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces MNTZorro_v0_1_S00_AXI_0/m00_axi] [get_bd_addr_segs processing_system7_0/S_AXI_ACP/ACP_M_AXI_GP1] SEG_processing_system7_0_ACP_M_AXI_GP1
  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces MNTZorro_v0_1_S00_AXI_0/m01_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
  create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs MNTZorro_v0_1_S00_AXI_0/S_AXI/reg0] SEG_MNTZorro_v0_1_S00_AXI_0_reg0
  create_bd_addr_seg -range 0x00010000 -offset 0x83000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs video/axi_vdma_0/S_AXI_LITE/Reg] SEG_axi_vdma_0_Reg
  create_bd_addr_seg -range 0x00010000 -offset 0x83C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs clk_wiz_0/s_axi_lite/Reg] SEG_clk_wiz_0_Reg
  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces video/axi_vdma_0/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM

  # Perform GUI Layout
  regenerate_bd_layout -layout_string {
   "ExpandedHierarchyInLayout":"",
   "guistr":"# # String gsaved with Nlview 6.8.11  2018-08-07 bk=1.4403 VDI=40 GEI=35 GUI=JA:9.0 TLS
#  -string -flagsOSRD
preplace port ZORRO_C28D -pg 1 -y 1520 -defaultsOSRD
preplace port VCAP_B7 -pg 1 -y 1740 -defaultsOSRD
preplace port VCAP_R6 -pg 1 -y 1920 -defaultsOSRD
preplace port ZORRO_NIORST -pg 1 -y 1460 -defaultsOSRD
preplace port ZORRO_NDS1 -pg 1 -y 1360 -defaultsOSRD
preplace port ZORRO_NLDS -pg 1 -y 1340 -defaultsOSRD
preplace port DDR -pg 1 -y 600 -defaultsOSRD
preplace port VCAP_R7 -pg 1 -y 1900 -defaultsOSRD
preplace port ZORRO_DATADIR -pg 1 -y 1660 -defaultsOSRD
preplace port ZORRO_NCFGIN -pg 1 -y 1480 -defaultsOSRD
preplace port ZORRO_DOE -pg 1 -y 1440 -defaultsOSRD
preplace port VGA_PCLK -pg 1 -y 80 -defaultsOSRD
preplace port ZORRO_NBRN -pg 1 -y 1720 -defaultsOSRD
preplace port VCAP_G0 -pg 1 -y 1580 -defaultsOSRD
preplace port VGA_VS -pg 1 -y 270 -defaultsOSRD
preplace port VCAP_G1 -pg 1 -y 1600 -defaultsOSRD
preplace port ZORRO_READ -pg 1 -y 1300 -defaultsOSRD
preplace port ZORRO_NCFGOUT -pg 1 -y 1740 -defaultsOSRD
preplace port VCAP_B0 -pg 1 -y 1880 -defaultsOSRD
preplace port VCAP_G2 -pg 1 -y 1620 -defaultsOSRD
preplace port ZORRO_NFCS -pg 1 -y 1420 -defaultsOSRD
preplace port ZORRO_ADDRDIR -pg 1 -y 1680 -defaultsOSRD
preplace port ZORRO_INT6 -pg 1 -y 1640 -defaultsOSRD
preplace port VCAP_R0 -pg 1 -y 2040 -defaultsOSRD
preplace port VCAP_B1 -pg 1 -y 1860 -defaultsOSRD
preplace port VCAP_G3 -pg 1 -y 1640 -defaultsOSRD
preplace port ZORRO_NUDS -pg 1 -y 1320 -defaultsOSRD
preplace port VGA_DE -pg 1 -y 290 -defaultsOSRD
preplace port VCAP_R1 -pg 1 -y 2020 -defaultsOSRD
preplace port VCAP_G4 -pg 1 -y 1660 -defaultsOSRD
preplace port VCAP_B2 -pg 1 -y 1840 -defaultsOSRD
preplace port ZORRO_NDTACK -pg 1 -y 1800 -defaultsOSRD
preplace port FIXED_IO -pg 1 -y 620 -defaultsOSRD
preplace port VCAP_R2 -pg 1 -y 2000 -defaultsOSRD
preplace port VCAP_G5 -pg 1 -y 1680 -defaultsOSRD
preplace port VCAP_VSYNC -pg 1 -y 1540 -defaultsOSRD
preplace port VCAP_B3 -pg 1 -y 1820 -defaultsOSRD
preplace port ZORRO_NCINH -pg 1 -y 1780 -defaultsOSRD
preplace port ZORRO_ADDRDIR2 -pg 1 -y 1700 -defaultsOSRD
preplace port VCAP_R3 -pg 1 -y 1980 -defaultsOSRD
preplace port VCAP_B4 -pg 1 -y 1800 -defaultsOSRD
preplace port VCAP_G6 -pg 1 -y 1700 -defaultsOSRD
preplace port VCAP_R4 -pg 1 -y 1960 -defaultsOSRD
preplace port VCAP_B5 -pg 1 -y 1780 -defaultsOSRD
preplace port VCAP_G7 -pg 1 -y 1720 -defaultsOSRD
preplace port ZORRO_E7M -pg 1 -y 1500 -defaultsOSRD
preplace port ZORRO_NSLAVE -pg 1 -y 1760 -defaultsOSRD
preplace port VGA_HS -pg 1 -y 250 -defaultsOSRD
preplace port ZORRO_NBGN -pg 1 -y 1280 -defaultsOSRD
preplace port VCAP_R5 -pg 1 -y 1940 -defaultsOSRD
preplace port VCAP_B6 -pg 1 -y 1760 -defaultsOSRD
preplace port VCAP_HSYNC -pg 1 -y 1560 -defaultsOSRD
preplace port ZORRO_NCCS -pg 1 -y 1400 -defaultsOSRD
preplace port ZORRO_NDS0 -pg 1 -y 1380 -defaultsOSRD
preplace portBus VGA_B -pg 1 -y 540 -defaultsOSRD
preplace portBus ZORRO_ADDR -pg 1 -y 1600 -defaultsOSRD
preplace portBus VGA_R -pg 1 -y 340 -defaultsOSRD
preplace portBus ZORRO_DATA -pg 1 -y 1620 -defaultsOSRD
preplace portBus VGA_G -pg 1 -y 440 -defaultsOSRD
preplace inst rst_ps7_0_25M -pg 1 -lvl 4 -y 370 -defaultsOSRD
preplace inst xlslice_0 -pg 1 -lvl 7 -y 340 -defaultsOSRD
preplace inst xlslice_1 -pg 1 -lvl 7 -y 440 -defaultsOSRD
preplace inst xlslice_2 -pg 1 -lvl 7 -y 540 -defaultsOSRD
preplace inst axi_dwidth_converter_0 -pg 1 -lvl 5 -y 760 -defaultsOSRD
preplace inst axi_register_slice_0 -pg 1 -lvl 2 -y 390 -defaultsOSRD
preplace inst proc_sys_reset_0 -pg 1 -lvl 1 -y 580 -defaultsOSRD
preplace inst axi_register_slice_1 -pg 1 -lvl 5 -y 600 -defaultsOSRD
preplace inst axi_register_slice_2 -pg 1 -lvl 3 -y 560 -defaultsOSRD
preplace inst axi_protocol_convert_0 -pg 1 -lvl 5 -y 1090 -defaultsOSRD
preplace inst axi_register_slice_3 -pg 1 -lvl 4 -y 740 -defaultsOSRD
preplace inst axi_protocol_convert_1 -pg 1 -lvl 4 -y 580 -defaultsOSRD
preplace inst MNTZorro_v0_1_S00_AXI_0 -pg 1 -lvl 6 -y 1944 -defaultsOSRD
preplace inst axi_protocol_convert_2 -pg 1 -lvl 3 -y 730 -defaultsOSRD
preplace inst ps7_0_axi_periph -pg 1 -lvl 5 -y 230 -defaultsOSRD
preplace inst video -pg 1 -lvl 6 -y 322 -defaultsOSRD
preplace inst clk_wiz_0 -pg 1 -lvl 6 -y 90 -defaultsOSRD
preplace inst axi_mem_intercon -pg 1 -lvl 7 -y 1154 -defaultsOSRD
preplace inst processing_system7_0 -pg 1 -lvl 6 -y 884 -defaultsOSRD
preplace netloc xlslice_2_Dout 1 7 1 NJ
preplace netloc axi_protocol_convert_1_M_AXI 1 4 1 N
preplace netloc VCAP_R4_0_1 1 0 6 NJ 1960 NJ 1960 NJ 1960 NJ 1960 NJ 1960 1790J
preplace netloc VCAP_B2_0_1 1 0 6 NJ 1840 NJ 1840 NJ 1840 NJ 1840 NJ 1840 1850J
preplace netloc processing_system7_0_FIXED_IO 1 6 2 2850J 620 NJ
preplace netloc VCAP_VSYNC_0_1 1 0 6 NJ 1540 NJ 1540 NJ 1540 NJ 1540 NJ 1540 2020J
preplace netloc VCAP_B0_0_1 1 0 6 NJ 1880 NJ 1880 NJ 1880 NJ 1880 NJ 1880 1830J
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NCINH 1 6 2 2850J 1780 NJ
preplace netloc rst_ps7_0_25M_peripheral_aresetn 1 4 2 NJ 410 1980
preplace netloc VCAP_G6_0_1 1 0 6 NJ 1700 NJ 1700 NJ 1700 NJ 1700 NJ 1700 1920J
preplace netloc VCAP_R2_0_1 1 0 6 NJ 2000 NJ 2000 NJ 2000 NJ 2000 NJ 2000 1770J
preplace netloc VCAP_G5_0_1 1 0 6 NJ 1680 NJ 1680 NJ 1680 NJ 1680 NJ 1680 1930J
preplace netloc video_subsystem_VGA_HS 1 6 2 2720J 250 NJ
preplace netloc video_subsystem_M_AXI_MM2S 1 1 6 390 90 NJ 90 NJ 90 NJ 90 2180J 180 2710
preplace netloc axi_dwidth_converter_0_M_AXI 1 5 1 2120
preplace netloc VCAP_R5_0_1 1 0 6 NJ 1940 NJ 1940 NJ 1940 NJ 1940 NJ 1940 1800J
preplace netloc VCAP_G3_0_1 1 0 6 NJ 1640 NJ 1640 NJ 1640 NJ 1640 NJ 1640 1950J
preplace netloc VCAP_R1_0_1 1 0 6 NJ 2020 NJ 2020 NJ 2020 NJ 2020 NJ 2020 1760J
preplace netloc ZORRO_NIORST_1 1 0 6 NJ 1460 NJ 1460 NJ 1460 NJ 1460 NJ 1460 2060J
preplace netloc axi_register_slice_2_M_AXI 1 3 1 N
preplace netloc VCAP_B3_0_1 1 0 6 NJ 1820 NJ 1820 NJ 1820 NJ 1820 NJ 1820 1860J
preplace netloc ZORRO_NDS0_1 1 0 6 NJ 1380 NJ 1380 NJ 1380 NJ 1380 NJ 1380 2100J
preplace netloc ZORRO_NDS1_1 1 0 6 NJ 1360 NJ 1360 NJ 1360 NJ 1360 NJ 1360 2110J
preplace netloc video_subsystem_VGA_DE 1 6 2 2840J 280 3650J
preplace netloc VCAP_G7_0_1 1 0 6 NJ 1720 NJ 1720 NJ 1720 NJ 1720 NJ 1720 1910J
preplace netloc VCAP_HSYNC_0_1 1 0 6 NJ 1560 NJ 1560 NJ 1560 NJ 1560 NJ 1560 2010J
preplace netloc processing_system7_0_DDR 1 6 2 2840J 600 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_m00_axi 1 2 5 690 2464 NJ 2464 NJ 2464 NJ 2464 2670
preplace netloc VCAP_R3_0_1 1 0 6 NJ 1980 NJ 1980 NJ 1980 NJ 1980 NJ 1980 1780J
preplace netloc VCAP_R0_0_1 1 0 6 NJ 2040 NJ 2040 NJ 2040 NJ 2040 NJ 2040 1750J
preplace netloc ZORRO_NLDS_1 1 0 6 NJ 1340 NJ 1340 NJ 1340 NJ 1340 NJ 1340 2120J
preplace netloc axi_protocol_convert_0_M_AXI 1 5 1 2160
preplace netloc VCAP_B4_0_1 1 0 6 NJ 1800 NJ 1800 NJ 1800 NJ 1800 NJ 1800 1870J
preplace netloc ZORRO_C28D_0_1 1 0 6 NJ 1520 NJ 1520 NJ 1520 NJ 1520 NJ 1520 2030J
preplace netloc ps7_0_axi_periph_M00_AXI 1 5 1 1970
preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 7 30 480 NJ 480 650J 460 1010 472 NJ 472 NJ 472 2700
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_INT6 1 6 2 2780J 1640 NJ
preplace netloc xlslice_1_Dout 1 7 1 NJ
preplace netloc ps7_0_axi_periph_M01_AXI 1 5 1 2180
preplace netloc VCAP_G1_0_1 1 0 6 NJ 1600 NJ 1600 NJ 1600 NJ 1600 NJ 1600 1970J
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NDTACK 1 6 2 2860J 1800 NJ
preplace netloc VCAP_B5_0_1 1 0 6 NJ 1780 NJ 1780 NJ 1780 NJ 1780 NJ 1780 1880J
preplace netloc VCAP_G2_0_1 1 0 6 NJ 1620 NJ 1620 NJ 1620 NJ 1620 NJ 1620 1960J
preplace netloc video_control_vblank 1 5 2 2170 502 2710
preplace netloc xlslice_0_Dout 1 7 1 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_ADDRDIR2 1 6 2 2810J 1700 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NSLAVE 1 6 2 2840J 1760 NJ
preplace netloc ZORRO_DOE_1 1 0 6 NJ 1440 NJ 1440 NJ 1440 NJ 1440 NJ 1440 2070J
preplace netloc axi_protocol_convert_2_M_AXI 1 3 1 1010
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_DATADIR 1 6 2 2790J 1660 NJ
preplace netloc axi_register_slice_1_M_AXI 1 5 1 2130
preplace netloc Net 1 6 2 2760J 1600 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NBRN 1 6 2 2820J 1720 NJ
preplace netloc Net1 1 6 2 2770J 1620 NJ
preplace netloc processing_system7_0_FCLK_CLK0 1 0 7 20 470 390 470 670 470 1000 500 1380 500 1990 1044 2840
preplace netloc processing_system7_0_FCLK_CLK1 1 3 4 1010 270 1380 80 2140 1034 2670
preplace netloc VCAP_R7_0_1 1 0 6 NJ 1900 NJ 1900 NJ 1900 NJ 1900 NJ 1900 1820J
preplace netloc VCAP_B6_0_1 1 0 6 NJ 1760 NJ 1760 NJ 1760 NJ 1760 NJ 1760 1890J
preplace netloc axi_register_slice_0_M_AXI 1 2 1 660
preplace netloc v_axi4s_vid_out_0_vid_data 1 6 1 2850
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_ADDRDIR 1 6 2 2800J 1680 NJ
preplace netloc VCAP_G0_0_1 1 0 6 NJ 1580 NJ 1580 NJ 1580 NJ 1580 NJ 1580 1980J
preplace netloc VCAP_R6_0_1 1 0 6 NJ 1920 NJ 1920 NJ 1920 NJ 1920 NJ 1920 1810J
preplace netloc proc_sys_reset_1_peripheral_aresetn 1 1 6 400 490 680 480 990 660 1390 680 2000 1134 2850
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NCFGOUT 1 6 2 2830J 1740 NJ
preplace netloc M00_ARESETN_1 1 4 1 1390
preplace netloc ZORRO_NCFGIN_1 1 0 6 NJ 1480 NJ 1480 NJ 1480 NJ 1480 NJ 1480 2050J
preplace netloc ZORRO_NCCS_1 1 0 6 NJ 1400 NJ 1400 NJ 1400 NJ 1400 NJ 1400 2090J
preplace netloc VCAP_B7_0_1 1 0 6 NJ 1740 NJ 1740 NJ 1740 NJ 1740 NJ 1740 1900J
preplace netloc ZORRO_NBGN_0_1 1 0 6 NJ 1280 NJ 1280 NJ 1280 NJ 1280 NJ 1280 2150J
preplace netloc processing_system7_0_M_AXI_GP0 1 4 3 1410 1170 NJ 1170 2690
preplace netloc processing_system7_0_M_AXI_GP1 1 4 3 1400 1180 NJ 1180 2680
preplace netloc ZORRO_E7M_1 1 0 6 NJ 1500 NJ 1500 NJ 1500 NJ 1500 NJ 1500 2040J
preplace netloc axi_mem_intercon_M00_AXI 1 5 3 2180 734 NJ 734 3650
preplace netloc MNTZorro_v0_1_S00_AXI_0_m01_axi 1 6 1 2750
preplace netloc ZORRO_READ_1 1 0 6 NJ 1300 NJ 1300 NJ 1300 NJ 1300 NJ 1300 2140J
preplace netloc video_subsystem_VGA_VS 1 6 2 2740J 270 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_video_control_op 1 5 2 2160 492 2720
preplace netloc axi_register_slice_3_M_AXI 1 4 1 N
preplace netloc VCAP_B1_0_1 1 0 6 NJ 1860 NJ 1860 NJ 1860 NJ 1860 NJ 1860 1840J
preplace netloc MNTZorro_v0_1_S00_AXI_0_video_control_interlace 1 5 2 2180 462 2740
preplace netloc clk_1 1 5 3 2170 452 2730 80 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_video_control_data 1 5 2 2150 482 2730
preplace netloc ZORRO_NUDS_1 1 0 6 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ 1320 2130J
preplace netloc ZORRO_NFCS_1 1 0 6 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 2080J
preplace netloc VCAP_G4_0_1 1 0 6 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 1940J
levelinfo -pg 1 0 210 530 840 1200 1580 2450 3500 3670 -top 0 -bot 3270
"
}

  # Restore current instance
  current_bd_instance $oldCurInst

  validate_bd_design
  save_bd_design
  close_bd_design $design_name 
}
# End of cr_bd_zz9000_ps()
cr_bd_zz9000_ps ""
set_property REGISTERED_WITH_MANAGER "1" [get_files zz9000_ps.bd ] 
set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files zz9000_ps.bd ] 

# Create 'synth_1' run (if not found)
if {[string equal [get_runs -quiet synth_1] ""]} {
    create_run -name synth_1 -part xc7z020clg400-1 -flow {Vivado Synthesis 2018} -strategy "Flow_AreaOptimized_high" -report_strategy {No Reports} -constrset constrs_1
} else {
  set_property strategy "Flow_AreaOptimized_high" [get_runs synth_1]
  set_property flow "Vivado Synthesis 2018" [get_runs synth_1]
}
set obj [get_runs synth_1]
set_property set_report_strategy_name 1 $obj
set_property report_strategy {Vivado Synthesis Default Reports} $obj
set_property set_report_strategy_name 0 $obj
# Create 'synth_1_synth_report_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
}
set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
if { $obj != "" } {
set_property -name "display_name" -value "synth_1_synth_report_utilization_0" -objects $obj

}
set obj [get_runs synth_1]
set_property -name "part" -value "xc7z020clg400-1" -objects $obj
set_property -name "strategy" -value "Flow_AreaOptimized_high" -objects $obj
set_property -name "steps.synth_design.args.directive" -value "AreaOptimized_high" -objects $obj
set_property -name "steps.synth_design.args.control_set_opt_threshold" -value "1" -objects $obj

# set the current synth run
current_run -synthesis [get_runs synth_1]

# Create 'impl_1' run (if not found)
if {[string equal [get_runs -quiet impl_1] ""]} {
    create_run -name impl_1 -part xc7z020clg400-1 -flow {Vivado Implementation 2018} -strategy "Flow_RunPostRoutePhysOpt" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
} else {
  set_property strategy "Flow_RunPostRoutePhysOpt" [get_runs impl_1]
  set_property flow "Vivado Implementation 2018" [get_runs impl_1]
}
set obj [get_runs impl_1]
set_property set_report_strategy_name 1 $obj
set_property report_strategy {Timing Closure Reports} $obj
set_property set_report_strategy_name 0 $obj
# Create 'impl_1_opt_report_drc_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
if { $obj != "" } {
set_property -name "display_name" -value "impl_1_opt_report_drc_0" -objects $obj

}
# Create 'impl_1_opt_report_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_utilization_0] "" ] } {
  create_report_config -report_name impl_1_opt_report_utilization_0 -report_type report_utilization:1.0 -steps opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_utilization_0]
if { $obj != "" } {
set_property -name "display_name" -value "impl_1_opt_report_utilization_0" -objects $obj

}
# Create 'impl_1_opt_report_methodology_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_methodology_0] "" ] } {
  create_report_config -report_name impl_1_opt_report_methodology_0 -report_type report_methodology:1.0 -steps opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_methodology_0]
if { $obj != "" } {
set_property -name "display_name" -value "impl_1_opt_report_methodology_0" -objects $obj

}
# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "display_name" -value "impl_1_opt_report_timing_summary_0" -objects $obj

}
# Create 'impl_1_place_report_io_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
if { $obj != "" } {
set_property -name "display_name" -value "impl_1_place_report_io_0" -objects $obj

}
# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
if { $obj != "" } {
set_property -name "display_name" -value "impl_1_place_report_incremental_reuse_0" -objects $obj

}
# Create 'impl_1_place_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
if { $obj != "" } {
set_property -name "display_name" -value "impl_1_place_report_timing_summary_0" -objects $obj

}
# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "display_name" -value "impl_1_phys_opt_report_timing_summary_0" -objects $obj

}
# Create 'impl_1_phys_opt_report_design_analysis_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_design_analysis_0] "" ] } {
  create_report_config -report_name impl_1_phys_opt_report_design_analysis_0 -report_type report_design_analysis:1.0 -steps phys_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_design_analysis_0]
if { $obj != "" } {
set_property -name "display_name" -value "impl_1_phys_opt_report_design_analysis_0" -objects $obj

}
# Create 'impl_1_route_report_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_utilization_0] "" ] } {
  create_report_config -report_name impl_1_route_report_utilization_0 -report_type report_utilization:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_utilization_0]
if { $obj != "" } {
set_property -name "display_name" -value "impl_1_route_report_utilization_0" -objects $obj

}
# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
if { $obj != "" } {
set_property -name "display_name" -value "impl_1_route_report_clock_utilization_0" -objects $obj

}
# Create 'impl_1_route_report_drc_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
if { $obj != "" } {
set_property -name "display_name" -value "impl_1_route_report_drc_0" -objects $obj

}
# Create 'impl_1_route_report_power_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
if { $obj != "" } {
set_property -name "display_name" -value "impl_1_route_report_power_0" -objects $obj

}
# Create 'impl_1_route_report_route_status_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
if { $obj != "" } {
set_property -name "display_name" -value "impl_1_route_report_route_status_0" -objects $obj

}
# Create 'impl_1_route_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
if { $obj != "" } {
set_property -name "display_name" -value "impl_1_route_report_timing_summary_0" -objects $obj

}
# Create 'impl_1_route_report_design_analysis_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_design_analysis_0] "" ] } {
  create_report_config -report_name impl_1_route_report_design_analysis_0 -report_type report_design_analysis:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_design_analysis_0]
if { $obj != "" } {
set_property -name "display_name" -value "impl_1_route_report_design_analysis_0" -objects $obj

}
# Create 'impl_1_route_report_qor_suggestions_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_qor_suggestions_0] "" ] } {
  create_report_config -report_name impl_1_route_report_qor_suggestions_0 -report_type report_qor_suggestions:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_qor_suggestions_0]
if { $obj != "" } {
set_property -name "display_name" -value "impl_1_route_report_qor_suggestions_0" -objects $obj

}
# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
if { $obj != "" } {
set_property -name "display_name" -value "impl_1_route_report_incremental_reuse_0" -objects $obj

}
# Create 'impl_1_route_report_bus_skew_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
  create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
if { $obj != "" } {
set_property -name "display_name" -value "impl_1_route_report_bus_skew_0" -objects $obj

}
# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "display_name" -value "impl_1_post_route_phys_opt_report_timing_summary_0" -objects $obj

}
# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
  create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
if { $obj != "" } {
set_property -name "display_name" -value "impl_1_post_route_phys_opt_report_bus_skew_0" -objects $obj

}
set obj [get_runs impl_1]
set_property -name "part" -value "xc7z020clg400-1" -objects $obj
set_property -name "strategy" -value "Flow_RunPostRoutePhysOpt" -objects $obj
set_property -name "steps.phys_opt_design.is_enabled" -value "1" -objects $obj
set_property -name "steps.phys_opt_design.args.directive" -value "Explore" -objects $obj
set_property -name "steps.route_design.args.more options" -value "-tns_cleanup" -objects $obj
set_property -name "steps.post_route_phys_opt_design.is_enabled" -value "1" -objects $obj
set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj

# set the current impl run
current_run -implementation [get_runs impl_1]

puts "INFO: Project created:${_xil_proj_name_}"
set obj [get_dashboards default_dashboard]

# Create 'drc_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets -of_objects [get_dashboards default_dashboard] [ list "drc_1" ] ] ""]} {
create_dashboard_gadget -name {drc_1} -type drc
}
set obj [get_dashboard_gadgets -of_objects [get_dashboards default_dashboard] [ list "drc_1" ] ]
set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj

# Create 'methodology_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets -of_objects [get_dashboards default_dashboard] [ list "methodology_1" ] ] ""]} {
create_dashboard_gadget -name {methodology_1} -type methodology
}
set obj [get_dashboard_gadgets -of_objects [get_dashboards default_dashboard] [ list "methodology_1" ] ]
set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj

# Create 'power_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets -of_objects [get_dashboards default_dashboard] [ list "power_1" ] ] ""]} {
create_dashboard_gadget -name {power_1} -type power
}
set obj [get_dashboard_gadgets -of_objects [get_dashboards default_dashboard] [ list "power_1" ] ]
set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj

# Create 'timing_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets -of_objects [get_dashboards default_dashboard] [ list "timing_1" ] ] ""]} {
create_dashboard_gadget -name {timing_1} -type timing
}
set obj [get_dashboard_gadgets -of_objects [get_dashboards default_dashboard] [ list "timing_1" ] ]
set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj

# Create 'utilization_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets -of_objects [get_dashboards default_dashboard] [ list "utilization_1" ] ] ""]} {
create_dashboard_gadget -name {utilization_1} -type utilization
}
set obj [get_dashboard_gadgets -of_objects [get_dashboards default_dashboard] [ list "utilization_1" ] ]
set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
set_property -name "run.step" -value "synth_design" -objects $obj
set_property -name "run.type" -value "synthesis" -objects $obj

# Create 'utilization_2' gadget (if not found)
if {[string equal [get_dashboard_gadgets -of_objects [get_dashboards default_dashboard] [ list "utilization_2" ] ] ""]} {
create_dashboard_gadget -name {utilization_2} -type utilization
}
set obj [get_dashboard_gadgets -of_objects [get_dashboards default_dashboard] [ list "utilization_2" ] ]
set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj

move_dashboard_gadget -name {utilization_1} -row 0 -col 0
move_dashboard_gadget -name {power_1} -row 1 -col 0
move_dashboard_gadget -name {drc_1} -row 2 -col 0
move_dashboard_gadget -name {timing_1} -row 0 -col 1
move_dashboard_gadget -name {utilization_2} -row 1 -col 1
move_dashboard_gadget -name {methodology_1} -row 2 -col 1
# Set current dashboard to 'default_dashboard' 
current_dashboard default_dashboard