Firmware for MNT ZZ9000 graphics and ARM coprocessor card for Amiga computers.
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  1. #*****************************************************************************************
  2. # Vivado (TM) v2018.3 (64-bit)
  3. #
  4. # zz9000_project.tcl: Tcl script for re-creating project 'ZZ9000_proto'
  5. #
  6. # Generated by Vivado on Wed Sep 02 13:20:36 CEST 2020
  7. # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
  8. #
  9. # This file contains the Vivado Tcl commands for re-creating the project to the state*
  10. # when this script was generated. In order to re-create the project, please source this
  11. # file in the Vivado Tcl Shell.
  12. #
  13. # * Note that the runs in the created project will be configured the same way as the
  14. # original project, however they will not be launched automatically. To regenerate the
  15. # run results please launch the synthesis/implementation runs as needed.
  16. #
  17. #*****************************************************************************************
  18. # NOTE: In order to use this script for source control purposes, please make sure that the
  19. # following files are added to the source control system:-
  20. #
  21. # 1. This project restoration tcl script (zz9000_project.tcl) that was generated.
  22. #
  23. # 2. The following source(s) files that were local or imported into the original project.
  24. # (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
  25. #
  26. # "/home/mntmn/code/ZZ9000_proto/mntzorro.v"
  27. # "/home/mntmn/code/ZZ9000_proto/video_formatter.v"
  28. # "/home/mntmn/code/ZZ9000_proto/ZZ9000_proto.srcs/sources_1/bd/zz9000_ps/hdl/zz9000_ps_wrapper.v"
  29. # "/home/mntmn/code/ZZ9000_proto/ZZ9000_proto.srcs/constrs_1/new/zz9000.xdc"
  30. #
  31. # 3. The following remote source files that were added to the original project:-
  32. #
  33. # <none>
  34. #
  35. #*****************************************************************************************
  36. # Set the reference directory for source file relative paths (by default the value is script directory path)
  37. set origin_dir "."
  38. # Use origin directory path location variable, if specified in the tcl shell
  39. if { [info exists ::origin_dir_loc] } {
  40. set origin_dir $::origin_dir_loc
  41. }
  42. # Set the project name
  43. set _xil_proj_name_ "ZZ9000_proto"
  44. # Use project name variable, if specified in the tcl shell
  45. if { [info exists ::user_project_name] } {
  46. set _xil_proj_name_ $::user_project_name
  47. }
  48. variable script_file
  49. set script_file "zz9000_project.tcl"
  50. # Help information for this script
  51. proc print_help {} {
  52. variable script_file
  53. puts "\nDescription:"
  54. puts "Recreate a Vivado project from this script. The created project will be"
  55. puts "functionally equivalent to the original project for which this script was"
  56. puts "generated. The script contains commands for creating a project, filesets,"
  57. puts "runs, adding/importing sources and setting properties on various objects.\n"
  58. puts "Syntax:"
  59. puts "$script_file"
  60. puts "$script_file -tclargs \[--origin_dir <path>\]"
  61. puts "$script_file -tclargs \[--project_name <name>\]"
  62. puts "$script_file -tclargs \[--help\]\n"
  63. puts "Usage:"
  64. puts "Name Description"
  65. puts "-------------------------------------------------------------------------"
  66. puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
  67. puts " origin_dir path value is \".\", otherwise, the value"
  68. puts " that was set with the \"-paths_relative_to\" switch"
  69. puts " when this script was generated.\n"
  70. puts "\[--project_name <name>\] Create project with the specified name. Default"
  71. puts " name is the name of the project from where this"
  72. puts " script was generated.\n"
  73. puts "\[--help\] Print help information for this script"
  74. puts "-------------------------------------------------------------------------\n"
  75. exit 0
  76. }
  77. if { $::argc > 0 } {
  78. for {set i 0} {$i < $::argc} {incr i} {
  79. set option [string trim [lindex $::argv $i]]
  80. switch -regexp -- $option {
  81. "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
  82. "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
  83. "--help" { print_help }
  84. default {
  85. if { [regexp {^-} $option] } {
  86. puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
  87. return 1
  88. }
  89. }
  90. }
  91. }
  92. }
  93. # Set the directory path for the original project from where this script was exported
  94. set orig_proj_dir "[file normalize "$origin_dir/"]"
  95. # Create project
  96. create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg400-1
  97. # Set the directory path for the new project
  98. set proj_dir [get_property directory [current_project]]
  99. # Set project properties
  100. set obj [current_project]
  101. set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
  102. set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj
  103. set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj
  104. set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj
  105. set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj
  106. set_property -name "dsa.emu_dir" -value "emu" -objects $obj
  107. set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj
  108. set_property -name "dsa.flash_offset_address" -value "0" -objects $obj
  109. set_property -name "dsa.flash_size" -value "1024" -objects $obj
  110. set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj
  111. set_property -name "dsa.host_interface" -value "pcie" -objects $obj
  112. set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj
  113. set_property -name "dsa.vendor" -value "xilinx" -objects $obj
  114. set_property -name "dsa.version" -value "0.0" -objects $obj
  115. set_property -name "enable_vhdl_2008" -value "1" -objects $obj
  116. set_property -name "ip_cache_permissions" -value "read write" -objects $obj
  117. set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
  118. set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
  119. set_property -name "part" -value "xc7z020clg400-1" -objects $obj
  120. set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
  121. set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
  122. set_property -name "simulator_language" -value "Mixed" -objects $obj
  123. set_property -name "webtalk.activehdl_export_sim" -value "21" -objects $obj
  124. set_property -name "webtalk.ies_export_sim" -value "21" -objects $obj
  125. set_property -name "webtalk.modelsim_export_sim" -value "21" -objects $obj
  126. set_property -name "webtalk.questa_export_sim" -value "21" -objects $obj
  127. set_property -name "webtalk.riviera_export_sim" -value "21" -objects $obj
  128. set_property -name "webtalk.vcs_export_sim" -value "21" -objects $obj
  129. set_property -name "webtalk.xsim_export_sim" -value "21" -objects $obj
  130. set_property -name "webtalk.xsim_launch_sim" -value "38" -objects $obj
  131. set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj
  132. # Create 'sources_1' fileset (if not found)
  133. if {[string equal [get_filesets -quiet sources_1] ""]} {
  134. create_fileset -srcset sources_1
  135. }
  136. # Set IP repository paths
  137. set obj [get_filesets sources_1]
  138. set_property "ip_repo_paths" "[file normalize "$origin_dir/../ip_repo/MNTZorro_1.0"]" $obj
  139. # Rebuild user ip_repo's index before adding any source files
  140. update_ip_catalog -rebuild
  141. # Set 'sources_1' fileset object
  142. set obj [get_filesets sources_1]
  143. # Import local files from the original project
  144. set files [list \
  145. [file normalize "${origin_dir}/mntzorro.v" ]\
  146. [file normalize "${origin_dir}/video_formatter.v" ]\
  147. [file normalize "${origin_dir}/ZZ9000_proto.srcs/sources_1/bd/zz9000_ps/hdl/zz9000_ps_wrapper.v" ]\
  148. ]
  149. set imported_files [import_files -fileset sources_1 $files]
  150. # Set 'sources_1' fileset file properties for remote files
  151. # None
  152. # Set 'sources_1' fileset file properties for local files
  153. set file "mntzorro.v"
  154. set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
  155. set_property -name "path_mode" -value "RelativeOnly" -objects $file_obj
  156. # Set 'sources_1' fileset properties
  157. set obj [get_filesets sources_1]
  158. set_property -name "top" -value "zz9000_ps_wrapper" -objects $obj
  159. # Create 'constrs_1' fileset (if not found)
  160. if {[string equal [get_filesets -quiet constrs_1] ""]} {
  161. create_fileset -constrset constrs_1
  162. }
  163. # Set 'constrs_1' fileset object
  164. set obj [get_filesets constrs_1]
  165. # Add/Import constrs file and set constrs file properties
  166. set file "[file normalize "$origin_dir/ZZ9000_proto.srcs/constrs_1/new/zz9000.xdc"]"
  167. set file_imported [import_files -fileset constrs_1 [list $file]]
  168. set file "new/zz9000.xdc"
  169. set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
  170. set_property -name "file_type" -value "XDC" -objects $file_obj
  171. # Set 'constrs_1' fileset properties
  172. set obj [get_filesets constrs_1]
  173. set_property -name "target_constrs_file" -value "[get_files *new/zz9000.xdc]" -objects $obj
  174. set_property -name "target_part" -value "xc7z020clg400-1" -objects $obj
  175. set_property -name "target_ucf" -value "[get_files *new/zz9000.xdc]" -objects $obj
  176. # Create 'sim_1' fileset (if not found)
  177. if {[string equal [get_filesets -quiet sim_1] ""]} {
  178. create_fileset -simset sim_1
  179. }
  180. # Set 'sim_1' fileset object
  181. set obj [get_filesets sim_1]
  182. # Empty (no sources present)
  183. # Set 'sim_1' fileset properties
  184. set obj [get_filesets sim_1]
  185. set_property -name "nl.mode" -value "funcsim" -objects $obj
  186. set_property -name "sim_mode" -value "post-synthesis" -objects $obj
  187. set_property -name "top" -value "zz9000_ps_wrapper" -objects $obj
  188. set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
  189. set_property -name "xsim.elaborate.mt_level" -value "off" -objects $obj
  190. set_property -name "xsim.elaborate.xelab.more_options" -value "-v 1" -objects $obj
  191. # Set 'utils_1' fileset object
  192. set obj [get_filesets utils_1]
  193. # Empty (no sources present)
  194. # Set 'utils_1' fileset properties
  195. set obj [get_filesets utils_1]
  196. # Adding sources referenced in BDs, if not already added
  197. if { [get_files mntzorro.v] == "" } {
  198. import_files -quiet -fileset sources_1 mntzorro.v
  199. }
  200. if { [get_files video_formatter.v] == "" } {
  201. import_files -quiet -fileset sources_1 video_formatter.v
  202. }
  203. # Proc to create BD zz9000_ps
  204. proc cr_bd_zz9000_ps { parentCell } {
  205. # The design that will be created by this Tcl proc contains the following
  206. # module references:
  207. # MNTZorro_v0_1_S00_AXI, video_formatter
  208. # CHANGE DESIGN NAME HERE
  209. set design_name zz9000_ps
  210. common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
  211. create_bd_design $design_name
  212. set bCheckIPsPassed 1
  213. ##################################################################
  214. # CHECK IPs
  215. ##################################################################
  216. set bCheckIPs 1
  217. if { $bCheckIPs == 1 } {
  218. set list_check_ips "\
  219. xilinx.com:ip:axi_dwidth_converter:2.1\
  220. xilinx.com:ip:axi_register_slice:2.1\
  221. xilinx.com:ip:clk_wiz:6.0\
  222. xilinx.com:ip:proc_sys_reset:5.0\
  223. xilinx.com:ip:processing_system7:5.5\
  224. xilinx.com:ip:xadc_wiz:3.3\
  225. xilinx.com:ip:xlslice:1.0\
  226. xilinx.com:ip:axi_vdma:6.3\
  227. xilinx.com:ip:axis_data_fifo:2.0\
  228. "
  229. set list_ips_missing ""
  230. common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
  231. foreach ip_vlnv $list_check_ips {
  232. set ip_obj [get_ipdefs -all $ip_vlnv]
  233. if { $ip_obj eq "" } {
  234. lappend list_ips_missing $ip_vlnv
  235. }
  236. }
  237. if { $list_ips_missing ne "" } {
  238. catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
  239. set bCheckIPsPassed 0
  240. }
  241. }
  242. ##################################################################
  243. # CHECK Modules
  244. ##################################################################
  245. set bCheckModules 1
  246. if { $bCheckModules == 1 } {
  247. set list_check_mods "\
  248. MNTZorro_v0_1_S00_AXI\
  249. video_formatter\
  250. "
  251. set list_mods_missing ""
  252. common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
  253. foreach mod_vlnv $list_check_mods {
  254. if { [can_resolve_reference $mod_vlnv] == 0 } {
  255. lappend list_mods_missing $mod_vlnv
  256. }
  257. }
  258. if { $list_mods_missing ne "" } {
  259. catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
  260. common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above."
  261. set bCheckIPsPassed 0
  262. }
  263. }
  264. if { $bCheckIPsPassed != 1 } {
  265. common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
  266. return 3
  267. }
  268. # Hierarchical cell: video
  269. proc create_hier_cell_video { parentCell nameHier } {
  270. variable script_folder
  271. if { $parentCell eq "" || $nameHier eq "" } {
  272. catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_video() - Empty argument(s)!"}
  273. return
  274. }
  275. # Get object for parentCell
  276. set parentObj [get_bd_cells $parentCell]
  277. if { $parentObj == "" } {
  278. catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
  279. return
  280. }
  281. # Make sure parentObj is hier blk
  282. set parentType [get_property TYPE $parentObj]
  283. if { $parentType ne "hier" } {
  284. catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
  285. return
  286. }
  287. # Save current instance; Restore later
  288. set oldCurInst [current_bd_instance .]
  289. # Set parent object as current
  290. current_bd_instance $parentObj
  291. # Create cell and set as current instance
  292. set hier_obj [create_bd_cell -type hier $nameHier]
  293. current_bd_instance $hier_obj
  294. # Create interface pins
  295. create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_MM2S1
  296. create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_LITE
  297. # Create pins
  298. create_bd_pin -dir O VGA_DE
  299. create_bd_pin -dir O VGA_HS
  300. create_bd_pin -dir I -type clk VGA_PCLK
  301. create_bd_pin -dir O VGA_VS
  302. create_bd_pin -dir I -type rst aresetn
  303. create_bd_pin -dir I -type rst axi_resetn
  304. create_bd_pin -dir I -from 31 -to 0 control_data
  305. create_bd_pin -dir I control_interlace
  306. create_bd_pin -dir I -from 7 -to 0 control_op
  307. create_bd_pin -dir O control_vblank
  308. create_bd_pin -dir O -from 31 -to 0 dvi_rgb
  309. create_bd_pin -dir I -type clk m_axi_mm2s_aclk
  310. create_bd_pin -dir I -type clk s_axi_lite_aclk
  311. # Create instance: axi_vdma_0, and set properties
  312. set axi_vdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.3 axi_vdma_0 ]
  313. set_property -dict [ list \
  314. CONFIG.c_include_mm2s_dre {1} \
  315. CONFIG.c_include_s2mm {0} \
  316. CONFIG.c_m_axi_mm2s_data_width {32} \
  317. CONFIG.c_mm2s_genlock_mode {0} \
  318. CONFIG.c_mm2s_linebuffer_depth {2048} \
  319. CONFIG.c_mm2s_max_burst_length {128} \
  320. CONFIG.c_num_fstores {1} \
  321. CONFIG.c_s2mm_genlock_mode {0} \
  322. ] $axi_vdma_0
  323. # Create instance: axis_data_fifo_0, and set properties
  324. set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
  325. set_property -dict [ list \
  326. CONFIG.FIFO_DEPTH {32} \
  327. CONFIG.FIFO_MEMORY_TYPE {auto} \
  328. ] $axis_data_fifo_0
  329. # Create instance: video_formatter_0, and set properties
  330. set block_name video_formatter
  331. set block_cell_name video_formatter_0
  332. if { [catch {set video_formatter_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
  333. catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
  334. return 1
  335. } elseif { $video_formatter_0 eq "" } {
  336. catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
  337. return 1
  338. }
  339. # Create interface connections
  340. connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins M_AXI_MM2S1] [get_bd_intf_pins axi_vdma_0/M_AXI_MM2S]
  341. connect_bd_intf_net -intf_net axi_vdma_0_M_AXIS_MM2S [get_bd_intf_pins axi_vdma_0/M_AXIS_MM2S] [get_bd_intf_pins axis_data_fifo_0/S_AXIS]
  342. connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axis_data_fifo_0/M_AXIS] [get_bd_intf_pins video_formatter_0/m_axis_vid]
  343. connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins S_AXI_LITE] [get_bd_intf_pins axi_vdma_0/S_AXI_LITE]
  344. # Create port connections
  345. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_data [get_bd_pins control_data] [get_bd_pins video_formatter_0/control_data]
  346. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_interlace [get_bd_pins control_interlace] [get_bd_pins video_formatter_0/control_interlace]
  347. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_op [get_bd_pins control_op] [get_bd_pins video_formatter_0/control_op]
  348. connect_bd_net -net clk_1 [get_bd_pins VGA_PCLK] [get_bd_pins video_formatter_0/dvi_clk]
  349. connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins video_formatter_0/aresetn]
  350. connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins m_axi_mm2s_aclk] [get_bd_pins axi_vdma_0/m_axi_mm2s_aclk] [get_bd_pins axi_vdma_0/m_axis_mm2s_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins video_formatter_0/m_axis_vid_aclk]
  351. connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_pins s_axi_lite_aclk] [get_bd_pins axi_vdma_0/s_axi_lite_aclk]
  352. connect_bd_net -net rst_ps7_0_25M_peripheral_aresetn [get_bd_pins axi_resetn] [get_bd_pins axi_vdma_0/axi_resetn]
  353. connect_bd_net -net v_axi4s_vid_out_0_vid_data [get_bd_pins dvi_rgb] [get_bd_pins video_formatter_0/dvi_rgb]
  354. connect_bd_net -net video_formatter_0_control_vblank [get_bd_pins control_vblank] [get_bd_pins video_formatter_0/control_vblank]
  355. connect_bd_net -net video_subsystem_VGA_DE [get_bd_pins VGA_DE] [get_bd_pins video_formatter_0/dvi_active_video]
  356. connect_bd_net -net video_subsystem_VGA_HS [get_bd_pins VGA_HS] [get_bd_pins video_formatter_0/dvi_hsync]
  357. connect_bd_net -net video_subsystem_VGA_VS [get_bd_pins VGA_VS] [get_bd_pins video_formatter_0/dvi_vsync]
  358. # Restore current instance
  359. current_bd_instance $oldCurInst
  360. }
  361. variable script_folder
  362. if { $parentCell eq "" } {
  363. set parentCell [get_bd_cells /]
  364. }
  365. # Get object for parentCell
  366. set parentObj [get_bd_cells $parentCell]
  367. if { $parentObj == "" } {
  368. catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
  369. return
  370. }
  371. # Make sure parentObj is hier blk
  372. set parentType [get_property TYPE $parentObj]
  373. if { $parentType ne "hier" } {
  374. catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
  375. return
  376. }
  377. # Save current instance; Restore later
  378. set oldCurInst [current_bd_instance .]
  379. # Set parent object as current
  380. current_bd_instance $parentObj
  381. # Create interface ports
  382. set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
  383. set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
  384. # Create ports
  385. set VCAP_B0 [ create_bd_port -dir I VCAP_B0 ]
  386. set VCAP_B1 [ create_bd_port -dir I VCAP_B1 ]
  387. set VCAP_B2 [ create_bd_port -dir I VCAP_B2 ]
  388. set VCAP_B3 [ create_bd_port -dir I VCAP_B3 ]
  389. set VCAP_B4 [ create_bd_port -dir I VCAP_B4 ]
  390. set VCAP_B5 [ create_bd_port -dir I VCAP_B5 ]
  391. set VCAP_B6 [ create_bd_port -dir I VCAP_B6 ]
  392. set VCAP_B7 [ create_bd_port -dir I VCAP_B7 ]
  393. set VCAP_G0 [ create_bd_port -dir I VCAP_G0 ]
  394. set VCAP_G1 [ create_bd_port -dir I VCAP_G1 ]
  395. set VCAP_G2 [ create_bd_port -dir I VCAP_G2 ]
  396. set VCAP_G3 [ create_bd_port -dir I VCAP_G3 ]
  397. set VCAP_G4 [ create_bd_port -dir I VCAP_G4 ]
  398. set VCAP_G5 [ create_bd_port -dir I VCAP_G5 ]
  399. set VCAP_G6 [ create_bd_port -dir I VCAP_G6 ]
  400. set VCAP_G7 [ create_bd_port -dir I VCAP_G7 ]
  401. set VCAP_HSYNC [ create_bd_port -dir I VCAP_HSYNC ]
  402. set VCAP_R0 [ create_bd_port -dir I VCAP_R0 ]
  403. set VCAP_R1 [ create_bd_port -dir I VCAP_R1 ]
  404. set VCAP_R2 [ create_bd_port -dir I VCAP_R2 ]
  405. set VCAP_R3 [ create_bd_port -dir I VCAP_R3 ]
  406. set VCAP_R4 [ create_bd_port -dir I VCAP_R4 ]
  407. set VCAP_R5 [ create_bd_port -dir I VCAP_R5 ]
  408. set VCAP_R6 [ create_bd_port -dir I VCAP_R6 ]
  409. set VCAP_R7 [ create_bd_port -dir I VCAP_R7 ]
  410. set VCAP_VSYNC [ create_bd_port -dir I VCAP_VSYNC ]
  411. set VGA_B [ create_bd_port -dir O -from 7 -to 0 VGA_B ]
  412. set VGA_DE [ create_bd_port -dir O VGA_DE ]
  413. set VGA_G [ create_bd_port -dir O -from 7 -to 0 VGA_G ]
  414. set VGA_HS [ create_bd_port -dir O VGA_HS ]
  415. set VGA_PCLK [ create_bd_port -dir O -type clk VGA_PCLK ]
  416. set VGA_R [ create_bd_port -dir O -from 7 -to 0 VGA_R ]
  417. set VGA_VS [ create_bd_port -dir O VGA_VS ]
  418. set ZORRO_ADDR [ create_bd_port -dir IO -from 22 -to 0 ZORRO_ADDR ]
  419. set ZORRO_ADDRDIR [ create_bd_port -dir O ZORRO_ADDRDIR ]
  420. set ZORRO_ADDRDIR2 [ create_bd_port -dir O ZORRO_ADDRDIR2 ]
  421. set ZORRO_C28D [ create_bd_port -dir I ZORRO_C28D ]
  422. set ZORRO_DATA [ create_bd_port -dir IO -from 15 -to 0 ZORRO_DATA ]
  423. set ZORRO_DATADIR [ create_bd_port -dir O ZORRO_DATADIR ]
  424. set ZORRO_DOE [ create_bd_port -dir I ZORRO_DOE ]
  425. set ZORRO_E7M [ create_bd_port -dir I ZORRO_E7M ]
  426. set ZORRO_INT6 [ create_bd_port -dir O ZORRO_INT6 ]
  427. set ZORRO_NBGN [ create_bd_port -dir I ZORRO_NBGN ]
  428. set ZORRO_NBRN [ create_bd_port -dir O ZORRO_NBRN ]
  429. set ZORRO_NCCS [ create_bd_port -dir I ZORRO_NCCS ]
  430. set ZORRO_NCFGIN [ create_bd_port -dir I ZORRO_NCFGIN ]
  431. set ZORRO_NCFGOUT [ create_bd_port -dir O ZORRO_NCFGOUT ]
  432. set ZORRO_NCINH [ create_bd_port -dir O ZORRO_NCINH ]
  433. set ZORRO_NDS0 [ create_bd_port -dir I ZORRO_NDS0 ]
  434. set ZORRO_NDS1 [ create_bd_port -dir I ZORRO_NDS1 ]
  435. set ZORRO_NDTACK [ create_bd_port -dir O ZORRO_NDTACK ]
  436. set ZORRO_NFCS [ create_bd_port -dir I ZORRO_NFCS ]
  437. set ZORRO_NIORST [ create_bd_port -dir I ZORRO_NIORST ]
  438. set ZORRO_NLDS [ create_bd_port -dir I ZORRO_NLDS ]
  439. set ZORRO_NSLAVE [ create_bd_port -dir O ZORRO_NSLAVE ]
  440. set ZORRO_NUDS [ create_bd_port -dir I ZORRO_NUDS ]
  441. set ZORRO_READ [ create_bd_port -dir I ZORRO_READ ]
  442. # Create instance: MNTZorro_v0_1_S00_AXI_0, and set properties
  443. set block_name MNTZorro_v0_1_S00_AXI
  444. set block_cell_name MNTZorro_v0_1_S00_AXI_0
  445. if { [catch {set MNTZorro_v0_1_S00_AXI_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
  446. catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
  447. return 1
  448. } elseif { $MNTZorro_v0_1_S00_AXI_0 eq "" } {
  449. catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
  450. return 1
  451. }
  452. # Create instance: axi_dwidth_converter_0, and set properties
  453. set axi_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_0 ]
  454. # Create instance: axi_interconnect_0, and set properties
  455. set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
  456. set_property -dict [ list \
  457. CONFIG.NUM_MI {1} \
  458. CONFIG.S00_HAS_REGSLICE {3} \
  459. ] $axi_interconnect_0
  460. # Create instance: axi_interconnect_1, and set properties
  461. set axi_interconnect_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_1 ]
  462. set_property -dict [ list \
  463. CONFIG.NUM_MI {1} \
  464. CONFIG.S00_HAS_REGSLICE {4} \
  465. ] $axi_interconnect_1
  466. # Create instance: axi_interconnect_2, and set properties
  467. set axi_interconnect_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_2 ]
  468. set_property -dict [ list \
  469. CONFIG.NUM_MI {1} \
  470. CONFIG.S00_HAS_REGSLICE {3} \
  471. ] $axi_interconnect_2
  472. # Create instance: axi_register_slice_1, and set properties
  473. set axi_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_1 ]
  474. set_property -dict [ list \
  475. CONFIG.PROTOCOL {AXI3} \
  476. CONFIG.REG_AR {7} \
  477. CONFIG.REG_AW {7} \
  478. CONFIG.REG_B {7} \
  479. ] $axi_register_slice_1
  480. # Create instance: clk_wiz_0, and set properties
  481. set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
  482. set_property -dict [ list \
  483. CONFIG.CLKOUT1_DRIVES {BUFG} \
  484. CONFIG.CLKOUT1_JITTER {272.433} \
  485. CONFIG.CLKOUT1_PHASE_ERROR {261.747} \
  486. CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {75} \
  487. CONFIG.CLKOUT2_DRIVES {BUFG} \
  488. CONFIG.CLKOUT3_DRIVES {BUFG} \
  489. CONFIG.CLKOUT4_DRIVES {BUFG} \
  490. CONFIG.CLKOUT5_DRIVES {BUFG} \
  491. CONFIG.CLKOUT6_DRIVES {BUFG} \
  492. CONFIG.CLKOUT7_DRIVES {BUFG} \
  493. CONFIG.MMCM_CLKFBOUT_MULT_F {33} \
  494. CONFIG.MMCM_CLKOUT0_DIVIDE_F {11} \
  495. CONFIG.MMCM_COMPENSATION {ZHOLD} \
  496. CONFIG.MMCM_DIVCLK_DIVIDE {4} \
  497. CONFIG.PRIMITIVE {PLL} \
  498. CONFIG.PRIM_SOURCE {Single_ended_clock_capable_pin} \
  499. CONFIG.SECONDARY_SOURCE {Single_ended_clock_capable_pin} \
  500. CONFIG.USE_DYN_RECONFIG {true} \
  501. CONFIG.USE_PHASE_ALIGNMENT {false} \
  502. ] $clk_wiz_0
  503. # Create instance: proc_sys_reset_0, and set properties
  504. set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
  505. # Create instance: processing_system7_0, and set properties
  506. set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
  507. set_property -dict [ list \
  508. CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
  509. CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
  510. CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
  511. CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
  512. CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
  513. CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
  514. CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {25.000000} \
  515. CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
  516. CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
  517. CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
  518. CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {10.000000} \
  519. CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {25.000000} \
  520. CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
  521. CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
  522. CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
  523. CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
  524. CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
  525. CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
  526. CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
  527. CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
  528. CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
  529. CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
  530. CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
  531. CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
  532. CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {666.666} \
  533. CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
  534. CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
  535. CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
  536. CONFIG.PCW_CLK0_FREQ {100000000} \
  537. CONFIG.PCW_CLK1_FREQ {25000000} \
  538. CONFIG.PCW_CLK2_FREQ {10000000} \
  539. CONFIG.PCW_CLK3_FREQ {10000000} \
  540. CONFIG.PCW_CORE0_FIQ_INTR {0} \
  541. CONFIG.PCW_CORE0_IRQ_INTR {0} \
  542. CONFIG.PCW_CORE1_IRQ_INTR {0} \
  543. CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
  544. CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
  545. CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
  546. CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
  547. CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
  548. CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
  549. CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
  550. CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
  551. CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
  552. CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \
  553. CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
  554. CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
  555. CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
  556. CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
  557. CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
  558. CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
  559. CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
  560. CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
  561. CONFIG.PCW_ENET0_RESET_ENABLE {0} \
  562. CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \
  563. CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
  564. CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
  565. CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
  566. CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
  567. CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
  568. CONFIG.PCW_ENET1_RESET_ENABLE {0} \
  569. CONFIG.PCW_ENET_RESET_ENABLE {0} \
  570. CONFIG.PCW_ENET_RESET_SELECT {<Select>} \
  571. CONFIG.PCW_EN_CLK0_PORT {1} \
  572. CONFIG.PCW_EN_CLK1_PORT {1} \
  573. CONFIG.PCW_EN_DDR {1} \
  574. CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \
  575. CONFIG.PCW_EN_EMIO_ENET0 {0} \
  576. CONFIG.PCW_EN_EMIO_ENET1 {0} \
  577. CONFIG.PCW_EN_EMIO_GPIO {0} \
  578. CONFIG.PCW_EN_EMIO_I2C0 {0} \
  579. CONFIG.PCW_EN_EMIO_TTC0 {0} \
  580. CONFIG.PCW_EN_EMIO_WDT {0} \
  581. CONFIG.PCW_EN_ENET0 {1} \
  582. CONFIG.PCW_EN_ENET1 {0} \
  583. CONFIG.PCW_EN_GPIO {1} \
  584. CONFIG.PCW_EN_I2C0 {1} \
  585. CONFIG.PCW_EN_RST0_PORT {1} \
  586. CONFIG.PCW_EN_RST1_PORT {1} \
  587. CONFIG.PCW_EN_SDIO0 {1} \
  588. CONFIG.PCW_EN_TTC0 {0} \
  589. CONFIG.PCW_EN_UART1 {1} \
  590. CONFIG.PCW_EN_USB0 {1} \
  591. CONFIG.PCW_EN_WDT {0} \
  592. CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \
  593. CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
  594. CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \
  595. CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {8} \
  596. CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {5} \
  597. CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
  598. CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
  599. CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
  600. CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
  601. CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \
  602. CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \
  603. CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
  604. CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {25} \
  605. CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
  606. CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \
  607. CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
  608. CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
  609. CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \
  610. CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \
  611. CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
  612. CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
  613. CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \
  614. CONFIG.PCW_I2C0_GRP_INT_IO {<Select>} \
  615. CONFIG.PCW_I2C0_I2C0_IO {MIO 50 .. 51} \
  616. CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
  617. CONFIG.PCW_I2C0_RESET_ENABLE {0} \
  618. CONFIG.PCW_I2C0_RESET_IO {<Select>} \
  619. CONFIG.PCW_I2C1_RESET_ENABLE {0} \
  620. CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {111.111115} \
  621. CONFIG.PCW_I2C_RESET_ENABLE {0} \
  622. CONFIG.PCW_I2C_RESET_SELECT {<Select>} \
  623. CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
  624. CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
  625. CONFIG.PCW_IRQ_F2P_INTR {1} \
  626. CONFIG.PCW_MIO_0_DIRECTION {inout} \
  627. CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
  628. CONFIG.PCW_MIO_0_PULLUP {enabled} \
  629. CONFIG.PCW_MIO_0_SLEW {slow} \
  630. CONFIG.PCW_MIO_10_DIRECTION {inout} \
  631. CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
  632. CONFIG.PCW_MIO_10_PULLUP {enabled} \
  633. CONFIG.PCW_MIO_10_SLEW {slow} \
  634. CONFIG.PCW_MIO_11_DIRECTION {inout} \
  635. CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
  636. CONFIG.PCW_MIO_11_PULLUP {enabled} \
  637. CONFIG.PCW_MIO_11_SLEW {slow} \
  638. CONFIG.PCW_MIO_12_DIRECTION {inout} \
  639. CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
  640. CONFIG.PCW_MIO_12_PULLUP {enabled} \
  641. CONFIG.PCW_MIO_12_SLEW {slow} \
  642. CONFIG.PCW_MIO_13_DIRECTION {inout} \
  643. CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
  644. CONFIG.PCW_MIO_13_PULLUP {enabled} \
  645. CONFIG.PCW_MIO_13_SLEW {slow} \
  646. CONFIG.PCW_MIO_14_DIRECTION {inout} \
  647. CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
  648. CONFIG.PCW_MIO_14_PULLUP {enabled} \
  649. CONFIG.PCW_MIO_14_SLEW {slow} \
  650. CONFIG.PCW_MIO_15_DIRECTION {inout} \
  651. CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
  652. CONFIG.PCW_MIO_15_PULLUP {enabled} \
  653. CONFIG.PCW_MIO_15_SLEW {slow} \
  654. CONFIG.PCW_MIO_16_DIRECTION {out} \
  655. CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
  656. CONFIG.PCW_MIO_16_PULLUP {enabled} \
  657. CONFIG.PCW_MIO_16_SLEW {slow} \
  658. CONFIG.PCW_MIO_17_DIRECTION {out} \
  659. CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
  660. CONFIG.PCW_MIO_17_PULLUP {enabled} \
  661. CONFIG.PCW_MIO_17_SLEW {slow} \
  662. CONFIG.PCW_MIO_18_DIRECTION {out} \
  663. CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
  664. CONFIG.PCW_MIO_18_PULLUP {enabled} \
  665. CONFIG.PCW_MIO_18_SLEW {slow} \
  666. CONFIG.PCW_MIO_19_DIRECTION {out} \
  667. CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
  668. CONFIG.PCW_MIO_19_PULLUP {enabled} \
  669. CONFIG.PCW_MIO_19_SLEW {slow} \
  670. CONFIG.PCW_MIO_1_DIRECTION {inout} \
  671. CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
  672. CONFIG.PCW_MIO_1_PULLUP {enabled} \
  673. CONFIG.PCW_MIO_1_SLEW {slow} \
  674. CONFIG.PCW_MIO_20_DIRECTION {out} \
  675. CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
  676. CONFIG.PCW_MIO_20_PULLUP {enabled} \
  677. CONFIG.PCW_MIO_20_SLEW {slow} \
  678. CONFIG.PCW_MIO_21_DIRECTION {out} \
  679. CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
  680. CONFIG.PCW_MIO_21_PULLUP {enabled} \
  681. CONFIG.PCW_MIO_21_SLEW {slow} \
  682. CONFIG.PCW_MIO_22_DIRECTION {in} \
  683. CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
  684. CONFIG.PCW_MIO_22_PULLUP {enabled} \
  685. CONFIG.PCW_MIO_22_SLEW {slow} \
  686. CONFIG.PCW_MIO_23_DIRECTION {in} \
  687. CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
  688. CONFIG.PCW_MIO_23_PULLUP {enabled} \
  689. CONFIG.PCW_MIO_23_SLEW {slow} \
  690. CONFIG.PCW_MIO_24_DIRECTION {in} \
  691. CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
  692. CONFIG.PCW_MIO_24_PULLUP {enabled} \
  693. CONFIG.PCW_MIO_24_SLEW {slow} \
  694. CONFIG.PCW_MIO_25_DIRECTION {in} \
  695. CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
  696. CONFIG.PCW_MIO_25_PULLUP {enabled} \
  697. CONFIG.PCW_MIO_25_SLEW {slow} \
  698. CONFIG.PCW_MIO_26_DIRECTION {in} \
  699. CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
  700. CONFIG.PCW_MIO_26_PULLUP {enabled} \
  701. CONFIG.PCW_MIO_26_SLEW {slow} \
  702. CONFIG.PCW_MIO_27_DIRECTION {in} \
  703. CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
  704. CONFIG.PCW_MIO_27_PULLUP {enabled} \
  705. CONFIG.PCW_MIO_27_SLEW {slow} \
  706. CONFIG.PCW_MIO_28_DIRECTION {inout} \
  707. CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
  708. CONFIG.PCW_MIO_28_PULLUP {enabled} \
  709. CONFIG.PCW_MIO_28_SLEW {slow} \
  710. CONFIG.PCW_MIO_29_DIRECTION {in} \
  711. CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
  712. CONFIG.PCW_MIO_29_PULLUP {enabled} \
  713. CONFIG.PCW_MIO_29_SLEW {slow} \
  714. CONFIG.PCW_MIO_2_DIRECTION {inout} \
  715. CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
  716. CONFIG.PCW_MIO_2_PULLUP {disabled} \
  717. CONFIG.PCW_MIO_2_SLEW {slow} \
  718. CONFIG.PCW_MIO_30_DIRECTION {out} \
  719. CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
  720. CONFIG.PCW_MIO_30_PULLUP {enabled} \
  721. CONFIG.PCW_MIO_30_SLEW {slow} \
  722. CONFIG.PCW_MIO_31_DIRECTION {in} \
  723. CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
  724. CONFIG.PCW_MIO_31_PULLUP {enabled} \
  725. CONFIG.PCW_MIO_31_SLEW {slow} \
  726. CONFIG.PCW_MIO_32_DIRECTION {inout} \
  727. CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
  728. CONFIG.PCW_MIO_32_PULLUP {enabled} \
  729. CONFIG.PCW_MIO_32_SLEW {slow} \
  730. CONFIG.PCW_MIO_33_DIRECTION {inout} \
  731. CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
  732. CONFIG.PCW_MIO_33_PULLUP {enabled} \
  733. CONFIG.PCW_MIO_33_SLEW {slow} \
  734. CONFIG.PCW_MIO_34_DIRECTION {inout} \
  735. CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
  736. CONFIG.PCW_MIO_34_PULLUP {enabled} \
  737. CONFIG.PCW_MIO_34_SLEW {slow} \
  738. CONFIG.PCW_MIO_35_DIRECTION {inout} \
  739. CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
  740. CONFIG.PCW_MIO_35_PULLUP {enabled} \
  741. CONFIG.PCW_MIO_35_SLEW {slow} \
  742. CONFIG.PCW_MIO_36_DIRECTION {in} \
  743. CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
  744. CONFIG.PCW_MIO_36_PULLUP {enabled} \
  745. CONFIG.PCW_MIO_36_SLEW {slow} \
  746. CONFIG.PCW_MIO_37_DIRECTION {inout} \
  747. CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
  748. CONFIG.PCW_MIO_37_PULLUP {enabled} \
  749. CONFIG.PCW_MIO_37_SLEW {slow} \
  750. CONFIG.PCW_MIO_38_DIRECTION {inout} \
  751. CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
  752. CONFIG.PCW_MIO_38_PULLUP {enabled} \
  753. CONFIG.PCW_MIO_38_SLEW {slow} \
  754. CONFIG.PCW_MIO_39_DIRECTION {inout} \
  755. CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
  756. CONFIG.PCW_MIO_39_PULLUP {enabled} \
  757. CONFIG.PCW_MIO_39_SLEW {slow} \
  758. CONFIG.PCW_MIO_3_DIRECTION {inout} \
  759. CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
  760. CONFIG.PCW_MIO_3_PULLUP {disabled} \
  761. CONFIG.PCW_MIO_3_SLEW {slow} \
  762. CONFIG.PCW_MIO_40_DIRECTION {inout} \
  763. CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
  764. CONFIG.PCW_MIO_40_PULLUP {enabled} \
  765. CONFIG.PCW_MIO_40_SLEW {slow} \
  766. CONFIG.PCW_MIO_41_DIRECTION {inout} \
  767. CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
  768. CONFIG.PCW_MIO_41_PULLUP {enabled} \
  769. CONFIG.PCW_MIO_41_SLEW {slow} \
  770. CONFIG.PCW_MIO_42_DIRECTION {inout} \
  771. CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
  772. CONFIG.PCW_MIO_42_PULLUP {enabled} \
  773. CONFIG.PCW_MIO_42_SLEW {slow} \
  774. CONFIG.PCW_MIO_43_DIRECTION {inout} \
  775. CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
  776. CONFIG.PCW_MIO_43_PULLUP {enabled} \
  777. CONFIG.PCW_MIO_43_SLEW {slow} \
  778. CONFIG.PCW_MIO_44_DIRECTION {inout} \
  779. CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
  780. CONFIG.PCW_MIO_44_PULLUP {enabled} \
  781. CONFIG.PCW_MIO_44_SLEW {slow} \
  782. CONFIG.PCW_MIO_45_DIRECTION {inout} \
  783. CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
  784. CONFIG.PCW_MIO_45_PULLUP {enabled} \
  785. CONFIG.PCW_MIO_45_SLEW {slow} \
  786. CONFIG.PCW_MIO_46_DIRECTION {inout} \
  787. CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
  788. CONFIG.PCW_MIO_46_PULLUP {enabled} \
  789. CONFIG.PCW_MIO_46_SLEW {slow} \
  790. CONFIG.PCW_MIO_47_DIRECTION {inout} \
  791. CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
  792. CONFIG.PCW_MIO_47_PULLUP {enabled} \
  793. CONFIG.PCW_MIO_47_SLEW {slow} \
  794. CONFIG.PCW_MIO_48_DIRECTION {out} \
  795. CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
  796. CONFIG.PCW_MIO_48_PULLUP {enabled} \
  797. CONFIG.PCW_MIO_48_SLEW {slow} \
  798. CONFIG.PCW_MIO_49_DIRECTION {in} \
  799. CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
  800. CONFIG.PCW_MIO_49_PULLUP {enabled} \
  801. CONFIG.PCW_MIO_49_SLEW {slow} \
  802. CONFIG.PCW_MIO_4_DIRECTION {inout} \
  803. CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
  804. CONFIG.PCW_MIO_4_PULLUP {disabled} \
  805. CONFIG.PCW_MIO_4_SLEW {slow} \
  806. CONFIG.PCW_MIO_50_DIRECTION {inout} \
  807. CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
  808. CONFIG.PCW_MIO_50_PULLUP {enabled} \
  809. CONFIG.PCW_MIO_50_SLEW {slow} \
  810. CONFIG.PCW_MIO_51_DIRECTION {inout} \
  811. CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
  812. CONFIG.PCW_MIO_51_PULLUP {enabled} \
  813. CONFIG.PCW_MIO_51_SLEW {slow} \
  814. CONFIG.PCW_MIO_52_DIRECTION {out} \
  815. CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
  816. CONFIG.PCW_MIO_52_PULLUP {enabled} \
  817. CONFIG.PCW_MIO_52_SLEW {slow} \
  818. CONFIG.PCW_MIO_53_DIRECTION {inout} \
  819. CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
  820. CONFIG.PCW_MIO_53_PULLUP {enabled} \
  821. CONFIG.PCW_MIO_53_SLEW {slow} \
  822. CONFIG.PCW_MIO_5_DIRECTION {inout} \
  823. CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
  824. CONFIG.PCW_MIO_5_PULLUP {disabled} \
  825. CONFIG.PCW_MIO_5_SLEW {slow} \
  826. CONFIG.PCW_MIO_6_DIRECTION {inout} \
  827. CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
  828. CONFIG.PCW_MIO_6_PULLUP {disabled} \
  829. CONFIG.PCW_MIO_6_SLEW {slow} \
  830. CONFIG.PCW_MIO_7_DIRECTION {out} \
  831. CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
  832. CONFIG.PCW_MIO_7_PULLUP {disabled} \
  833. CONFIG.PCW_MIO_7_SLEW {slow} \
  834. CONFIG.PCW_MIO_8_DIRECTION {out} \
  835. CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
  836. CONFIG.PCW_MIO_8_PULLUP {disabled} \
  837. CONFIG.PCW_MIO_8_SLEW {slow} \
  838. CONFIG.PCW_MIO_9_DIRECTION {inout} \
  839. CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
  840. CONFIG.PCW_MIO_9_PULLUP {enabled} \
  841. CONFIG.PCW_MIO_9_SLEW {slow} \
  842. CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO#GPIO#UART 1#UART 1#I2C 0#I2C 0#Enet 0#Enet 0} \
  843. CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#gpio[1]#gpio[2]#gpio[3]#gpio[4]#gpio[5]#gpio[6]#gpio[7]#gpio[8]#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#gpio[46]#gpio[47]#tx#rx#scl#sda#mdc#mdio} \
  844. CONFIG.PCW_P2F_ENET0_INTR {0} \
  845. CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
  846. CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
  847. CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {1} \
  848. CONFIG.PCW_SD0_GRP_CD_ENABLE {0} \
  849. CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
  850. CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
  851. CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
  852. CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
  853. CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
  854. CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {40} \
  855. CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {25} \
  856. CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
  857. CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
  858. CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
  859. CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {32} \
  860. CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {32} \
  861. CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
  862. CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
  863. CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
  864. CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
  865. CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0} \
  866. CONFIG.PCW_TTC0_TTC0_IO {<Select>} \
  867. CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \
  868. CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
  869. CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
  870. CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
  871. CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
  872. CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
  873. CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
  874. CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
  875. CONFIG.PCW_UIPARAM_DDR_AL {0} \
  876. CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
  877. CONFIG.PCW_UIPARAM_DDR_BL {8} \
  878. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.271} \
  879. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.259} \
  880. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.219} \
  881. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.207} \
  882. CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} \
  883. CONFIG.PCW_UIPARAM_DDR_CL {7} \
  884. CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
  885. CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
  886. CONFIG.PCW_UIPARAM_DDR_CWL {6} \
  887. CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
  888. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.229} \
  889. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.250} \
  890. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.121} \
  891. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.146} \
  892. CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
  893. CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
  894. CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
  895. CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333} \
  896. CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
  897. CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \
  898. CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \
  899. CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
  900. CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
  901. CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
  902. CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
  903. CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
  904. CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
  905. CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
  906. CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \
  907. CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
  908. CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
  909. CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
  910. CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
  911. CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
  912. CONFIG.PCW_USB0_RESET_ENABLE {0} \
  913. CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
  914. CONFIG.PCW_USB1_RESET_ENABLE {0} \
  915. CONFIG.PCW_USB_RESET_ENABLE {0} \
  916. CONFIG.PCW_USE_AXI_NONSECURE {0} \
  917. CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {1} \
  918. CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
  919. CONFIG.PCW_USE_M_AXI_GP0 {1} \
  920. CONFIG.PCW_USE_M_AXI_GP1 {1} \
  921. CONFIG.PCW_USE_S_AXI_ACP {1} \
  922. CONFIG.PCW_USE_S_AXI_GP0 {0} \
  923. CONFIG.PCW_USE_S_AXI_HP0 {1} \
  924. CONFIG.PCW_USE_S_AXI_HP1 {1} \
  925. CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \
  926. CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \
  927. CONFIG.PCW_WDT_WDT_IO {<Select>} \
  928. ] $processing_system7_0
  929. # Create instance: ps7_0_axi_periph, and set properties
  930. set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
  931. set_property -dict [ list \
  932. CONFIG.M00_HAS_DATA_FIFO {0} \
  933. CONFIG.M00_HAS_REGSLICE {3} \
  934. CONFIG.M01_HAS_DATA_FIFO {0} \
  935. CONFIG.M01_HAS_REGSLICE {3} \
  936. CONFIG.NUM_MI {3} \
  937. CONFIG.S00_HAS_DATA_FIFO {0} \
  938. CONFIG.S00_HAS_REGSLICE {3} \
  939. ] $ps7_0_axi_periph
  940. # Create instance: rst_ps7_0_25M, and set properties
  941. set rst_ps7_0_25M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_25M ]
  942. set_property -dict [ list \
  943. CONFIG.C_NUM_INTERCONNECT_ARESETN {1} \
  944. CONFIG.C_NUM_PERP_ARESETN {1} \
  945. ] $rst_ps7_0_25M
  946. # Create instance: video
  947. create_hier_cell_video [current_bd_instance .] video
  948. # Create instance: xadc_wiz_0, and set properties
  949. set xadc_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.3 xadc_wiz_0 ]
  950. set_property -dict [ list \
  951. CONFIG.AVERAGE_ENABLE_TEMPERATURE {true} \
  952. CONFIG.AVERAGE_ENABLE_VBRAM {true} \
  953. CONFIG.AVERAGE_ENABLE_VCCAUX {true} \
  954. CONFIG.AVERAGE_ENABLE_VCCDDRO {true} \
  955. CONFIG.AVERAGE_ENABLE_VCCINT {true} \
  956. CONFIG.AVERAGE_ENABLE_VCCPAUX {true} \
  957. CONFIG.AVERAGE_ENABLE_VCCPINT {true} \
  958. CONFIG.CHANNEL_ENABLE_TEMPERATURE {true} \
  959. CONFIG.CHANNEL_ENABLE_VBRAM {true} \
  960. CONFIG.CHANNEL_ENABLE_VCCAUX {true} \
  961. CONFIG.CHANNEL_ENABLE_VCCDDRO {true} \
  962. CONFIG.CHANNEL_ENABLE_VCCINT {true} \
  963. CONFIG.CHANNEL_ENABLE_VCCPAUX {true} \
  964. CONFIG.CHANNEL_ENABLE_VCCPINT {true} \
  965. CONFIG.CHANNEL_ENABLE_VP_VN {false} \
  966. CONFIG.ENABLE_VCCDDRO_ALARM {false} \
  967. CONFIG.ENABLE_VCCPAUX_ALARM {false} \
  968. CONFIG.ENABLE_VCCPINT_ALARM {false} \
  969. CONFIG.EXTERNAL_MUX_CHANNEL {VP_VN} \
  970. CONFIG.SEQUENCER_MODE {Off} \
  971. CONFIG.SINGLE_CHANNEL_SELECTION {TEMPERATURE} \
  972. CONFIG.TEMPERATURE_ALARM_OT_TRIGGER {80} \
  973. CONFIG.TEMPERATURE_ALARM_TRIGGER {85.0} \
  974. CONFIG.TIMING_MODE {Continuous} \
  975. CONFIG.USER_TEMP_ALARM {false} \
  976. CONFIG.VCCAUX_ALARM {false} \
  977. CONFIG.VCCINT_ALARM {false} \
  978. CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} \
  979. ] $xadc_wiz_0
  980. # Create instance: xlslice_0, and set properties
  981. set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ]
  982. set_property -dict [ list \
  983. CONFIG.DIN_FROM {23} \
  984. CONFIG.DIN_TO {16} \
  985. CONFIG.DIN_WIDTH {32} \
  986. CONFIG.DOUT_WIDTH {8} \
  987. ] $xlslice_0
  988. # Create instance: xlslice_1, and set properties
  989. set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ]
  990. set_property -dict [ list \
  991. CONFIG.DIN_FROM {15} \
  992. CONFIG.DIN_TO {8} \
  993. CONFIG.DIN_WIDTH {32} \
  994. CONFIG.DOUT_WIDTH {8} \
  995. ] $xlslice_1
  996. # Create instance: xlslice_2, and set properties
  997. set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ]
  998. set_property -dict [ list \
  999. CONFIG.DIN_FROM {7} \
  1000. CONFIG.DIN_TO {0} \
  1001. CONFIG.DIN_WIDTH {32} \
  1002. CONFIG.DOUT_WIDTH {8} \
  1003. ] $xlslice_2
  1004. # Create interface connections
  1005. connect_bd_intf_net -intf_net MNTZorro_v0_1_S00_AXI_0_m00_axi [get_bd_intf_pins MNTZorro_v0_1_S00_AXI_0/m00_axi] [get_bd_intf_pins axi_dwidth_converter_0/S_AXI]
  1006. connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
  1007. connect_bd_intf_net -intf_net S00_AXI_2 [get_bd_intf_pins processing_system7_0/M_AXI_GP1] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
  1008. connect_bd_intf_net -intf_net S00_AXI_3 [get_bd_intf_pins axi_interconnect_1/S00_AXI] [get_bd_intf_pins video/M_AXI_MM2S1]
  1009. connect_bd_intf_net -intf_net S00_AXI_4 [get_bd_intf_pins MNTZorro_v0_1_S00_AXI_0/m01_axi] [get_bd_intf_pins axi_interconnect_2/S00_AXI]
  1010. connect_bd_intf_net -intf_net axi_dwidth_converter_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/M_AXI] [get_bd_intf_pins axi_register_slice_1/S_AXI]
  1011. connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins MNTZorro_v0_1_S00_AXI_0/S_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
  1012. connect_bd_intf_net -intf_net axi_interconnect_1_M00_AXI [get_bd_intf_pins axi_interconnect_1/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0]
  1013. connect_bd_intf_net -intf_net axi_interconnect_2_M00_AXI [get_bd_intf_pins axi_interconnect_2/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP1]
  1014. connect_bd_intf_net -intf_net axi_register_slice_1_M_AXI [get_bd_intf_pins axi_register_slice_1/M_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_ACP]
  1015. connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
  1016. connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
  1017. connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins clk_wiz_0/s_axi_lite] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI]
  1018. connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] [get_bd_intf_pins video/S_AXI_LITE]
  1019. connect_bd_intf_net -intf_net ps7_0_axi_periph_M02_AXI [get_bd_intf_pins ps7_0_axi_periph/M02_AXI] [get_bd_intf_pins xadc_wiz_0/s_axi_lite]
  1020. # Create port connections
  1021. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_ADDRDIR [get_bd_ports ZORRO_ADDRDIR] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_ADDRDIR]
  1022. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_ADDRDIR2 [get_bd_ports ZORRO_ADDRDIR2] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_ADDRDIR2]
  1023. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_DATADIR [get_bd_ports ZORRO_DATADIR] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_DATADIR]
  1024. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_INT6 [get_bd_ports ZORRO_INT6] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_INT6]
  1025. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_NBRN [get_bd_ports ZORRO_NBRN] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NBRN]
  1026. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_NCFGOUT [get_bd_ports ZORRO_NCFGOUT] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NCFGOUT]
  1027. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_NCINH [get_bd_ports ZORRO_NCINH] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NCINH]
  1028. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_NDTACK [get_bd_ports ZORRO_NDTACK] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NDTACK]
  1029. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_NSLAVE [get_bd_ports ZORRO_NSLAVE] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NSLAVE]
  1030. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_arm_interrupt [get_bd_pins MNTZorro_v0_1_S00_AXI_0/arm_interrupt] [get_bd_pins processing_system7_0/IRQ_F2P]
  1031. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_data [get_bd_pins MNTZorro_v0_1_S00_AXI_0/video_control_data_out] [get_bd_pins video/control_data]
  1032. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_interlace [get_bd_pins MNTZorro_v0_1_S00_AXI_0/video_control_interlace_out] [get_bd_pins video/control_interlace]
  1033. connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_op [get_bd_pins MNTZorro_v0_1_S00_AXI_0/video_control_op_out] [get_bd_pins video/control_op]
  1034. connect_bd_net -net Net [get_bd_ports ZORRO_ADDR] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_ADDR]
  1035. connect_bd_net -net Net1 [get_bd_ports ZORRO_DATA] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_DATA]
  1036. connect_bd_net -net S00_ACLK_1 [get_bd_pins clk_wiz_0/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK1] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_25M/slowest_sync_clk] [get_bd_pins video/s_axi_lite_aclk] [get_bd_pins xadc_wiz_0/s_axi_aclk]
  1037. connect_bd_net -net VCAP_B0_0_1 [get_bd_ports VCAP_B0] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B0]
  1038. connect_bd_net -net VCAP_B1_0_1 [get_bd_ports VCAP_B1] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B1]
  1039. connect_bd_net -net VCAP_B2_0_1 [get_bd_ports VCAP_B2] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B2]
  1040. connect_bd_net -net VCAP_B3_0_1 [get_bd_ports VCAP_B3] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B3]
  1041. connect_bd_net -net VCAP_B4_0_1 [get_bd_ports VCAP_B4] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B4]
  1042. connect_bd_net -net VCAP_B5_0_1 [get_bd_ports VCAP_B5] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B5]
  1043. connect_bd_net -net VCAP_B6_0_1 [get_bd_ports VCAP_B6] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B6]
  1044. connect_bd_net -net VCAP_B7_0_1 [get_bd_ports VCAP_B7] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B7]
  1045. connect_bd_net -net VCAP_G0_0_1 [get_bd_ports VCAP_G0] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_G0]
  1046. connect_bd_net -net VCAP_G1_0_1 [get_bd_ports VCAP_G1] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_G1]
  1047. connect_bd_net -net VCAP_G2_0_1 [get_bd_ports VCAP_G2] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_G2]
  1048. connect_bd_net -net VCAP_G3_0_1 [get_bd_ports VCAP_G3] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_G3]
  1049. connect_bd_net -net VCAP_G4_0_1 [get_bd_ports VCAP_G4] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_G4]
  1050. connect_bd_net -net VCAP_G5_0_1 [get_bd_ports VCAP_G5] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_G5]
  1051. connect_bd_net -net VCAP_G6_0_1 [get_bd_ports VCAP_G6] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_G6]
  1052. connect_bd_net -net VCAP_G7_0_1 [get_bd_ports VCAP_G7] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_G7]
  1053. connect_bd_net -net VCAP_HSYNC_0_1 [get_bd_ports VCAP_HSYNC] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_HSYNC]
  1054. connect_bd_net -net VCAP_R0_0_1 [get_bd_ports VCAP_R0] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_R0]
  1055. connect_bd_net -net VCAP_R1_0_1 [get_bd_ports VCAP_R1] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_R1]
  1056. connect_bd_net -net VCAP_R2_0_1 [get_bd_ports VCAP_R2] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_R2]
  1057. connect_bd_net -net VCAP_R3_0_1 [get_bd_ports VCAP_R3] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_R3]
  1058. connect_bd_net -net VCAP_R4_0_1 [get_bd_ports VCAP_R4] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_R4]
  1059. connect_bd_net -net VCAP_R5_0_1 [get_bd_ports VCAP_R5] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_R5]
  1060. connect_bd_net -net VCAP_R6_0_1 [get_bd_ports VCAP_R6] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_R6]
  1061. connect_bd_net -net VCAP_R7_0_1 [get_bd_ports VCAP_R7] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_R7]
  1062. connect_bd_net -net VCAP_VSYNC_0_1 [get_bd_ports VCAP_VSYNC] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_VSYNC]
  1063. connect_bd_net -net ZORRO_C28D_0_1 [get_bd_ports ZORRO_C28D] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_C28D]
  1064. connect_bd_net -net ZORRO_DOE_1 [get_bd_ports ZORRO_DOE] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_DOE]
  1065. connect_bd_net -net ZORRO_E7M_1 [get_bd_ports ZORRO_E7M] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_E7M]
  1066. connect_bd_net -net ZORRO_NBGN_0_1 [get_bd_ports ZORRO_NBGN] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NBGN]
  1067. connect_bd_net -net ZORRO_NCCS_1 [get_bd_ports ZORRO_NCCS] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NCCS]
  1068. connect_bd_net -net ZORRO_NCFGIN_1 [get_bd_ports ZORRO_NCFGIN] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NCFGIN]
  1069. connect_bd_net -net ZORRO_NDS0_1 [get_bd_ports ZORRO_NDS0] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NDS0]
  1070. connect_bd_net -net ZORRO_NDS1_1 [get_bd_ports ZORRO_NDS1] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NDS1]
  1071. connect_bd_net -net ZORRO_NFCS_1 [get_bd_ports ZORRO_NFCS] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NFCS]
  1072. connect_bd_net -net ZORRO_NIORST_1 [get_bd_ports ZORRO_NIORST] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NIORST]
  1073. connect_bd_net -net ZORRO_NLDS_1 [get_bd_ports ZORRO_NLDS] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NLDS]
  1074. connect_bd_net -net ZORRO_NUDS_1 [get_bd_ports ZORRO_NUDS] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NUDS]
  1075. connect_bd_net -net ZORRO_READ_1 [get_bd_ports ZORRO_READ] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_READ]
  1076. connect_bd_net -net clk_1 [get_bd_ports VGA_PCLK] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins video/VGA_PCLK]
  1077. connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins MNTZorro_v0_1_S00_AXI_0/S_AXI_ARESETN] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/m00_axi_aresetn] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/m01_axi_aresetn] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_1/ARESETN] [get_bd_pins axi_interconnect_1/M00_ARESETN] [get_bd_pins axi_interconnect_1/S00_ARESETN] [get_bd_pins axi_interconnect_2/ARESETN] [get_bd_pins axi_interconnect_2/M00_ARESETN] [get_bd_pins axi_interconnect_2/S00_ARESETN] [get_bd_pins axi_register_slice_1/aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins video/aresetn]
  1078. connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins MNTZorro_v0_1_S00_AXI_0/S_AXI_ACLK] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/m00_axi_aclk] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/m01_axi_aclk] [get_bd_pins axi_dwidth_converter_0/s_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_1/ACLK] [get_bd_pins axi_interconnect_1/M00_ACLK] [get_bd_pins axi_interconnect_1/S00_ACLK] [get_bd_pins axi_interconnect_2/ACLK] [get_bd_pins axi_interconnect_2/M00_ACLK] [get_bd_pins axi_interconnect_2/S00_ACLK] [get_bd_pins axi_register_slice_1/aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_ACP_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins video/m_axi_mm2s_aclk]
  1079. connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N]
  1080. connect_bd_net -net processing_system7_0_FCLK_RESET1_N [get_bd_pins processing_system7_0/FCLK_RESET1_N] [get_bd_pins rst_ps7_0_25M/ext_reset_in]
  1081. connect_bd_net -net rst_ps7_0_25M_peripheral_aresetn [get_bd_pins clk_wiz_0/s_axi_aresetn] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_25M/peripheral_aresetn] [get_bd_pins video/axi_resetn] [get_bd_pins xadc_wiz_0/s_axi_aresetn]
  1082. connect_bd_net -net v_axi4s_vid_out_0_vid_data [get_bd_pins video/dvi_rgb] [get_bd_pins xlslice_0/Din] [get_bd_pins xlslice_1/Din] [get_bd_pins xlslice_2/Din]
  1083. connect_bd_net -net video_control_vblank [get_bd_pins MNTZorro_v0_1_S00_AXI_0/video_control_vblank_in] [get_bd_pins video/control_vblank]
  1084. connect_bd_net -net video_subsystem_VGA_DE [get_bd_ports VGA_DE] [get_bd_pins video/VGA_DE]
  1085. connect_bd_net -net video_subsystem_VGA_HS [get_bd_ports VGA_HS] [get_bd_pins video/VGA_HS]
  1086. connect_bd_net -net video_subsystem_VGA_VS [get_bd_ports VGA_VS] [get_bd_pins video/VGA_VS]
  1087. connect_bd_net -net xlslice_0_Dout [get_bd_ports VGA_R] [get_bd_pins xlslice_0/Dout]
  1088. connect_bd_net -net xlslice_1_Dout [get_bd_ports VGA_G] [get_bd_pins xlslice_1/Dout]
  1089. connect_bd_net -net xlslice_2_Dout [get_bd_ports VGA_B] [get_bd_pins xlslice_2/Dout]
  1090. # Create address segments
  1091. create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces MNTZorro_v0_1_S00_AXI_0/m00_axi] [get_bd_addr_segs processing_system7_0/S_AXI_ACP/ACP_DDR_LOWOCM] SEG_processing_system7_0_ACP_DDR_LOWOCM
  1092. create_bd_addr_seg -range 0x00400000 -offset 0xE0000000 [get_bd_addr_spaces MNTZorro_v0_1_S00_AXI_0/m00_axi] [get_bd_addr_segs processing_system7_0/S_AXI_ACP/ACP_IOP] SEG_processing_system7_0_ACP_IOP
  1093. create_bd_addr_seg -range 0x40000000 -offset 0x40000000 [get_bd_addr_spaces MNTZorro_v0_1_S00_AXI_0/m00_axi] [get_bd_addr_segs processing_system7_0/S_AXI_ACP/ACP_M_AXI_GP0] SEG_processing_system7_0_ACP_M_AXI_GP0
  1094. create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces MNTZorro_v0_1_S00_AXI_0/m00_axi] [get_bd_addr_segs processing_system7_0/S_AXI_ACP/ACP_M_AXI_GP1] SEG_processing_system7_0_ACP_M_AXI_GP1
  1095. create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces MNTZorro_v0_1_S00_AXI_0/m01_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
  1096. create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs MNTZorro_v0_1_S00_AXI_0/S_AXI/reg0] SEG_MNTZorro_v0_1_S00_AXI_0_reg0
  1097. create_bd_addr_seg -range 0x00010000 -offset 0x83000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs video/axi_vdma_0/S_AXI_LITE/Reg] SEG_axi_vdma_0_Reg
  1098. create_bd_addr_seg -range 0x00010000 -offset 0x83C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs clk_wiz_0/s_axi_lite/Reg] SEG_clk_wiz_0_Reg
  1099. create_bd_addr_seg -range 0x00010000 -offset 0x83C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs xadc_wiz_0/s_axi_lite/Reg] SEG_xadc_wiz_0_Reg
  1100. create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces video/axi_vdma_0/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM
  1101. # Perform GUI Layout
  1102. regenerate_bd_layout -layout_string {
  1103. "ExpandedHierarchyInLayout":"",
  1104. "guistr":"# # String gsaved with Nlview 6.8.11 2018-08-07 bk=1.4403 VDI=40 GEI=35 GUI=JA:9.0 TLS
  1105. # -string -flagsOSRD
  1106. preplace port ZORRO_C28D -pg 1 -y 1550 -defaultsOSRD
  1107. preplace port VCAP_B7 -pg 1 -y 1770 -defaultsOSRD
  1108. preplace port VCAP_R6 -pg 1 -y 1950 -defaultsOSRD
  1109. preplace port ZORRO_NIORST -pg 1 -y 1490 -defaultsOSRD
  1110. preplace port ZORRO_NDS1 -pg 1 -y 1390 -defaultsOSRD
  1111. preplace port ZORRO_NLDS -pg 1 -y 1370 -defaultsOSRD
  1112. preplace port DDR -pg 1 -y 410 -defaultsOSRD
  1113. preplace port VCAP_R7 -pg 1 -y 1930 -defaultsOSRD
  1114. preplace port ZORRO_DATADIR -pg 1 -y 1890 -defaultsOSRD
  1115. preplace port ZORRO_NCFGIN -pg 1 -y 1510 -defaultsOSRD
  1116. preplace port ZORRO_DOE -pg 1 -y 1470 -defaultsOSRD
  1117. preplace port VGA_PCLK -pg 1 -y 770 -defaultsOSRD
  1118. preplace port ZORRO_NBRN -pg 1 -y 1950 -defaultsOSRD
  1119. preplace port VCAP_G0 -pg 1 -y 1610 -defaultsOSRD
  1120. preplace port VGA_VS -pg 1 -y 1110 -defaultsOSRD
  1121. preplace port VCAP_G1 -pg 1 -y 1630 -defaultsOSRD
  1122. preplace port ZORRO_READ -pg 1 -y 1330 -defaultsOSRD
  1123. preplace port ZORRO_NCFGOUT -pg 1 -y 1970 -defaultsOSRD
  1124. preplace port VCAP_B0 -pg 1 -y 1910 -defaultsOSRD
  1125. preplace port VCAP_G2 -pg 1 -y 1650 -defaultsOSRD
  1126. preplace port ZORRO_NFCS -pg 1 -y 1450 -defaultsOSRD
  1127. preplace port ZORRO_ADDRDIR -pg 1 -y 1910 -defaultsOSRD
  1128. preplace port ZORRO_INT6 -pg 1 -y 1870 -defaultsOSRD
  1129. preplace port VCAP_R0 -pg 1 -y 2070 -defaultsOSRD
  1130. preplace port VCAP_B1 -pg 1 -y 1890 -defaultsOSRD
  1131. preplace port VCAP_G3 -pg 1 -y 1670 -defaultsOSRD
  1132. preplace port ZORRO_NUDS -pg 1 -y 1350 -defaultsOSRD
  1133. preplace port VGA_DE -pg 1 -y 1130 -defaultsOSRD
  1134. preplace port VCAP_R1 -pg 1 -y 2050 -defaultsOSRD
  1135. preplace port VCAP_G4 -pg 1 -y 1690 -defaultsOSRD
  1136. preplace port VCAP_B2 -pg 1 -y 1870 -defaultsOSRD
  1137. preplace port ZORRO_NDTACK -pg 1 -y 2030 -defaultsOSRD
  1138. preplace port FIXED_IO -pg 1 -y 430 -defaultsOSRD
  1139. preplace port VCAP_R2 -pg 1 -y 2030 -defaultsOSRD
  1140. preplace port VCAP_G5 -pg 1 -y 1710 -defaultsOSRD
  1141. preplace port VCAP_VSYNC -pg 1 -y 1570 -defaultsOSRD
  1142. preplace port VCAP_B3 -pg 1 -y 1850 -defaultsOSRD
  1143. preplace port ZORRO_NCINH -pg 1 -y 2010 -defaultsOSRD
  1144. preplace port ZORRO_ADDRDIR2 -pg 1 -y 1930 -defaultsOSRD
  1145. preplace port VCAP_R3 -pg 1 -y 2010 -defaultsOSRD
  1146. preplace port VCAP_B4 -pg 1 -y 1830 -defaultsOSRD
  1147. preplace port VCAP_G6 -pg 1 -y 1730 -defaultsOSRD
  1148. preplace port VCAP_R4 -pg 1 -y 1990 -defaultsOSRD
  1149. preplace port VCAP_B5 -pg 1 -y 1810 -defaultsOSRD
  1150. preplace port VCAP_G7 -pg 1 -y 1750 -defaultsOSRD
  1151. preplace port ZORRO_E7M -pg 1 -y 1530 -defaultsOSRD
  1152. preplace port ZORRO_NSLAVE -pg 1 -y 1990 -defaultsOSRD
  1153. preplace port VGA_HS -pg 1 -y 1090 -defaultsOSRD
  1154. preplace port ZORRO_NBGN -pg 1 -y 1310 -defaultsOSRD
  1155. preplace port VCAP_R5 -pg 1 -y 1970 -defaultsOSRD
  1156. preplace port VCAP_B6 -pg 1 -y 1790 -defaultsOSRD
  1157. preplace port VCAP_HSYNC -pg 1 -y 1590 -defaultsOSRD
  1158. preplace port ZORRO_NCCS -pg 1 -y 1430 -defaultsOSRD
  1159. preplace port ZORRO_NDS0 -pg 1 -y 1410 -defaultsOSRD
  1160. preplace portBus VGA_B -pg 1 -y 1390 -defaultsOSRD
  1161. preplace portBus ZORRO_ADDR -pg 1 -y 1830 -defaultsOSRD
  1162. preplace portBus VGA_R -pg 1 -y 1290 -defaultsOSRD
  1163. preplace portBus ZORRO_DATA -pg 1 -y 1850 -defaultsOSRD
  1164. preplace portBus VGA_G -pg 1 -y 1190 -defaultsOSRD
  1165. preplace inst rst_ps7_0_25M -pg 1 -lvl 2 -y 540 -defaultsOSRD
  1166. preplace inst xlslice_0 -pg 1 -lvl 5 -y 1290 -defaultsOSRD
  1167. preplace inst xlslice_1 -pg 1 -lvl 5 -y 1190 -defaultsOSRD
  1168. preplace inst xadc_wiz_0 -pg 1 -lvl 5 -y 200 -defaultsOSRD
  1169. preplace inst xlslice_2 -pg 1 -lvl 5 -y 1390 -defaultsOSRD
  1170. preplace inst axi_dwidth_converter_0 -pg 1 -lvl 2 -y 330 -defaultsOSRD
  1171. preplace inst proc_sys_reset_0 -pg 1 -lvl 1 -y 330 -defaultsOSRD
  1172. preplace inst axi_register_slice_1 -pg 1 -lvl 3 -y 370 -defaultsOSRD
  1173. preplace inst MNTZorro_v0_1_S00_AXI_0 -pg 1 -lvl 4 -y 1750 -defaultsOSRD
  1174. preplace inst axi_interconnect_0 -pg 1 -lvl 3 -y 1090 -defaultsOSRD
  1175. preplace inst ps7_0_axi_periph -pg 1 -lvl 3 -y 150 -defaultsOSRD
  1176. preplace inst axi_interconnect_1 -pg 1 -lvl 3 -y 570 -defaultsOSRD
  1177. preplace inst video -pg 1 -lvl 4 -y 1120 -defaultsOSRD
  1178. preplace inst clk_wiz_0 -pg 1 -lvl 4 -y 780 -defaultsOSRD
  1179. preplace inst axi_interconnect_2 -pg 1 -lvl 3 -y 820 -defaultsOSRD
  1180. preplace inst processing_system7_0 -pg 1 -lvl 4 -y 490 -defaultsOSRD
  1181. preplace netloc S00_AXI_2 1 2 3 800 -10 NJ -10 1740
  1182. preplace netloc xlslice_2_Dout 1 5 1 NJ
  1183. preplace netloc S00_AXI_3 1 2 3 810 690 NJ 690 1740
  1184. preplace netloc VCAP_R4_0_1 1 0 4 NJ 1990 NJ 1990 NJ 1990 NJ
  1185. preplace netloc S00_AXI_4 1 2 3 810 940 NJ 940 1730
  1186. preplace netloc MNTZorro_v0_1_S00_AXI_0_arm_interrupt 1 3 2 1250 870 1750
  1187. preplace netloc VCAP_B2_0_1 1 0 4 NJ 1870 NJ 1870 NJ 1870 NJ
  1188. preplace netloc processing_system7_0_FIXED_IO 1 4 2 NJ 430 NJ
  1189. preplace netloc VCAP_VSYNC_0_1 1 0 4 NJ 1570 NJ 1570 NJ 1570 NJ
  1190. preplace netloc VCAP_B0_0_1 1 0 4 NJ 1910 NJ 1910 NJ 1910 NJ
  1191. preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NCINH 1 4 2 NJ 1830 2150J
  1192. preplace netloc rst_ps7_0_25M_peripheral_aresetn 1 2 3 780 -20 1200 230 N
  1193. preplace netloc ps7_0_axi_periph_M02_AXI 1 3 2 NJ 170 N
  1194. preplace netloc VCAP_G6_0_1 1 0 4 NJ 1730 NJ 1730 NJ 1730 NJ
  1195. preplace netloc VCAP_R2_0_1 1 0 4 NJ 2030 NJ 2030 NJ 2030 NJ
  1196. preplace netloc VCAP_G5_0_1 1 0 4 NJ 1710 NJ 1710 NJ 1710 NJ
  1197. preplace netloc video_subsystem_VGA_HS 1 4 2 NJ 1090 NJ
  1198. preplace netloc axi_dwidth_converter_0_M_AXI 1 2 1 790
  1199. preplace netloc VCAP_R5_0_1 1 0 4 NJ 1970 NJ 1970 NJ 1970 NJ
  1200. preplace netloc VCAP_G3_0_1 1 0 4 NJ 1670 NJ 1670 NJ 1670 NJ
  1201. preplace netloc VCAP_R1_0_1 1 0 4 NJ 2050 NJ 2050 NJ 2050 NJ
  1202. preplace netloc ZORRO_NIORST_1 1 0 4 NJ 1490 NJ 1490 NJ 1490 NJ
  1203. preplace netloc VCAP_B3_0_1 1 0 4 NJ 1850 NJ 1850 NJ 1850 NJ
  1204. preplace netloc ZORRO_NDS0_1 1 0 4 NJ 1410 NJ 1410 NJ 1410 NJ
  1205. preplace netloc ZORRO_NDS1_1 1 0 4 NJ 1390 NJ 1390 NJ 1390 NJ
  1206. preplace netloc video_subsystem_VGA_DE 1 4 2 NJ 1130 NJ
  1207. preplace netloc VCAP_G7_0_1 1 0 4 NJ 1750 NJ 1750 NJ 1750 NJ
  1208. preplace netloc processing_system7_0_FCLK_RESET1_N 1 1 4 390 700 NJ 700 1180J 670 1730
  1209. preplace netloc VCAP_HSYNC_0_1 1 0 4 NJ 1590 NJ 1590 NJ 1590 NJ
  1210. preplace netloc processing_system7_0_DDR 1 4 2 NJ 410 NJ
  1211. preplace netloc MNTZorro_v0_1_S00_AXI_0_m00_axi 1 1 4 390 -40 NJ -40 NJ -40 1770
  1212. preplace netloc VCAP_R3_0_1 1 0 4 NJ 2010 NJ 2010 NJ 2010 NJ
  1213. preplace netloc VCAP_R0_0_1 1 0 4 NJ 2070 NJ 2070 NJ 2070 NJ
  1214. preplace netloc ZORRO_NLDS_1 1 0 4 NJ 1370 NJ 1370 NJ 1370 NJ
  1215. preplace netloc axi_interconnect_1_M00_AXI 1 3 1 1160
  1216. preplace netloc VCAP_B4_0_1 1 0 4 NJ 1830 NJ 1830 NJ 1830 NJ
  1217. preplace netloc ZORRO_C28D_0_1 1 0 4 NJ 1550 NJ 1550 NJ 1550 NJ
  1218. preplace netloc ps7_0_axi_periph_M00_AXI 1 3 1 1220
  1219. preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 5 10 -30 NJ -30 NJ -30 NJ -30 1750
  1220. preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_INT6 1 4 2 NJ 1690 2220J
  1221. preplace netloc xlslice_1_Dout 1 5 1 NJ
  1222. preplace netloc ps7_0_axi_periph_M01_AXI 1 3 1 1190
  1223. preplace netloc VCAP_G1_0_1 1 0 4 NJ 1630 NJ 1630 NJ 1630 NJ
  1224. preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NDTACK 1 4 2 NJ 1850 2140J
  1225. preplace netloc VCAP_B5_0_1 1 0 4 NJ 1810 NJ 1810 NJ 1810 NJ
  1226. preplace netloc VCAP_G2_0_1 1 0 4 NJ 1650 NJ 1650 NJ 1650 NJ
  1227. preplace netloc video_control_vblank 1 3 2 1260 2300 1760
  1228. preplace netloc xlslice_0_Dout 1 5 1 NJ
  1229. preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_ADDRDIR2 1 4 2 NJ 1750 2190J
  1230. preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NSLAVE 1 4 2 NJ 1810 2160J
  1231. preplace netloc ZORRO_DOE_1 1 0 4 NJ 1470 NJ 1470 NJ 1470 NJ
  1232. preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_DATADIR 1 4 2 NJ 1710 2210J
  1233. preplace netloc axi_register_slice_1_M_AXI 1 3 1 1210
  1234. preplace netloc Net 1 4 2 NJ 1650 2240J
  1235. preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NBRN 1 4 2 NJ 1770 2180J
  1236. preplace netloc Net1 1 4 2 NJ 1670 2230J
  1237. preplace netloc processing_system7_0_FCLK_CLK0 1 0 5 20 230 380 250 770 450 1150 660 1740
  1238. preplace netloc VCAP_R7_0_1 1 0 4 NJ 1930 NJ 1930 NJ 1930 NJ
  1239. preplace netloc axi_interconnect_2_M00_AXI 1 3 1 1170
  1240. preplace netloc VCAP_B6_0_1 1 0 4 NJ 1790 NJ 1790 NJ 1790 NJ
  1241. preplace netloc v_axi4s_vid_out_0_vid_data 1 4 1 1780
  1242. preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_ADDRDIR 1 4 2 NJ 1730 2200J
  1243. preplace netloc VCAP_G0_0_1 1 0 4 NJ 1610 NJ 1610 NJ 1610 NJ
  1244. preplace netloc VCAP_R6_0_1 1 0 4 NJ 1950 NJ 1950 NJ 1950 NJ
  1245. preplace netloc proc_sys_reset_1_peripheral_aresetn 1 1 3 390 410 790 970 1130
  1246. preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NCFGOUT 1 4 2 NJ 1790 2170J
  1247. preplace netloc ZORRO_NCFGIN_1 1 0 4 NJ 1510 NJ 1510 NJ 1510 NJ
  1248. preplace netloc ZORRO_NCCS_1 1 0 4 NJ 1430 NJ 1430 NJ 1430 NJ
  1249. preplace netloc VCAP_B7_0_1 1 0 4 NJ 1770 NJ 1770 NJ 1770 NJ
  1250. preplace netloc ZORRO_NBGN_0_1 1 0 4 NJ 1310 NJ 1310 NJ 1310 NJ
  1251. preplace netloc ZORRO_E7M_1 1 0 4 NJ 1530 NJ 1530 NJ 1530 NJ
  1252. preplace netloc ZORRO_READ_1 1 0 4 NJ 1330 NJ 1330 NJ 1330 NJ
  1253. preplace netloc video_subsystem_VGA_VS 1 4 2 NJ 1110 NJ
  1254. preplace netloc MNTZorro_v0_1_S00_AXI_0_video_control_op 1 3 2 1240 2290 1750
  1255. preplace netloc VCAP_B1_0_1 1 0 4 NJ 1890 NJ 1890 NJ 1890 NJ
  1256. preplace netloc axi_interconnect_0_M00_AXI 1 3 1 1140
  1257. preplace netloc S00_AXI_1 1 2 3 810 960 NJ 960 1760
  1258. preplace netloc S00_ACLK_1 1 1 4 380 640 800 950 1230 650 1780
  1259. preplace netloc MNTZorro_v0_1_S00_AXI_0_video_control_interlace 1 3 2 1270 2280 1730
  1260. preplace netloc clk_1 1 3 3 1270 680 1780 770 NJ
  1261. preplace netloc MNTZorro_v0_1_S00_AXI_0_video_control_data 1 3 2 1250 2270 1740
  1262. preplace netloc ZORRO_NUDS_1 1 0 4 NJ 1350 NJ 1350 NJ 1350 NJ
  1263. preplace netloc ZORRO_NFCS_1 1 0 4 NJ 1450 NJ 1450 NJ 1450 NJ
  1264. preplace netloc VCAP_G4_0_1 1 0 4 NJ 1690 NJ 1690 NJ 1690 NJ
  1265. levelinfo -pg 1 -10 200 590 980 1500 2000 2280 -top -110 -bot 2310
  1266. "
  1267. }
  1268. # Restore current instance
  1269. current_bd_instance $oldCurInst
  1270. validate_bd_design
  1271. save_bd_design
  1272. close_bd_design $design_name
  1273. }
  1274. # End of cr_bd_zz9000_ps()
  1275. cr_bd_zz9000_ps ""
  1276. set_property REGISTERED_WITH_MANAGER "1" [get_files zz9000_ps.bd ]
  1277. set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files zz9000_ps.bd ]
  1278. # Create 'synth_1' run (if not found)
  1279. if {[string equal [get_runs -quiet synth_1] ""]} {
  1280. create_run -name synth_1 -part xc7z020clg400-1 -flow {Vivado Synthesis 2018} -strategy "Flow_PerfOptimized_high" -report_strategy {No Reports} -constrset constrs_1
  1281. } else {
  1282. set_property strategy "Flow_PerfOptimized_high" [get_runs synth_1]
  1283. set_property flow "Vivado Synthesis 2018" [get_runs synth_1]
  1284. }
  1285. set obj [get_runs synth_1]
  1286. set_property set_report_strategy_name 1 $obj
  1287. set_property report_strategy {Vivado Synthesis Default Reports} $obj
  1288. set_property set_report_strategy_name 0 $obj
  1289. # Create 'synth_1_synth_report_utilization_0' report (if not found)
  1290. if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
  1291. create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
  1292. }
  1293. set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
  1294. if { $obj != "" } {
  1295. set_property -name "display_name" -value "synth_1_synth_report_utilization_0" -objects $obj
  1296. }
  1297. set obj [get_runs synth_1]
  1298. set_property -name "part" -value "xc7z020clg400-1" -objects $obj
  1299. set_property -name "strategy" -value "Flow_PerfOptimized_high" -objects $obj
  1300. set_property -name "steps.synth_design.args.fanout_limit" -value "400" -objects $obj
  1301. set_property -name "steps.synth_design.args.fsm_extraction" -value "one_hot" -objects $obj
  1302. set_property -name "steps.synth_design.args.keep_equivalent_registers" -value "1" -objects $obj
  1303. set_property -name "steps.synth_design.args.resource_sharing" -value "off" -objects $obj
  1304. set_property -name "steps.synth_design.args.no_lc" -value "1" -objects $obj
  1305. set_property -name "steps.synth_design.args.shreg_min_size" -value "5" -objects $obj
  1306. # set the current synth run
  1307. current_run -synthesis [get_runs synth_1]
  1308. # Create 'impl_1' run (if not found)
  1309. if {[string equal [get_runs -quiet impl_1] ""]} {
  1310. create_run -name impl_1 -part xc7z020clg400-1 -flow {Vivado Implementation 2018} -strategy "Flow_RunPostRoutePhysOpt" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
  1311. } else {
  1312. set_property strategy "Flow_RunPostRoutePhysOpt" [get_runs impl_1]
  1313. set_property flow "Vivado Implementation 2018" [get_runs impl_1]
  1314. }
  1315. set obj [get_runs impl_1]
  1316. set_property set_report_strategy_name 1 $obj
  1317. set_property report_strategy {Timing Closure Reports} $obj
  1318. set_property set_report_strategy_name 0 $obj
  1319. # Create 'impl_1_opt_report_drc_0' report (if not found)
  1320. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
  1321. create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
  1322. }
  1323. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
  1324. if { $obj != "" } {
  1325. set_property -name "display_name" -value "impl_1_opt_report_drc_0" -objects $obj
  1326. }
  1327. # Create 'impl_1_opt_report_utilization_0' report (if not found)
  1328. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_utilization_0] "" ] } {
  1329. create_report_config -report_name impl_1_opt_report_utilization_0 -report_type report_utilization:1.0 -steps opt_design -runs impl_1
  1330. }
  1331. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_utilization_0]
  1332. if { $obj != "" } {
  1333. set_property -name "display_name" -value "impl_1_opt_report_utilization_0" -objects $obj
  1334. }
  1335. # Create 'impl_1_opt_report_methodology_0' report (if not found)
  1336. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_methodology_0] "" ] } {
  1337. create_report_config -report_name impl_1_opt_report_methodology_0 -report_type report_methodology:1.0 -steps opt_design -runs impl_1
  1338. }
  1339. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_methodology_0]
  1340. if { $obj != "" } {
  1341. set_property -name "display_name" -value "impl_1_opt_report_methodology_0" -objects $obj
  1342. }
  1343. # Create 'impl_1_opt_report_timing_summary_0' report (if not found)
  1344. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
  1345. create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
  1346. }
  1347. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
  1348. if { $obj != "" } {
  1349. set_property -name "display_name" -value "impl_1_opt_report_timing_summary_0" -objects $obj
  1350. }
  1351. # Create 'impl_1_place_report_io_0' report (if not found)
  1352. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
  1353. create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
  1354. }
  1355. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
  1356. if { $obj != "" } {
  1357. set_property -name "display_name" -value "impl_1_place_report_io_0" -objects $obj
  1358. }
  1359. # Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
  1360. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
  1361. create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
  1362. }
  1363. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
  1364. if { $obj != "" } {
  1365. set_property -name "display_name" -value "impl_1_place_report_incremental_reuse_0" -objects $obj
  1366. }
  1367. # Create 'impl_1_place_report_timing_summary_0' report (if not found)
  1368. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
  1369. create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
  1370. }
  1371. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
  1372. if { $obj != "" } {
  1373. set_property -name "display_name" -value "impl_1_place_report_timing_summary_0" -objects $obj
  1374. }
  1375. # Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
  1376. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
  1377. create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
  1378. }
  1379. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
  1380. if { $obj != "" } {
  1381. set_property -name "display_name" -value "impl_1_phys_opt_report_timing_summary_0" -objects $obj
  1382. }
  1383. # Create 'impl_1_phys_opt_report_design_analysis_0' report (if not found)
  1384. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_design_analysis_0] "" ] } {
  1385. create_report_config -report_name impl_1_phys_opt_report_design_analysis_0 -report_type report_design_analysis:1.0 -steps phys_opt_design -runs impl_1
  1386. }
  1387. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_design_analysis_0]
  1388. if { $obj != "" } {
  1389. set_property -name "display_name" -value "impl_1_phys_opt_report_design_analysis_0" -objects $obj
  1390. }
  1391. # Create 'impl_1_route_report_utilization_0' report (if not found)
  1392. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_utilization_0] "" ] } {
  1393. create_report_config -report_name impl_1_route_report_utilization_0 -report_type report_utilization:1.0 -steps route_design -runs impl_1
  1394. }
  1395. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_utilization_0]
  1396. if { $obj != "" } {
  1397. set_property -name "display_name" -value "impl_1_route_report_utilization_0" -objects $obj
  1398. }
  1399. # Create 'impl_1_route_report_clock_utilization_0' report (if not found)
  1400. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
  1401. create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
  1402. }
  1403. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
  1404. if { $obj != "" } {
  1405. set_property -name "display_name" -value "impl_1_route_report_clock_utilization_0" -objects $obj
  1406. }
  1407. # Create 'impl_1_route_report_drc_0' report (if not found)
  1408. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
  1409. create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
  1410. }
  1411. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
  1412. if { $obj != "" } {
  1413. set_property -name "display_name" -value "impl_1_route_report_drc_0" -objects $obj
  1414. }
  1415. # Create 'impl_1_route_report_power_0' report (if not found)
  1416. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
  1417. create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
  1418. }
  1419. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
  1420. if { $obj != "" } {
  1421. set_property -name "display_name" -value "impl_1_route_report_power_0" -objects $obj
  1422. }
  1423. # Create 'impl_1_route_report_route_status_0' report (if not found)
  1424. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
  1425. create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
  1426. }
  1427. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
  1428. if { $obj != "" } {
  1429. set_property -name "display_name" -value "impl_1_route_report_route_status_0" -objects $obj
  1430. }
  1431. # Create 'impl_1_route_report_timing_summary_0' report (if not found)
  1432. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
  1433. create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
  1434. }
  1435. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
  1436. if { $obj != "" } {
  1437. set_property -name "display_name" -value "impl_1_route_report_timing_summary_0" -objects $obj
  1438. }
  1439. # Create 'impl_1_route_report_design_analysis_0' report (if not found)
  1440. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_design_analysis_0] "" ] } {
  1441. create_report_config -report_name impl_1_route_report_design_analysis_0 -report_type report_design_analysis:1.0 -steps route_design -runs impl_1
  1442. }
  1443. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_design_analysis_0]
  1444. if { $obj != "" } {
  1445. set_property -name "display_name" -value "impl_1_route_report_design_analysis_0" -objects $obj
  1446. }
  1447. # Create 'impl_1_route_report_qor_suggestions_0' report (if not found)
  1448. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_qor_suggestions_0] "" ] } {
  1449. create_report_config -report_name impl_1_route_report_qor_suggestions_0 -report_type report_qor_suggestions:1.0 -steps route_design -runs impl_1
  1450. }
  1451. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_qor_suggestions_0]
  1452. if { $obj != "" } {
  1453. set_property -name "display_name" -value "impl_1_route_report_qor_suggestions_0" -objects $obj
  1454. }
  1455. # Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
  1456. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
  1457. create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
  1458. }
  1459. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
  1460. if { $obj != "" } {
  1461. set_property -name "display_name" -value "impl_1_route_report_incremental_reuse_0" -objects $obj
  1462. }
  1463. # Create 'impl_1_route_report_bus_skew_0' report (if not found)
  1464. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
  1465. create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
  1466. }
  1467. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
  1468. if { $obj != "" } {
  1469. set_property -name "display_name" -value "impl_1_route_report_bus_skew_0" -objects $obj
  1470. }
  1471. # Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
  1472. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
  1473. create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
  1474. }
  1475. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
  1476. if { $obj != "" } {
  1477. set_property -name "display_name" -value "impl_1_post_route_phys_opt_report_timing_summary_0" -objects $obj
  1478. }
  1479. # Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
  1480. if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
  1481. create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
  1482. }
  1483. set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
  1484. if { $obj != "" } {
  1485. set_property -name "display_name" -value "impl_1_post_route_phys_opt_report_bus_skew_0" -objects $obj
  1486. }
  1487. set obj [get_runs impl_1]
  1488. set_property -name "part" -value "xc7z020clg400-1" -objects $obj
  1489. set_property -name "strategy" -value "Flow_RunPostRoutePhysOpt" -objects $obj
  1490. set_property -name "steps.phys_opt_design.is_enabled" -value "1" -objects $obj
  1491. set_property -name "steps.phys_opt_design.args.directive" -value "Explore" -objects $obj
  1492. set_property -name "steps.route_design.args.more options" -value "-tns_cleanup" -objects $obj
  1493. set_property -name "steps.post_route_phys_opt_design.is_enabled" -value "1" -objects $obj
  1494. set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
  1495. set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
  1496. # set the current impl run
  1497. current_run -implementation [get_runs impl_1]
  1498. puts "INFO: Project created:${_xil_proj_name_}"
  1499. set obj [get_dashboards default_dashboard]
  1500. # Create 'drc_1' gadget (if not found)
  1501. if {[string equal [get_dashboard_gadgets -of_objects [get_dashboards default_dashboard] [ list "drc_1" ] ] ""]} {
  1502. create_dashboard_gadget -name {drc_1} -type drc
  1503. }
  1504. set obj [get_dashboard_gadgets -of_objects [get_dashboards default_dashboard] [ list "drc_1" ] ]
  1505. set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
  1506. # Create 'methodology_1' gadget (if not found)
  1507. if {[string equal [get_dashboard_gadgets -of_objects [get_dashboards default_dashboard] [ list "methodology_1" ] ] ""]} {
  1508. create_dashboard_gadget -name {methodology_1} -type methodology
  1509. }
  1510. set obj [get_dashboard_gadgets -of_objects [get_dashboards default_dashboard] [ list "methodology_1" ] ]
  1511. set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
  1512. # Create 'power_1' gadget (if not found)
  1513. if {[string equal [get_dashboard_gadgets -of_objects [get_dashboards default_dashboard] [ list "power_1" ] ] ""]} {
  1514. create_dashboard_gadget -name {power_1} -type power
  1515. }
  1516. set obj [get_dashboard_gadgets -of_objects [get_dashboards default_dashboard] [ list "power_1" ] ]
  1517. set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
  1518. # Create 'timing_1' gadget (if not found)
  1519. if {[string equal [get_dashboard_gadgets -of_objects [get_dashboards default_dashboard] [ list "timing_1" ] ] ""]} {
  1520. create_dashboard_gadget -name {timing_1} -type timing
  1521. }
  1522. set obj [get_dashboard_gadgets -of_objects [get_dashboards default_dashboard] [ list "timing_1" ] ]
  1523. set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
  1524. # Create 'utilization_1' gadget (if not found)
  1525. if {[string equal [get_dashboard_gadgets -of_objects [get_dashboards default_dashboard] [ list "utilization_1" ] ] ""]} {
  1526. create_dashboard_gadget -name {utilization_1} -type utilization
  1527. }
  1528. set obj [get_dashboard_gadgets -of_objects [get_dashboards default_dashboard] [ list "utilization_1" ] ]
  1529. set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
  1530. set_property -name "run.step" -value "synth_design" -objects $obj
  1531. set_property -name "run.type" -value "synthesis" -objects $obj
  1532. # Create 'utilization_2' gadget (if not found)
  1533. if {[string equal [get_dashboard_gadgets -of_objects [get_dashboards default_dashboard] [ list "utilization_2" ] ] ""]} {
  1534. create_dashboard_gadget -name {utilization_2} -type utilization
  1535. }
  1536. set obj [get_dashboard_gadgets -of_objects [get_dashboards default_dashboard] [ list "utilization_2" ] ]
  1537. set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
  1538. move_dashboard_gadget -name {utilization_1} -row 0 -col 0
  1539. move_dashboard_gadget -name {power_1} -row 1 -col 0
  1540. move_dashboard_gadget -name {drc_1} -row 2 -col 0
  1541. move_dashboard_gadget -name {timing_1} -row 0 -col 1
  1542. move_dashboard_gadget -name {utilization_2} -row 1 -col 1
  1543. move_dashboard_gadget -name {methodology_1} -row 2 -col 1
  1544. # Set current dashboard to 'default_dashboard'
  1545. current_dashboard default_dashboard