Firmware for MNT ZZ9000 graphics and ARM coprocessor card for Amiga computers.
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video_formatter.v 13KB

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  1. `timescale 1ns / 1ps
  2. /*
  3. * MNT ZZ9000 Amiga Graphics and Coprocessor Card Firmware
  4. * Video Stream Formatter
  5. *
  6. * Copyright (C) 2019, Lukas F. Hartmann <lukas@mntre.com>
  7. * MNT Research GmbH, Berlin
  8. * https://mntre.com
  9. *
  10. * More Info: https://mntre.com/zz9000
  11. *
  12. * SPDX-License-Identifier: GPL-3.0-or-later
  13. * GNU General Public License v3.0 or later
  14. *
  15. * https://spdx.org/licenses/GPL-3.0-or-later.html
  16. *
  17. */
  18. module video_formatter(
  19. input [31:0] m_axis_vid_tdata,
  20. input m_axis_vid_tlast,
  21. output m_axis_vid_tready,
  22. input [0:0] m_axis_vid_tuser,
  23. input m_axis_vid_tvalid,
  24. input m_axis_vid_aclk,
  25. input aresetn,
  26. input dvi_clk,
  27. output reg dvi_hsync,
  28. output reg dvi_vsync,
  29. output reg dvi_active_video,
  30. output reg [31:0] dvi_rgb,
  31. // control inputs for setting palette, width/height, scaling
  32. input [31:0] control_data,
  33. input [7:0] control_op,
  34. input control_interlace,
  35. output reg control_vblank
  36. );
  37. localparam OP_COLORMODE=1;
  38. localparam OP_DIMENSIONS=2;
  39. localparam OP_PALETTE=3;
  40. localparam OP_SCALE=4;
  41. localparam OP_VSYNC=5;
  42. localparam OP_MAX=6;
  43. localparam OP_HS=7;
  44. localparam OP_VS=8;
  45. localparam OP_THRESH=9;
  46. localparam OP_POLARITY=10;
  47. localparam OP_RESET=11;
  48. localparam OP_UNUSED1=12;
  49. localparam OP_SPRITEXY=13;
  50. localparam OP_SPRITE_ADDR=14;
  51. localparam OP_SPRITE_DATA=15;
  52. localparam CMODE_8BIT=0;
  53. localparam CMODE_16BIT=1;
  54. localparam CMODE_32BIT=2;
  55. localparam CMODE_15BIT=4;
  56. reg [11:0] screen_width; // = 720;
  57. reg [11:0] screen_height; // = 576;
  58. reg scale_x = 0;
  59. reg scale_y = 1; // amiga boots in 640x256, so double the resolution vertically
  60. reg [31:0] palette[255:0];
  61. reg [2:0] colormode = CMODE_32BIT;
  62. reg vsync_request = 0;
  63. reg sync_polarity = 1; // negative polarity
  64. reg [15:0] screen_h_max; //= 864;
  65. reg [15:0] screen_v_max; //= 625;
  66. reg [15:0] screen_h_sync_start; //= 732;
  67. reg [15:0] screen_h_sync_end; //= 796;
  68. reg [15:0] screen_v_sync_start; //= 581;
  69. reg [15:0] screen_v_sync_end; //= 586;
  70. localparam MAXWIDTH=1280; // 1920?!?
  71. reg [31:0] line_buffer[MAXWIDTH-1:0];
  72. // (input) vdma state
  73. reg [3:0] next_input_state = 0;
  74. reg [11:0] inptr = 0;
  75. reg ready_for_vdma = 0;
  76. assign m_axis_vid_tready = ready_for_vdma;
  77. reg [11:0] counter_x = 0; // vga domain
  78. reg [11:0] counter_y = 0; // vga domain
  79. reg [11:0] need_line_fetch = 0; // vga domain
  80. reg [11:0] need_line_fetch_reg = 0;
  81. reg [11:0] need_line_fetch_reg2 = 0;
  82. reg [11:0] need_line_fetch_reg3 = 0;
  83. reg [11:0] last_line_fetch = 1;
  84. wire [31:0] pixin = m_axis_vid_tdata;
  85. wire pixin_valid = m_axis_vid_tvalid;
  86. wire pixin_end_of_line = m_axis_vid_tlast;
  87. wire pixin_framestart = m_axis_vid_tuser[0];
  88. reg scale_y_effective;
  89. reg need_frame_sync; // vga domain
  90. reg need_frame_sync_reg; // fetch domain
  91. // sprite
  92. localparam SPRITE_W = 32;
  93. localparam SPRITE_H = 48;
  94. localparam SPRITE_SIZE = SPRITE_W*SPRITE_H;
  95. reg [23:0] sprite_buffer[SPRITE_SIZE-1:0];
  96. reg [11:0] sprite_addr_in = 0;
  97. reg [11:0] sprite_x = 0;
  98. reg [11:0] sprite_y = 0;
  99. reg [11:0] vga_sprite_x = 0; // vga domain
  100. reg [11:0] vga_sprite_y = 0; // vga domain
  101. reg [11:0] sprite_px = 0; // vga domain
  102. reg [23:0] sprite_pix; // vga domain
  103. reg sprite_on = 0; // vga domain
  104. always @(posedge m_axis_vid_aclk)
  105. begin
  106. if (~aresetn) begin
  107. ready_for_vdma <= 0;
  108. next_input_state <= 0;
  109. inptr <= 0;
  110. end
  111. need_frame_sync_reg <= need_frame_sync;
  112. need_line_fetch_reg <= need_line_fetch; // sync to clock domain
  113. need_line_fetch_reg2 <= need_line_fetch_reg>>scale_y_effective; // line duplication
  114. scale_y_effective <= control_interlace ? 0 : scale_y;
  115. if (pixin_valid && ready_for_vdma) begin
  116. line_buffer[inptr] <= pixin;
  117. // disabling this makes the picture go wild
  118. if (pixin_framestart) // we might have missed the frame start
  119. inptr <= 1;
  120. else if (pixin_end_of_line) // next after this is the first pixel of the line (0)
  121. inptr <= 0;
  122. else
  123. inptr <= inptr + 1'b1;
  124. end
  125. case (next_input_state)
  126. 4'h0: begin
  127. // wait for start of frame
  128. ready_for_vdma <= 1;
  129. if (pixin_framestart)
  130. next_input_state <= 4'h3;
  131. end
  132. 4'h1: begin
  133. // reading from vdma
  134. last_line_fetch <= need_line_fetch_reg2;
  135. if (pixin_valid && pixin_end_of_line) begin
  136. ready_for_vdma <= 0;
  137. next_input_state <= 4'h2;
  138. end else
  139. ready_for_vdma <= 1; // moved here
  140. end
  141. 4'h2: begin
  142. // we've read more than enough of this line, wait until it's time for the next
  143. if (vsync_request) begin
  144. next_input_state <= 4'h0;
  145. end
  146. else if (need_line_fetch_reg2!=last_line_fetch) begin
  147. // time to read the next line
  148. next_input_state <= 4'h1;
  149. //ready_for_vdma <= 1; // from here
  150. end
  151. end
  152. 4'h3: begin
  153. // we are at frame start, wait for the first line of video output
  154. ready_for_vdma <= 0;
  155. // line_fetch_reg2 == 0
  156. if (need_frame_sync_reg==1) begin
  157. next_input_state <= 4'h2;
  158. end
  159. end
  160. endcase
  161. end
  162. reg [31:0] control_data_in;
  163. reg [7:0] control_op_in;
  164. reg control_interlace_in;
  165. reg [31:0] control_data_in2;
  166. reg [7:0] control_op_in2;
  167. reg control_interlace_in2;
  168. // control input
  169. always @(posedge m_axis_vid_aclk)
  170. begin
  171. control_op_in2 <= control_op;
  172. control_op_in <= control_op_in2;
  173. control_data_in2 <= control_data;
  174. control_data_in <= control_data_in2;
  175. control_interlace_in2 <= control_interlace;
  176. control_interlace_in <= control_interlace_in2;
  177. if (next_input_state==0) begin
  178. vsync_request <= 0;
  179. end
  180. if (control_interlace_in != control_interlace) begin
  181. vsync_request <= 1;
  182. end
  183. case (control_op_in)
  184. OP_PALETTE: palette[control_data_in[31:24]] <= control_data_in[23:0];
  185. OP_DIMENSIONS: begin
  186. screen_height <= control_data_in[31:16];
  187. screen_width <= control_data_in[15:0];
  188. end
  189. OP_SCALE: begin
  190. scale_x <= control_data_in[0];
  191. scale_y <= control_data_in[1];
  192. end
  193. OP_COLORMODE: colormode <= control_data_in[1:0]; // FIXME
  194. OP_VSYNC: vsync_request <= 1; //control_data[0];
  195. OP_MAX: begin
  196. screen_v_max <= control_data_in[31:16];
  197. screen_h_max <= control_data_in[15:0];
  198. end
  199. OP_HS: begin
  200. screen_h_sync_start <= control_data_in[31:16];
  201. screen_h_sync_end <= control_data_in[15:0];
  202. end
  203. OP_VS: begin
  204. screen_v_sync_start <= control_data_in[31:16];
  205. screen_v_sync_end <= control_data_in[15:0];
  206. end
  207. OP_THRESH: begin
  208. end
  209. OP_POLARITY: begin
  210. sync_polarity <= control_data_in[0];
  211. end
  212. OP_RESET: begin
  213. /*sync_polarity <= 1;
  214. screen_h_max <= 864;
  215. screen_v_max <= 625;
  216. screen_h_sync_start <= 732;
  217. screen_h_sync_end <= 796;
  218. screen_v_sync_start <= 581;
  219. screen_v_sync_end <= 586;
  220. scale_x <= 0;
  221. scale_y <= 1;
  222. screen_width <= 720;
  223. screen_height <= 576;
  224. colormode <= CMODE_32BIT;*/
  225. end
  226. OP_SPRITEXY: begin
  227. sprite_y <= control_data_in[31:16];
  228. sprite_x <= control_data_in[15:0];
  229. end
  230. OP_SPRITE_ADDR: begin
  231. sprite_addr_in <= control_data_in[11:0];
  232. end
  233. OP_SPRITE_DATA: begin
  234. sprite_buffer[sprite_addr_in] <= control_data_in[23:0];
  235. end
  236. endcase
  237. end
  238. reg [31:0] palout;
  239. reg [11:0] vga_v_rez;
  240. reg [11:0] vga_h_rez;
  241. reg [11:0] vga_v_max;
  242. reg [11:0] vga_h_max;
  243. reg [11:0] vga_h_sync_start;
  244. reg [11:0] vga_h_sync_end;
  245. reg [11:0] vga_v_sync_start;
  246. reg [11:0] vga_v_sync_end;
  247. reg [11:0] counter_scanout;
  248. reg [2:0] vga_colormode;
  249. reg [11:0] vga_h_rez_shifted;
  250. reg [11:0] vga_v_rez_shifted;
  251. reg vga_scale_x = 0;
  252. reg [31:0] pixout;
  253. reg [7:0] pixout8;
  254. reg [15:0] pixout16;
  255. reg [31:0] pixout32;
  256. reg [31:0] pixout32_dly;
  257. reg [31:0] pixout32_dly2;
  258. wire [7:0] red16 = {pixout16[4:0], pixout16[4:2]};
  259. wire [7:0] green16 = {pixout16[10:5], pixout16[10:9]};
  260. wire [7:0] blue16 = {pixout16[15:11], pixout16[15:13]};
  261. wire [7:0] red15 = {pixout16[4:0], pixout16[4:2]};
  262. wire [7:0] green15 = {pixout16[9:5], pixout16[9:7]};
  263. wire [7:0] blue15 = {pixout16[14:10], pixout16[14:12]};
  264. reg [3:0] counter_scanout_step; // = 0;
  265. reg [3:0] counter_subpixel = 0;
  266. reg vga_sync_polarity = 0;
  267. always @(posedge dvi_clk) begin
  268. vga_h_rez <= screen_width;
  269. vga_v_rez <= screen_height;
  270. vga_h_max <= screen_h_max;
  271. vga_v_max <= screen_v_max;
  272. vga_h_sync_start <= screen_h_sync_start; // + 4
  273. vga_h_sync_end <= screen_h_sync_end; // + 4
  274. vga_v_sync_start <= screen_v_sync_start;
  275. vga_v_sync_end <= screen_v_sync_end;
  276. vga_scale_x <= scale_x;
  277. vga_colormode <= colormode;
  278. vga_sync_polarity <= sync_polarity;
  279. if (counter_y == 0) begin
  280. vga_sprite_x <= sprite_x;
  281. vga_sprite_y <= sprite_y;
  282. end
  283. // FIXME there is some non-determinism in the relationship
  284. // between this process and the fetching process
  285. // depending on when a new screen is launched, there can be
  286. // 1 row of wrap-around
  287. /*
  288. pipelines (4 clocks):
  289. linebuf pixout32 pixout32_dly pixout32_dly2 pixout
  290. linebuf pixout32 pixout16 pixout32_dly pixout
  291. linebuf pixout32 pixout8 palout pixout
  292. */
  293. case ({vga_scale_x,counter_subpixel[2:0]})
  294. 4'b0011: pixout8 <= pixout32[31:24];
  295. 4'b0000: pixout8 <= pixout32[23:16];
  296. 4'b0001: pixout8 <= pixout32[15:8];
  297. 4'b0010: pixout8 <= pixout32[7:0];
  298. 4'b1111: pixout8 <= pixout32[31:24];
  299. 4'b1000: pixout8 <= pixout32[31:24];
  300. 4'b1001: pixout8 <= pixout32[23:16];
  301. 4'b1010: pixout8 <= pixout32[23:16];
  302. 4'b1011: pixout8 <= pixout32[15:8];
  303. 4'b1100: pixout8 <= pixout32[15:8];
  304. 4'b1101: pixout8 <= pixout32[7:0];
  305. 4'b1110: pixout8 <= pixout32[7:0];
  306. endcase
  307. case ({vga_scale_x,counter_subpixel[1:0]})
  308. 3'b001: pixout16 <= {pixout32[23:16],pixout32[31:24]};
  309. 3'b000: pixout16 <= {pixout32[7:0] ,pixout32[15:8] };
  310. 3'b100: pixout16 <= {pixout32[23:16],pixout32[31:24]};
  311. 3'b111: pixout16 <= {pixout32[23:16],pixout32[31:24]};
  312. 3'b110: pixout16 <= {pixout32[7:0] ,pixout32[15:8] };
  313. 3'b101: pixout16 <= {pixout32[7:0] ,pixout32[15:8] };
  314. endcase
  315. case ({vga_scale_x,vga_colormode})
  316. 4'b0000: counter_scanout_step <= 3; // 8 bit
  317. 4'b1000: counter_scanout_step <= 7;
  318. 4'b0001: counter_scanout_step <= 1; // 16 bit
  319. 4'b1001: counter_scanout_step <= 3;
  320. 4'b0010: counter_scanout_step <= 0; // 32 bit
  321. 4'b1010: counter_scanout_step <= 1;
  322. //4'b0100: counter_scanout_step <= 1; // 15 bit
  323. //4'b1100: counter_scanout_step <= 3;
  324. endcase
  325. if (counter_x>vga_h_rez) begin
  326. counter_scanout <= 0;
  327. counter_subpixel <= counter_scanout_step;
  328. end else begin
  329. if (counter_subpixel == 0) begin
  330. counter_subpixel <= counter_scanout_step;
  331. counter_scanout <= counter_scanout + 1'b1;
  332. end else
  333. counter_subpixel <= counter_subpixel - 1'b1;
  334. end
  335. pixout32 <= line_buffer[counter_scanout];
  336. if (vga_colormode==CMODE_16BIT)
  337. // 16 bit 5r6g5b
  338. pixout32_dly <= {8'b0,blue16,green16,red16};
  339. //else if (vga_colormode==CMODE_15BIT)
  340. // // 15 bit 5r5g5b for shapeshifter
  341. // pixout32_dly <= {8'b0,blue15,green15,red15};
  342. else
  343. pixout32_dly <= pixout32;
  344. pixout32_dly2 <= pixout32_dly;
  345. palout <= palette[pixout8];
  346. case (vga_colormode)
  347. CMODE_8BIT: pixout <= palout;
  348. CMODE_16BIT: pixout <= pixout32_dly;
  349. CMODE_32BIT: pixout <= pixout32_dly2;
  350. endcase
  351. sprite_pix <= sprite_buffer[sprite_px];
  352. if (counter_y >= vga_sprite_y && counter_y < (vga_sprite_y+SPRITE_H)
  353. && counter_x >= vga_sprite_x && counter_x < (vga_sprite_x+SPRITE_W)) begin
  354. sprite_on <= 1;
  355. sprite_px <= sprite_px + 1;
  356. end else begin
  357. sprite_on <= 0;
  358. end
  359. dvi_rgb <= (sprite_on && sprite_pix!='hff00ff) ? sprite_pix : pixout;
  360. if (counter_x > vga_h_max) begin
  361. counter_x <= 0;
  362. if (counter_y > vga_v_max) begin
  363. counter_y <= 0;
  364. sprite_px <= 0;
  365. end else begin
  366. counter_y <= counter_y + 1'b1;
  367. end
  368. end else begin
  369. counter_x <= counter_x + 1'b1;
  370. end
  371. if (counter_x==vga_h_rez) begin
  372. if (counter_y<vga_v_rez-1'b1)
  373. need_line_fetch <= counter_y + 1'b1;
  374. else
  375. need_line_fetch <= 0;
  376. end
  377. // signal synchronization point to fetch process
  378. if (counter_x<8 && counter_y==vga_v_sync_start)
  379. need_frame_sync <= 1;
  380. else
  381. need_frame_sync <= 0;
  382. if (counter_x>=vga_h_sync_start && counter_x<vga_h_sync_end)
  383. dvi_hsync <= 1^vga_sync_polarity;
  384. else
  385. dvi_hsync <= 0^vga_sync_polarity;
  386. if (counter_y>=vga_v_sync_start && counter_y<vga_v_sync_end) begin
  387. dvi_vsync <= 1^vga_sync_polarity;
  388. control_vblank <= 1;
  389. end
  390. else begin
  391. dvi_vsync <= 0^vga_sync_polarity;
  392. control_vblank <= 0;
  393. end
  394. // 4 clocks pipeline delay
  395. vga_h_rez_shifted <= vga_h_rez+4;
  396. if (counter_y<vga_v_rez && counter_x==4)
  397. dvi_active_video <= 1;
  398. if (counter_x==vga_h_rez_shifted)
  399. dvi_active_video <= 0;
  400. end
  401. endmodule