Firmware for MNT ZZ9000 graphics and ARM coprocessor card for Amiga computers.
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video_formatter.v 12KB

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  1. `timescale 1ns / 1ps
  2. /*
  3. * MNT ZZ9000 Amiga Graphics and Coprocessor Card Firmware
  4. * Video Stream Formatter
  5. *
  6. * Copyright (C) 2019, Lukas F. Hartmann <lukas@mntre.com>
  7. * MNT Research GmbH, Berlin
  8. * https://mntre.com
  9. *
  10. * More Info: https://mntre.com/zz9000
  11. *
  12. * SPDX-License-Identifier: GPL-3.0-or-later
  13. * GNU General Public License v3.0 or later
  14. *
  15. * https://spdx.org/licenses/GPL-3.0-or-later.html
  16. *
  17. */
  18. module video_formatter(
  19. input [31:0] m_axis_vid_tdata,
  20. input m_axis_vid_tlast,
  21. output m_axis_vid_tready,
  22. input [0:0] m_axis_vid_tuser,
  23. input m_axis_vid_tvalid,
  24. input m_axis_vid_aclk,
  25. input aresetn,
  26. input dvi_clk,
  27. output reg dvi_hsync,
  28. output reg dvi_vsync,
  29. output reg dvi_active_video,
  30. output reg [31:0] dvi_rgb,
  31. // control inputs for setting palette, width/height, scaling
  32. input [31:0] control_data,
  33. input [7:0] control_op,
  34. input control_interlace
  35. );
  36. localparam OP_COLORMODE=1;
  37. localparam OP_DIMENSIONS=2;
  38. localparam OP_PALETTE=3;
  39. localparam OP_SCALE=4;
  40. localparam OP_VSYNC=5;
  41. localparam OP_MAX=6;
  42. localparam OP_HS=7;
  43. localparam OP_VS=8;
  44. localparam OP_THRESH=9;
  45. localparam OP_POLARITY=10;
  46. localparam OP_RESET=11;
  47. localparam OP_MISC=12;
  48. localparam CMODE_8BIT=0;
  49. localparam CMODE_16BIT=1;
  50. localparam CMODE_32BIT=2;
  51. localparam CMODE_15BIT=4;
  52. reg [11:0] screen_width; // = 720;
  53. reg [11:0] screen_height; // = 576;
  54. reg scale_x = 0;
  55. reg scale_y = 1; // amiga boots in 640x256, so double the resolution vertically
  56. reg [31:0] palette[255:0];
  57. reg [2:0] colormode = CMODE_32BIT;
  58. reg vsync_request = 0;
  59. reg sync_polarity = 1; // negative polarity
  60. reg [15:0] screen_h_max; //= 864;
  61. reg [15:0] screen_v_max; //= 625;
  62. reg [15:0] screen_h_sync_start; //= 732;
  63. reg [15:0] screen_h_sync_end; //= 796;
  64. reg [15:0] screen_v_sync_start; //= 581;
  65. reg [15:0] screen_v_sync_end; //= 586;
  66. localparam MAXWIDTH=1280; // 1920?!?
  67. reg [31:0] line_buffer[MAXWIDTH-1:0];
  68. // (input) vdma state
  69. reg [3:0] next_input_state = 0;
  70. reg [11:0] inptr = 0;
  71. reg ready_for_vdma = 0;
  72. assign m_axis_vid_tready = ready_for_vdma;
  73. reg [11:0] counter_x = 0; // vga domain
  74. reg [11:0] counter_y = 0; // vga domain
  75. reg [11:0] need_line_fetch = 0; // vga domain
  76. reg [11:0] need_line_fetch_reg = 0;
  77. reg [11:0] need_line_fetch_reg2 = 0;
  78. reg [11:0] need_line_fetch_reg3 = 0;
  79. reg [11:0] last_line_fetch = 1;
  80. wire [31:0] pixin = m_axis_vid_tdata;
  81. wire pixin_valid = m_axis_vid_tvalid;
  82. wire pixin_end_of_line = m_axis_vid_tlast;
  83. wire pixin_framestart = m_axis_vid_tuser[0];
  84. reg scale_y_effective;
  85. reg need_frame_sync; // vga domain
  86. reg need_frame_sync_reg; // fetch domain
  87. always @(posedge m_axis_vid_aclk)
  88. begin
  89. if (~aresetn) begin
  90. ready_for_vdma <= 0;
  91. next_input_state <= 0;
  92. inptr <= 0;
  93. end
  94. need_frame_sync_reg <= need_frame_sync;
  95. need_line_fetch_reg <= need_line_fetch; // sync to clock domain
  96. need_line_fetch_reg2 <= need_line_fetch_reg>>scale_y_effective; // line duplication
  97. scale_y_effective <= control_interlace ? 0 : scale_y;
  98. if (pixin_valid && ready_for_vdma) begin
  99. line_buffer[inptr] <= pixin;
  100. // disabling this makes the picture go wild
  101. if (pixin_framestart) // we might have missed the frame start
  102. inptr <= 1;
  103. else if (pixin_end_of_line) // next after this is the first pixel of the line (0)
  104. inptr <= 0;
  105. else
  106. inptr <= inptr + 1'b1;
  107. end
  108. case (next_input_state)
  109. 4'h0: begin
  110. // wait for start of frame
  111. ready_for_vdma <= 1;
  112. if (pixin_framestart)
  113. next_input_state <= 4'h3;
  114. end
  115. 4'h1: begin
  116. // reading from vdma
  117. last_line_fetch <= need_line_fetch_reg2;
  118. if (pixin_valid && pixin_end_of_line) begin
  119. ready_for_vdma <= 0;
  120. next_input_state <= 4'h2;
  121. end else
  122. ready_for_vdma <= 1; // moved here
  123. end
  124. 4'h2: begin
  125. // we've read more than enough of this line, wait until it's time for the next
  126. if (vsync_request) begin
  127. next_input_state <= 4'h0;
  128. end
  129. else if (need_line_fetch_reg2!=last_line_fetch) begin
  130. // time to read the next line
  131. next_input_state <= 4'h1;
  132. //ready_for_vdma <= 1; // from here
  133. end
  134. end
  135. 4'h3: begin
  136. // we are at frame start, wait for the first line of video output
  137. ready_for_vdma <= 0;
  138. // line_fetch_reg2 == 0
  139. if (need_frame_sync_reg==1) begin
  140. next_input_state <= 4'h2;
  141. end
  142. end
  143. endcase
  144. end
  145. reg [31:0] control_data_in;
  146. reg [7:0] control_op_in;
  147. reg control_interlace_in;
  148. reg [31:0] control_data_in2;
  149. reg [7:0] control_op_in2;
  150. reg control_interlace_in2;
  151. // control input
  152. always @(posedge m_axis_vid_aclk)
  153. begin
  154. control_op_in2 <= control_op;
  155. control_op_in <= control_op_in2;
  156. control_data_in2 <= control_data;
  157. control_data_in <= control_data_in2;
  158. control_interlace_in2 <= control_interlace;
  159. control_interlace_in <= control_interlace_in2;
  160. if (next_input_state==0) begin
  161. vsync_request <= 0;
  162. end
  163. if (control_interlace_in != control_interlace) begin
  164. vsync_request <= 1;
  165. end
  166. case (control_op_in)
  167. OP_PALETTE: palette[control_data_in[31:24]] <= control_data_in[23:0];
  168. OP_DIMENSIONS: begin
  169. screen_height <= control_data_in[31:16];
  170. screen_width <= control_data_in[15:0];
  171. end
  172. OP_SCALE: begin
  173. scale_x <= control_data_in[0];
  174. scale_y <= control_data_in[1];
  175. end
  176. OP_COLORMODE: colormode <= control_data_in[1:0]; // FIXME
  177. OP_VSYNC: vsync_request <= 1; //control_data[0];
  178. OP_MAX: begin
  179. screen_v_max <= control_data_in[31:16];
  180. screen_h_max <= control_data_in[15:0];
  181. end
  182. OP_HS: begin
  183. screen_h_sync_start <= control_data_in[31:16];
  184. screen_h_sync_end <= control_data_in[15:0];
  185. end
  186. OP_VS: begin
  187. screen_v_sync_start <= control_data_in[31:16];
  188. screen_v_sync_end <= control_data_in[15:0];
  189. end
  190. OP_THRESH: begin
  191. end
  192. OP_POLARITY: begin
  193. sync_polarity <= control_data_in[0];
  194. end
  195. OP_RESET: begin
  196. sync_polarity <= 1;
  197. screen_h_max <= 864;
  198. screen_v_max <= 625;
  199. screen_h_sync_start <= 732;
  200. screen_h_sync_end <= 796;
  201. screen_v_sync_start <= 581;
  202. screen_v_sync_end <= 586;
  203. //vsync_request <= 1;
  204. scale_x <= 0;
  205. scale_y <= 1;
  206. screen_width <= 720;
  207. screen_height <= 576;
  208. colormode <= CMODE_32BIT;
  209. end
  210. OP_MISC: begin
  211. //vga_vsync_req_in <= control_data_in[0];
  212. end
  213. endcase
  214. end
  215. reg [31:0] palout;
  216. reg [11:0] vga_v_rez;
  217. reg [11:0] vga_h_rez;
  218. reg [11:0] vga_v_max;
  219. reg [11:0] vga_h_max;
  220. reg [11:0] vga_h_sync_start;
  221. reg [11:0] vga_h_sync_end;
  222. reg [11:0] vga_v_sync_start;
  223. reg [11:0] vga_v_sync_end;
  224. reg [11:0] counter_scanout;
  225. reg [2:0] vga_colormode;
  226. reg [11:0] vga_h_rez_shifted;
  227. reg [11:0] vga_v_rez_shifted;
  228. reg vga_scale_x = 0;
  229. reg [31:0] pixout;
  230. reg [7:0] pixout8;
  231. reg [15:0] pixout16;
  232. reg [31:0] pixout32;
  233. reg [31:0] pixout32_dly;
  234. reg [31:0] pixout32_dly2;
  235. wire [7:0] red16 = {pixout16[4:0], pixout16[4:2]};
  236. wire [7:0] green16 = {pixout16[10:5], pixout16[10:9]};
  237. wire [7:0] blue16 = {pixout16[15:11], pixout16[15:13]};
  238. wire [7:0] red15 = {pixout16[4:0], pixout16[4:2]};
  239. wire [7:0] green15 = {pixout16[9:5], pixout16[9:7]};
  240. wire [7:0] blue15 = {pixout16[14:10], pixout16[14:12]};
  241. reg [3:0] counter_scanout_step; // = 0;
  242. reg [3:0] counter_subpixel = 0;
  243. reg vga_sync_polarity = 0;
  244. always @(posedge dvi_clk) begin
  245. vga_h_rez <= screen_width;
  246. vga_v_rez <= screen_height;
  247. vga_h_max <= screen_h_max;
  248. vga_v_max <= screen_v_max;
  249. vga_h_sync_start <= screen_h_sync_start; // + 4
  250. vga_h_sync_end <= screen_h_sync_end; // + 4
  251. vga_v_sync_start <= screen_v_sync_start;
  252. vga_v_sync_end <= screen_v_sync_end;
  253. vga_scale_x <= scale_x;
  254. vga_colormode <= colormode;
  255. vga_sync_polarity <= sync_polarity;
  256. // FIXME there is some non-determinism in the relationship
  257. // between this process and the fetching process
  258. // depending on when a new screen is launched, there can be
  259. // 1 row of wrap-around
  260. /*
  261. pipelines (4 clocks):
  262. linebuf pixout32 pixout32_dly pixout32_dly2 pixout
  263. linebuf pixout32 pixout16 pixout32_dly pixout
  264. linebuf pixout32 pixout8 palout pixout
  265. */
  266. case ({vga_scale_x,counter_subpixel[2:0]})
  267. 4'b0011: pixout8 <= pixout32[31:24];
  268. 4'b0000: pixout8 <= pixout32[23:16];
  269. 4'b0001: pixout8 <= pixout32[15:8];
  270. 4'b0010: pixout8 <= pixout32[7:0];
  271. 4'b1111: pixout8 <= pixout32[31:24];
  272. 4'b1000: pixout8 <= pixout32[31:24];
  273. 4'b1001: pixout8 <= pixout32[23:16];
  274. 4'b1010: pixout8 <= pixout32[23:16];
  275. 4'b1011: pixout8 <= pixout32[15:8];
  276. 4'b1100: pixout8 <= pixout32[15:8];
  277. 4'b1101: pixout8 <= pixout32[7:0];
  278. 4'b1110: pixout8 <= pixout32[7:0];
  279. endcase
  280. case ({vga_scale_x,counter_subpixel[1:0]})
  281. 3'b001: pixout16 <= {pixout32[23:16],pixout32[31:24]};
  282. 3'b000: pixout16 <= {pixout32[7:0] ,pixout32[15:8] };
  283. 3'b100: pixout16 <= {pixout32[23:16],pixout32[31:24]};
  284. 3'b111: pixout16 <= {pixout32[23:16],pixout32[31:24]};
  285. 3'b110: pixout16 <= {pixout32[7:0] ,pixout32[15:8] };
  286. 3'b101: pixout16 <= {pixout32[7:0] ,pixout32[15:8] };
  287. endcase
  288. case ({vga_scale_x,vga_colormode})
  289. 4'b0000: counter_scanout_step <= 3; // 8 bit
  290. 4'b1000: counter_scanout_step <= 7;
  291. 4'b0001: counter_scanout_step <= 1; // 16 bit
  292. 4'b1001: counter_scanout_step <= 3;
  293. 4'b0010: counter_scanout_step <= 0; // 32 bit
  294. 4'b1010: counter_scanout_step <= 1;
  295. //4'b0100: counter_scanout_step <= 1; // 15 bit
  296. //4'b1100: counter_scanout_step <= 3;
  297. endcase
  298. if (counter_x>vga_h_rez) begin
  299. counter_scanout <= 0;
  300. counter_subpixel <= counter_scanout_step;
  301. end else begin
  302. if (counter_subpixel == 0) begin
  303. counter_subpixel <= counter_scanout_step;
  304. counter_scanout <= counter_scanout + 1'b1;
  305. end else
  306. counter_subpixel <= counter_subpixel - 1'b1;
  307. end
  308. pixout32 <= line_buffer[counter_scanout];
  309. if (vga_colormode==CMODE_16BIT)
  310. // 16 bit 5r6g5b
  311. pixout32_dly <= {8'b0,blue16,green16,red16};
  312. //else if (vga_colormode==CMODE_15BIT)
  313. // // 15 bit 5r5g5b for shapeshifter
  314. // pixout32_dly <= {8'b0,blue15,green15,red15};
  315. else
  316. pixout32_dly <= pixout32;
  317. pixout32_dly2 <= pixout32_dly;
  318. palout <= palette[pixout8];
  319. case (vga_colormode)
  320. CMODE_8BIT: pixout <= palout;
  321. CMODE_16BIT: pixout <= pixout32_dly;
  322. //CMODE_15BIT: pixout <= pixout32_dly;
  323. CMODE_32BIT: pixout <= pixout32_dly2;
  324. endcase
  325. dvi_rgb <= pixout;
  326. if (counter_x > vga_h_max) begin
  327. counter_x <= 0;
  328. if (counter_y > vga_v_max) begin
  329. counter_y <= 0;
  330. end else begin
  331. counter_y <= counter_y + 1'b1;
  332. end
  333. end else begin
  334. counter_x <= counter_x + 1'b1;
  335. end
  336. if (counter_x==vga_h_rez) begin
  337. if (counter_y<vga_v_rez-1'b1)
  338. need_line_fetch <= counter_y + 1'b1;
  339. else
  340. need_line_fetch <= 0;
  341. end
  342. // signal synchronization point to fetch process
  343. if (counter_x<8 && counter_y==vga_v_sync_start)
  344. need_frame_sync <= 1;
  345. else
  346. need_frame_sync <= 0;
  347. if (counter_x>=vga_h_sync_start && counter_x<vga_h_sync_end)
  348. dvi_hsync <= 1^vga_sync_polarity;
  349. else
  350. dvi_hsync <= 0^vga_sync_polarity;
  351. if (counter_y>=vga_v_sync_start && counter_y<vga_v_sync_end)
  352. dvi_vsync <= 1^vga_sync_polarity;
  353. else
  354. dvi_vsync <= 0^vga_sync_polarity;
  355. // 4 clocks pipeline delay
  356. vga_h_rez_shifted <= vga_h_rez+4;
  357. if (counter_y<vga_v_rez && counter_x==4)
  358. dvi_active_video <= 1;
  359. if (counter_x==vga_h_rez_shifted)
  360. dvi_active_video <= 0;
  361. end
  362. endmodule