Firmware for MNT ZZ9000 graphics and ARM coprocessor card for Amiga computers.
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  1. `timescale 1 ns / 1 ps
  2. /*
  3. * MNT ZZ9000 Amiga Graphics and Coprocessor Card Firmware
  4. * Zorro 2/3 AXI4-Lite Interface, 24-bit Video Capture (AXI DMA)
  5. *
  6. * Copyright (C) 2019-2020, Lukas F. Hartmann <lukas@mntre.com>
  7. * MNT Research GmbH, Berlin
  8. * https://mntre.com
  9. *
  10. * Contributors: _Bnu, shanshe
  11. *
  12. * More Info: https://mntre.com/zz9000
  13. *
  14. * SPDX-License-Identifier: GPL-3.0-or-later
  15. * GNU General Public License v3.0 or later
  16. *
  17. * https://spdx.org/licenses/GPL-3.0-or-later.html
  18. *
  19. */
  20. // ZORRO2/3 switch
  21. `define ZORRO2
  22. //`define ZORRO3
  23. // use together with ZORRO2:
  24. //`define VARIANT_ZZ9500
  25. //`define VARIANT_FW20
  26. `define C_S_AXI_DATA_WIDTH 32
  27. `define C_S_AXI_ADDR_WIDTH 4
  28. `define RAM_SIZE 32'h400000 // 4MB for Zorro 2
  29. `define REG_SIZE 32'h01000
  30. `define AUTOCONF_LOW 24'he80000
  31. `define AUTOCONF_HIGH 24'he80080
  32. `define Z3_RAM_SIZE 32'h10000000 // 256MB for Zorro 3
  33. `define ARM_MEMORY_START 32'h001f0000
  34. `define VIDEOCAP_ADDR 32'h01000000 // ARM_MEMORY_START+0xe0_0000
  35. `define C_M00_AXI_TARGET_SLAVE_BASE_ADDR 32'h10000000
  36. `define C_M00_AXI_ID_WIDTH 1
  37. `define C_M00_AXI_ADDR_WIDTH 32
  38. `define C_M00_AXI_DATA_WIDTH 32
  39. `define C_M00_AXI_AWUSER_WIDTH 0
  40. `define C_M00_AXI_ARUSER_WIDTH 0
  41. `define C_M00_AXI_WUSER_WIDTH 0
  42. `define C_M00_AXI_RUSER_WIDTH 0
  43. `define C_M00_AXI_BUSER_WIDTH 0
  44. module MNTZorro_v0_1_S00_AXI
  45. (
  46. output wire arm_interrupt,
  47. inout wire [22:0] ZORRO_ADDR,
  48. inout wire [15:0] ZORRO_DATA,
  49. output wire ZORRO_INT6,
  50. output wire ZORRO_DATADIR,
  51. output wire ZORRO_ADDRDIR,
  52. output wire ZORRO_ADDRDIR2,
  53. output wire ZORRO_NBRN,
  54. input wire ZORRO_NBGN,
  55. input wire ZORRO_READ,
  56. //input wire ZORRO_NMTCR,
  57. input wire ZORRO_NUDS,
  58. input wire ZORRO_NLDS,
  59. input wire ZORRO_NDS1,
  60. input wire ZORRO_NDS0,
  61. input wire ZORRO_NCCS,
  62. input wire ZORRO_NFCS,
  63. input wire ZORRO_DOE,
  64. input wire ZORRO_NIORST,
  65. input wire ZORRO_NCFGIN,
  66. input wire ZORRO_E7M,
  67. input wire ZORRO_C28D,
  68. input wire VCAP_VSYNC,
  69. input wire VCAP_HSYNC,
  70. input wire VCAP_G0,
  71. input wire VCAP_G1,
  72. input wire VCAP_G2,
  73. input wire VCAP_G3,
  74. input wire VCAP_G4,
  75. input wire VCAP_G5,
  76. input wire VCAP_G6,
  77. input wire VCAP_G7,
  78. input wire VCAP_B7,
  79. input wire VCAP_B6,
  80. input wire VCAP_B5,
  81. input wire VCAP_B4,
  82. input wire VCAP_B3,
  83. input wire VCAP_B2,
  84. input wire VCAP_B1,
  85. input wire VCAP_B0,
  86. input wire VCAP_R7,
  87. input wire VCAP_R6,
  88. input wire VCAP_R5,
  89. input wire VCAP_R4,
  90. input wire VCAP_R3,
  91. input wire VCAP_R2,
  92. input wire VCAP_R1,
  93. input wire VCAP_R0,
  94. output wire ZORRO_NCFGOUT,
  95. output wire ZORRO_NSLAVE,
  96. output wire ZORRO_NCINH,
  97. output wire ZORRO_NDTACK,
  98. // HP master interface to write to PS memory directly
  99. input wire m00_axi_aclk,
  100. input wire m00_axi_aresetn,
  101. // write address channel
  102. input wire m00_axi_awready,
  103. output wire [`C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr,
  104. output reg [3:0] m00_axi_awlen,
  105. output reg [2:0] m00_axi_awsize,
  106. output reg [1:0] m00_axi_awburst,
  107. output reg m00_axi_awlock,
  108. output reg [3:0] m00_axi_awcache,
  109. output reg [2:0] m00_axi_awprot,
  110. //output reg [3:0] m00_axi_awqos,
  111. output wire m00_axi_awvalid,
  112. // write channel
  113. input wire m00_axi_wready,
  114. output wire [`C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata,
  115. output wire [`C_M00_AXI_DATA_WIDTH/8-1 : 0] m00_axi_wstrb,
  116. output reg m00_axi_wlast,
  117. output wire m00_axi_wvalid,
  118. // buffered write response channel
  119. input wire [1 : 0] m00_axi_bresp,
  120. input wire m00_axi_bvalid,
  121. output reg m00_axi_bready,
  122. // read address channel
  123. input wire m00_axi_arready,
  124. output reg [`C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
  125. output reg [3 : 0] m00_axi_arlen,
  126. output reg [2 : 0] m00_axi_arsize,
  127. output reg [1 : 0] m00_axi_arburst,
  128. output reg m00_axi_arlock,
  129. output reg [3 : 0] m00_axi_arcache,
  130. output reg [2 : 0] m00_axi_arprot,
  131. //output reg [3 : 0] m00_axi_arqos,
  132. output reg m00_axi_arvalid,
  133. output reg m00_axi_rready,
  134. input wire [`C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
  135. input wire [1 : 0] m00_axi_rresp,
  136. input wire m00_axi_rlast,
  137. input wire m00_axi_rvalid,
  138. // HP master interface 2 to write to PS memory directly (for videocap)
  139. input wire m01_axi_aclk,
  140. input wire m01_axi_aresetn,
  141. // write address channel
  142. input wire m01_axi_awready,
  143. output wire [`C_M00_AXI_ADDR_WIDTH-1 : 0] m01_axi_awaddr,
  144. output reg [7:0] m01_axi_awlen,
  145. output reg [2:0] m01_axi_awsize,
  146. output reg [1:0] m01_axi_awburst,
  147. output reg m01_axi_awlock,
  148. output reg [3:0] m01_axi_awcache,
  149. output reg [2:0] m01_axi_awprot,
  150. output reg [3:0] m01_axi_awqos,
  151. output wire m01_axi_awvalid,
  152. // write channel
  153. input wire m01_axi_wready,
  154. output wire [`C_M00_AXI_DATA_WIDTH-1 : 0] m01_axi_wdata,
  155. output wire [`C_M00_AXI_DATA_WIDTH/8-1 : 0] m01_axi_wstrb,
  156. output reg m01_axi_wlast,
  157. output wire m01_axi_wvalid,
  158. // buffered write response channel
  159. input wire [1 : 0] m01_axi_bresp,
  160. input wire m01_axi_bvalid,
  161. output reg m01_axi_bready,
  162. // video_formatter control interface
  163. output reg [31:0] video_control_data_out,
  164. output reg [7:0] video_control_op_out,
  165. output reg video_control_interlace_out,
  166. input wire video_control_vblank_in,
  167. // Xilinx AXI4-Lite implementation starts here ==============================
  168. // Global Clock Signal
  169. input wire S_AXI_ACLK,
  170. // Global Reset Signal. This Signal is Active LOW
  171. input wire S_AXI_ARESETN,
  172. // Write address (issued by master, acceped by Slave)
  173. input wire [`C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
  174. // Write channel Protection type. This signal indicates the
  175. // privilege and security level of the transaction, and whether
  176. // the transaction is a data access or an instruction access.
  177. input wire [2 : 0] S_AXI_AWPROT,
  178. // Write address valid. This signal indicates that the master signaling
  179. // valid write address and control information.
  180. input wire S_AXI_AWVALID,
  181. // Write address ready. This signal indicates that the slave is ready
  182. // to accept an address and associated control signals.
  183. output wire S_AXI_AWREADY,
  184. // Write data (issued by master, acceped by Slave)
  185. input wire [`C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
  186. // Write strobes. This signal indicates which byte lanes hold
  187. // valid data. There is one write strobe bit for each eight
  188. // bits of the write data bus.
  189. input wire [(`C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
  190. // Write valid. This signal indicates that valid write
  191. // data and strobes are available.
  192. input wire S_AXI_WVALID,
  193. // Write ready. This signal indicates that the slave
  194. // can accept the write data.
  195. output wire S_AXI_WREADY,
  196. // Write response. This signal indicates the status
  197. // of the write transaction.
  198. output wire [1 : 0] S_AXI_BRESP,
  199. // Write response valid. This signal indicates that the channel
  200. // is signaling a valid write response.
  201. output wire S_AXI_BVALID,
  202. // Response ready. This signal indicates that the master
  203. // can accept a write response.
  204. input wire S_AXI_BREADY,
  205. // Read address (issued by master, acceped by Slave)
  206. input wire [`C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
  207. // Protection type. This signal indicates the privilege
  208. // and security level of the transaction, and whether the
  209. // transaction is a data access or an instruction access.
  210. input wire [2 : 0] S_AXI_ARPROT,
  211. // Read address valid. This signal indicates that the channel
  212. // is signaling valid read address and control information.
  213. input wire S_AXI_ARVALID,
  214. // Read address ready. This signal indicates that the slave is
  215. // ready to accept an address and associated control signals.
  216. output wire S_AXI_ARREADY,
  217. // Read data (issued by slave)
  218. output wire [`C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
  219. // Read response. This signal indicates the status of the
  220. // read transfer.
  221. output wire [1 : 0] S_AXI_RRESP,
  222. // Read valid. This signal indicates that the channel is
  223. // signaling the required read data.
  224. output wire S_AXI_RVALID,
  225. // Read ready. This signal indicates that the master can
  226. // accept the read data and response information.
  227. input wire S_AXI_RREADY
  228. );
  229. // AXI4LITE signals
  230. reg [`C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
  231. reg axi_awready;
  232. reg axi_wready;
  233. reg [1 : 0] axi_bresp;
  234. reg axi_bvalid;
  235. reg [`C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
  236. reg axi_arready;
  237. reg [`C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
  238. reg [1 : 0] axi_rresp;
  239. reg axi_rvalid;
  240. // Example-specific design signals
  241. // local localparam for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
  242. // ADDR_LSB is used for addressing 32/64 bit registers/memories
  243. // ADDR_LSB = 2 for 32 bits (n downto 2)
  244. // ADDR_LSB = 3 for 64 bits (n downto 3)
  245. localparam integer ADDR_LSB = (`C_S_AXI_DATA_WIDTH/32) + 1;
  246. localparam integer OPT_MEM_ADDR_BITS = 1;
  247. //----------------------------------------------
  248. //-- Signals for user logic register space example
  249. //------------------------------------------------
  250. //-- Number of Slave Registers 4
  251. reg [`C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
  252. reg [`C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
  253. reg [`C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
  254. reg [`C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
  255. wire slv_reg_rden;
  256. wire slv_reg_wren;
  257. reg [`C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
  258. integer byte_index;
  259. reg aw_en;
  260. reg [`C_S_AXI_DATA_WIDTH-1:0] out_reg0;
  261. reg [`C_S_AXI_DATA_WIDTH-1:0] out_reg1;
  262. reg [`C_S_AXI_DATA_WIDTH-1:0] out_reg2;
  263. reg [`C_S_AXI_DATA_WIDTH-1:0] out_reg3;
  264. // I/O Connections assignments
  265. assign S_AXI_AWREADY = axi_awready;
  266. assign S_AXI_WREADY = axi_wready;
  267. assign S_AXI_BRESP = axi_bresp;
  268. assign S_AXI_BVALID = axi_bvalid;
  269. assign S_AXI_ARREADY = axi_arready;
  270. assign S_AXI_RDATA = axi_rdata;
  271. assign S_AXI_RRESP = axi_rresp;
  272. assign S_AXI_RVALID = axi_rvalid;
  273. // Implement axi_awready generation
  274. // axi_awready is asserted for one S_AXI_ACLK clock cycle when both
  275. // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
  276. // de-asserted when reset is low.
  277. always @( posedge S_AXI_ACLK )
  278. begin
  279. if ( S_AXI_ARESETN == 1'b0 )
  280. begin
  281. axi_awready <= 1'b0;
  282. aw_en <= 1'b1;
  283. end
  284. else
  285. begin
  286. if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
  287. begin
  288. // slave is ready to accept write address when
  289. // there is a valid write address and write data
  290. // on the write address and data bus. This design
  291. // expects no outstanding transactions.
  292. axi_awready <= 1'b1;
  293. aw_en <= 1'b0;
  294. end
  295. else if (S_AXI_BREADY && axi_bvalid)
  296. begin
  297. aw_en <= 1'b1;
  298. axi_awready <= 1'b0;
  299. end
  300. else
  301. begin
  302. axi_awready <= 1'b0;
  303. end
  304. end
  305. end
  306. // Implement axi_awaddr latching
  307. // This process is used to latch the address when both
  308. // S_AXI_AWVALID and S_AXI_WVALID are valid.
  309. always @( posedge S_AXI_ACLK )
  310. begin
  311. if ( S_AXI_ARESETN == 1'b0 )
  312. begin
  313. axi_awaddr <= 0;
  314. end
  315. else
  316. begin
  317. if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
  318. begin
  319. // Write Address latching
  320. axi_awaddr <= S_AXI_AWADDR;
  321. end
  322. end
  323. end
  324. // Implement axi_wready generation
  325. // axi_wready is asserted for one S_AXI_ACLK clock cycle when both
  326. // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
  327. // de-asserted when reset is low.
  328. always @( posedge S_AXI_ACLK )
  329. begin
  330. if ( S_AXI_ARESETN == 1'b0 )
  331. begin
  332. axi_wready <= 1'b0;
  333. end
  334. else
  335. begin
  336. if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
  337. begin
  338. // slave is ready to accept write data when
  339. // there is a valid write address and write data
  340. // on the write address and data bus. This design
  341. // expects no outstanding transactions.
  342. axi_wready <= 1'b1;
  343. end
  344. else
  345. begin
  346. axi_wready <= 1'b0;
  347. end
  348. end
  349. end
  350. // Implement memory mapped register select and write logic generation
  351. // The write data is accepted and written to memory mapped registers when
  352. // axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
  353. // select byte enables of slave registers while writing.
  354. // These registers are cleared when reset (active low) is applied.
  355. // Slave register write enable is asserted when valid address and data are available
  356. // and the slave is ready to accept the write address and write data.
  357. assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
  358. always @( posedge S_AXI_ACLK )
  359. begin
  360. if ( S_AXI_ARESETN == 1'b0 )
  361. begin
  362. slv_reg0 <= 0;
  363. slv_reg1 <= 0;
  364. slv_reg2 <= 0;
  365. slv_reg3 <= 0;
  366. end
  367. else begin
  368. if (slv_reg_wren)
  369. begin
  370. case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
  371. 2'h0:
  372. for ( byte_index = 0; byte_index <= (`C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
  373. if ( S_AXI_WSTRB[byte_index] == 1 ) begin
  374. // Respective byte enables are asserted as per write strobes
  375. // Slave register 0
  376. slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
  377. end
  378. 2'h1:
  379. for ( byte_index = 0; byte_index <= (`C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
  380. if ( S_AXI_WSTRB[byte_index] == 1 ) begin
  381. // Respective byte enables are asserted as per write strobes
  382. // Slave register 1
  383. slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
  384. end
  385. 2'h2:
  386. for ( byte_index = 0; byte_index <= (`C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
  387. if ( S_AXI_WSTRB[byte_index] == 1 ) begin
  388. // Respective byte enables are asserted as per write strobes
  389. // Slave register 2
  390. slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
  391. end
  392. 2'h3:
  393. for ( byte_index = 0; byte_index <= (`C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
  394. if ( S_AXI_WSTRB[byte_index] == 1 ) begin
  395. // Respective byte enables are asserted as per write strobes
  396. // Slave register 3
  397. slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
  398. end
  399. default : begin
  400. slv_reg0 <= slv_reg0;
  401. slv_reg1 <= slv_reg1;
  402. slv_reg2 <= slv_reg2;
  403. slv_reg3 <= slv_reg3;
  404. end
  405. endcase
  406. end
  407. end
  408. end
  409. // Implement write response logic generation
  410. // The write response and response valid signals are asserted by the slave
  411. // when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
  412. // This marks the acceptance of address and indicates the status of
  413. // write transaction.
  414. always @( posedge S_AXI_ACLK )
  415. begin
  416. if ( S_AXI_ARESETN == 1'b0 )
  417. begin
  418. axi_bvalid <= 0;
  419. axi_bresp <= 2'b0;
  420. end
  421. else
  422. begin
  423. if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
  424. begin
  425. // indicates a valid write response is available
  426. axi_bvalid <= 1'b1;
  427. axi_bresp <= 2'b0; // 'OKAY' response
  428. end // work error responses in future
  429. else
  430. begin
  431. if (S_AXI_BREADY && axi_bvalid)
  432. //check if bready is asserted while bvalid is high)
  433. //(there is a possibility that bready is always asserted high)
  434. begin
  435. axi_bvalid <= 1'b0;
  436. end
  437. end
  438. end
  439. end
  440. // Implement axi_arready generation
  441. // axi_arready is asserted for one S_AXI_ACLK clock cycle when
  442. // S_AXI_ARVALID is asserted. axi_awready is
  443. // de-asserted when reset (active low) is asserted.
  444. // The read address is also latched when S_AXI_ARVALID is
  445. // asserted. axi_araddr is reset to zero on reset assertion.
  446. always @( posedge S_AXI_ACLK )
  447. begin
  448. if ( S_AXI_ARESETN == 1'b0 )
  449. begin
  450. axi_arready <= 1'b0;
  451. axi_araddr <= 32'b0;
  452. end
  453. else
  454. begin
  455. if (~axi_arready && S_AXI_ARVALID)
  456. begin
  457. // indicates that the slave has acceped the valid read address
  458. axi_arready <= 1'b1;
  459. // Read address latching
  460. axi_araddr <= S_AXI_ARADDR;
  461. end
  462. else
  463. begin
  464. axi_arready <= 1'b0;
  465. end
  466. end
  467. end
  468. // Implement axi_arvalid generation
  469. // axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
  470. // S_AXI_ARVALID and axi_arready are asserted. The slave registers
  471. // data are available on the axi_rdata bus at this instance. The
  472. // assertion of axi_rvalid marks the validity of read data on the
  473. // bus and axi_rresp indicates the status of read transaction.axi_rvalid
  474. // is deasserted on reset (active low). axi_rresp and axi_rdata are
  475. // cleared to zero on reset (active low).
  476. always @( posedge S_AXI_ACLK )
  477. begin
  478. if ( S_AXI_ARESETN == 1'b0 )
  479. begin
  480. axi_rvalid <= 0;
  481. axi_rresp <= 0;
  482. end
  483. else
  484. begin
  485. if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
  486. begin
  487. // Valid read data is available at the read data bus
  488. axi_rvalid <= 1'b1;
  489. axi_rresp <= 2'b0; // 'OKAY' response
  490. end
  491. else if (axi_rvalid && S_AXI_RREADY)
  492. begin
  493. // Read data is accepted by the master
  494. axi_rvalid <= 1'b0;
  495. end
  496. end
  497. end
  498. // Output register or memory read data
  499. always @( posedge S_AXI_ACLK )
  500. begin
  501. if ( S_AXI_ARESETN == 1'b0 )
  502. begin
  503. axi_rdata <= 0;
  504. end
  505. else
  506. begin
  507. // When there is a valid read address (S_AXI_ARVALID) with
  508. // acceptance of read address by the slave (axi_arready),
  509. // output the read dada
  510. if (slv_reg_rden)
  511. begin
  512. axi_rdata <= reg_data_out; // register read data
  513. end
  514. end
  515. end
  516. // end of AXI-Lite interface ==================================================
  517. (* mark_debug = "true" *) reg [4:0] znAS_sync;
  518. (* mark_debug = "true" *) reg [2:0] znUDS_sync;
  519. (* mark_debug = "true" *) reg [2:0] znLDS_sync;
  520. (* mark_debug = "true" *) reg [2:0] zREAD_sync;
  521. (* mark_debug = "true" *) reg [4:0] znFCS_sync;
  522. (* mark_debug = "true" *) reg [2:0] znDS1_sync;
  523. (* mark_debug = "true" *) reg [2:0] znDS0_sync;
  524. reg [1:0] znRST_sync;
  525. (* mark_debug = "true" *) reg [1:0] zDOE_sync;
  526. (* mark_debug = "true" *) reg [4:0] zE7M_sync;
  527. reg [2:0] znCFGIN_sync;
  528. (* mark_debug = "true" *) reg [23:0] zaddr; // zorro 2 address
  529. (* mark_debug = "true" *) reg [23:0] zaddr_sync;
  530. (* mark_debug = "true" *) reg [23:0] zaddr_sync2;
  531. (* mark_debug = "true" *) reg [15:0] zdata_in_sync;
  532. (* mark_debug = "true" *) reg [15:0] zdata_in_sync2;
  533. reg z2_addr_valid;
  534. reg [23:0] z2_mapped_addr;
  535. reg z2_read;
  536. reg z2_write;
  537. reg z2_datastrobe_synced;
  538. reg z2addr_in_ram;
  539. reg z2addr_in_reg;
  540. reg z2addr_autoconfig;
  541. reg [31:0] ram_low ;//= 32'h600000;
  542. reg [31:0] ram_high ;//= 32'ha00000;
  543. reg [31:0] reg_low ;//= 32'h601000;
  544. reg [31:0] reg_high ;//= 32'h602000;
  545. reg z2_uds;
  546. reg z2_lds;
  547. reg [31:0] z3_ram_low ;//= 32'h50000000;
  548. reg [31:0] z3_ram_high ;//= 32'h50000000 + `Z3_RAM_SIZE -4;
  549. reg [31:0] z3_reg_low ;//= 32'h50001000;
  550. reg [31:0] z3_reg_high ;//= 32'h50002000;
  551. reg [15:0] data_z3_hi16;
  552. reg [15:0] data_z3_low16;
  553. (* mark_debug = "true" *) reg [15:0] data_z3_hi16_latched;
  554. (* mark_debug = "true" *) reg [15:0] data_z3_low16_latched;
  555. (* mark_debug = "true" *) reg [15:0] z3_din_high_s2;
  556. (* mark_debug = "true" *) reg [15:0] z3_din_low_s2;
  557. (* mark_debug = "true" *) reg [31:0] z3addr;
  558. (* mark_debug = "true" *) reg [31:0] last_z3addr;
  559. (* mark_debug = "true" *) reg [31:0] z3addr2;
  560. (* mark_debug = "true" *) reg [31:0] z3_mapped_addr;
  561. (* mark_debug = "true" *) reg [31:0] z3_read_addr;
  562. (* mark_debug = "true" *) reg [15:0] z3_read_data;
  563. reg z3_din_latch;
  564. (* mark_debug = "true" *) reg z3_fcs_state;
  565. (* mark_debug = "true" *) reg z3_end_cycle;
  566. (* mark_debug = "true" *) reg z3addr_in_ram;
  567. (* mark_debug = "true" *) reg z3addr_in_reg;
  568. (* mark_debug = "true" *) reg z3addr_autoconfig;
  569. `ifdef ZORRO3
  570. reg ZORRO3 = 1;
  571. `else
  572. reg ZORRO3 = 0;
  573. `endif
  574. (* mark_debug = "true" *) reg dataout;
  575. (* mark_debug = "true" *) reg dataout_z3;
  576. (* mark_debug = "true" *) reg dataout_enable;
  577. (* mark_debug = "true" *) reg slaven;
  578. (* mark_debug = "true" *) reg dtack;
  579. reg z_reset;
  580. reg z_reset_delayed;
  581. reg z_cfgin;
  582. reg z_cfgin_lo;
  583. reg z3_confdone;
  584. reg zorro_read;
  585. reg zorro_write;
  586. reg zorro_interrupt;
  587. assign ZORRO_INT6 = zorro_interrupt;
  588. reg [15:0] data_in;
  589. reg [31:0] rr_data;
  590. reg [15:0] data_out;
  591. reg [15:0] regdata_in;
  592. // ram arbiter
  593. (* mark_debug = "true" *) reg zorro_ram_read_request;
  594. (* mark_debug = "true" *) reg zorro_ram_write_request;
  595. reg [31:0] zorro_ram_read_addr;
  596. reg [3:0] zorro_ram_read_bytes;
  597. reg [31:0] zorro_ram_write_addr;
  598. reg [31:0] zorro_ram_write_data;
  599. reg [3:0] zorro_ram_write_bytes;
  600. reg [15:0] default_data = 'hffff; // causes read/write glitches on A2000 (data bus interference) when 0
  601. reg [1:0] zorro_write_capture_bytes;
  602. reg [15:0] zorro_write_capture_data;
  603. // z3 strobes
  604. reg z3_ds3;
  605. reg z3_ds2;
  606. reg z3_ds1;
  607. reg z3_ds0;
  608. // level shifter direction pins
  609. assign ZORRO_DATADIR = ZORRO_DOE & (dataout_enable | dataout_z3); // d2-d9 d10-15, d0-d1
  610. assign ZORRO_ADDRDIR = ZORRO_DOE & (dataout_z3); // a16-a23 <- input a8-a15 <- input
  611. assign ZORRO_ADDRDIR2 = 0; //ZORRO_DOE & (dataout_z3_latched);
  612. assign ZORRO_NBRN = 1; // TODO busmastering
  613. // data/addr out signals are gated by master's DOE signal
  614. wire ZORRO_DATA_T = ~(ZORRO_DOE & (dataout_enable | dataout_z3));
  615. wire ZORRO_ADDR_T = ~(ZORRO_DOE & dataout_z3);
  616. reg z_ovr = 0;
  617. assign ZORRO_NCINH = z_ovr?1'b1:1'b0; // inverse
  618. // "slave" signals are gated by master's FCS signal
  619. assign ZORRO_NSLAVE = (ZORRO_DOE & slaven)?1'b0:1'b1; // cannot gate by FCS for Z2
  620. assign ZORRO_NDTACK = (ZORRO_DOE & dtack) ?1'b1:1'b0; // inverse, pull-down transistor on output
  621. wire [22:0] z3_addr_out = {data_z3_low16_latched, 7'bZZZ_ZZZZ}; // FIXME this creates tri-cell warning?
  622. //wire [22:0] z3_addr_out = {data_z3_low16_latched, 7'b111_1111}; // FIXME this creates tri-cell warning?
  623. wire [15:0] ZORRO_DATA_IN;
  624. wire [22:0] ZORRO_ADDR_IN;
  625. genvar i;
  626. generate
  627. for (i=0; i < 16; i=i+1) begin : ZORRO_DATABUS
  628. IOBUF u_iobuf_dq
  629. (
  630. .I (ZORRO3 ? data_z3_hi16_latched[i] : data_out[i]),
  631. .T (ZORRO_DATA_T),
  632. .IO (ZORRO_DATA[i]),
  633. .O (ZORRO_DATA_IN[i])
  634. );
  635. end
  636. endgenerate
  637. generate
  638. for (i=0; i < 23; i=i+1) begin : ZORRO_ADDRBUS
  639. IOBUF u_iobuf_dq
  640. (
  641. .I (z3_addr_out[i]),
  642. .T (ZORRO_ADDR_T),
  643. .IO (ZORRO_ADDR[i]),
  644. .O (ZORRO_ADDR_IN[i])
  645. );
  646. end
  647. endgenerate
  648. // autoconf output signal
  649. reg z_confout = 0;
  650. assign ZORRO_NCFGOUT = ZORRO_NCFGIN?1'b1:(~z_confout);
  651. reg [7:0] video_debug_reg;
  652. assign arm_interrupt = zorro_ram_write_request | zorro_ram_read_request;
  653. // -- synchronizers ------------------------------------------
  654. always @(posedge S_AXI_ACLK) begin
  655. znUDS_sync <= {znUDS_sync[1:0],ZORRO_NUDS};
  656. znLDS_sync <= {znLDS_sync[1:0],ZORRO_NLDS};
  657. znAS_sync <= {znAS_sync[3:0],ZORRO_NCCS};
  658. zREAD_sync <= {zREAD_sync[1:0],ZORRO_READ};
  659. znDS1_sync <= {znDS1_sync[1:0],ZORRO_NDS1};
  660. znDS0_sync <= {znDS0_sync[1:0],ZORRO_NDS0};
  661. znFCS_sync <= {znFCS_sync[3:0],ZORRO_NFCS};
  662. znCFGIN_sync<= {znCFGIN_sync[1:0],ZORRO_NCFGIN};
  663. zDOE_sync <= {zDOE_sync[0],ZORRO_DOE};
  664. znRST_sync <= {znRST_sync[0],ZORRO_NIORST};
  665. // Z2 ------------------------------------------------
  666. `ifndef ZORRO3
  667. // READ and nAS can happen dangerously close to each other. so we delay
  668. // the recognition of a valid Z2 cycle 2 clocks more than the other signals.
  669. z2_addr_valid <= (znAS_sync[4]==0 && znAS_sync[3]==0);
  670. zaddr <= ZORRO_ADDR_IN[22:0];
  671. zaddr_sync <= zaddr;
  672. zaddr_sync2 <= zaddr_sync;
  673. z2_mapped_addr <= {zaddr_sync2[22:0],1'b0};
  674. z2_read <= (zREAD_sync[2] == 1'b1); // FIXME was 0
  675. z2_write <= (zREAD_sync[2] == 1'b0); // FIXME was 0
  676. z2_datastrobe_synced <= ((znUDS_sync[2]==0 && znUDS_sync[1]==0) || (znLDS_sync[2]==0 && znLDS_sync[1]==0));
  677. z2_uds <= (znUDS_sync[2]==0 && znUDS_sync[1]==0);
  678. z2_lds <= (znLDS_sync[2]==0 && znLDS_sync[1]==0);
  679. z2addr_in_ram <= (z2_mapped_addr>=ram_low && z2_mapped_addr<ram_high);
  680. z2addr_in_reg <= (z2_mapped_addr>=reg_low && z2_mapped_addr<reg_high);
  681. // FIXME was 1
  682. if (znAS_sync[4]==0 && z2_mapped_addr>=`AUTOCONF_LOW && z2_mapped_addr<`AUTOCONF_HIGH)
  683. z2addr_autoconfig <= 1'b1;
  684. else
  685. z2addr_autoconfig <= 1'b0;
  686. `endif
  687. // Z3 ------------------------------------------------
  688. `ifdef ZORRO3
  689. // sample z3addr on falling edge of /FCS
  690. // according to Z3 spec, we have max 25ns to react to falling FCS.
  691. case (znFCS_sync[1:0])
  692. 2'b01: begin
  693. z3_fcs_state <= 1;
  694. z3addr <= 0;
  695. end
  696. 2'b10: begin
  697. z3_fcs_state <= 0;
  698. z3addr <= z3addr2;
  699. end
  700. endcase
  701. z3addr2 <= {ZORRO_DATA_IN[15:8],ZORRO_ADDR_IN[22:1],2'b00};
  702. z3addr_in_ram <= (z3addr >= z3_ram_low) && (z3addr < z3_ram_high);
  703. z3addr_in_reg <= (z3addr >= z3_reg_low) && (z3addr < z3_reg_high);
  704. z3_ds0 <= ~znDS0_sync[1];
  705. z3_ds1 <= ~znDS1_sync[1];
  706. z3_ds2 <= ~znLDS_sync[1];
  707. z3_ds3 <= ~znUDS_sync[1];
  708. z3addr_autoconfig <= (z3addr[31:16]=='hff00);
  709. z3_mapped_addr <= (z3addr-z3_ram_low);
  710. z3_din_high_s2 <= ZORRO_DATA_IN; //zD[15:0];
  711. z3_din_low_s2 <= ZORRO_ADDR_IN[22:7]; //zA[22:7];
  712. // pipelined for better timing
  713. data_z3_hi16_latched <= data_z3_hi16;
  714. data_z3_low16_latched <= data_z3_low16;
  715. `endif
  716. zdata_in_sync2 <= ZORRO_DATA_IN;
  717. zdata_in_sync <= zdata_in_sync2;
  718. zorro_read <= zREAD_sync[0];
  719. zorro_write <= ~zREAD_sync[0];
  720. z_reset_delayed <= (znRST_sync==2'b00);
  721. z_reset <= z_reset_delayed;
  722. z_cfgin <= (znCFGIN_sync==3'b000);
  723. z_cfgin_lo <= (znCFGIN_sync==3'b111);
  724. //video_debug_reg <= video_debug;
  725. end // always @ (posedge S_AXI_ACLK)
  726. reg [15:0] REVISION = 'h7a09; // z9
  727. // main FSM
  728. localparam RESET = 0;
  729. localparam Z2_CONFIGURING = 1;
  730. localparam Z2_IDLE = 2;
  731. localparam WAIT_WRITE = 3;
  732. localparam WAIT_WRITE2 = 4;
  733. localparam Z2_WRITE_FINALIZE = 5;
  734. localparam WAIT_READ = 6;
  735. localparam WAIT_READ2 = 7;
  736. localparam WAIT_READ3 = 8;
  737. localparam CONFIGURED = 9;
  738. localparam CONFIGURED_CLEAR = 10;
  739. localparam DECIDE_Z2_Z3 = 11;
  740. localparam Z3_IDLE = 12;
  741. localparam Z3_WRITE_UPPER = 13;
  742. localparam Z3_WRITE_LOWER = 14;
  743. localparam Z3_READ_UPPER = 15;
  744. localparam Z3_READ_LOWER = 16;
  745. localparam Z3_READ_DELAY = 17;
  746. localparam Z3_READ_DELAY1 = 18;
  747. localparam Z3_READ_DELAY2 = 19;
  748. localparam Z3_WRITE_PRE = 20;
  749. localparam Z3_WRITE_FINALIZE = 21;
  750. localparam Z3_ENDCYCLE = 22;
  751. localparam Z3_DTACK = 23;
  752. localparam Z3_CONFIGURING = 24;
  753. localparam Z2_REGWRITE = 25;
  754. localparam REGWRITE = 26;
  755. localparam REGREAD = 27;
  756. localparam Z2_REGREAD_POST = 28;
  757. localparam Z3_REGREAD_POST = 29;
  758. localparam Z3_REGWRITE = 30;
  759. localparam Z2_REGREAD = 31;
  760. localparam Z3_REGREAD = 32;
  761. localparam Z2_PRE_CONFIGURED = 34;
  762. localparam Z2_ENDCYCLE = 35;
  763. localparam WAIT_WRITE_DMA_Z2 = 36;
  764. localparam WAIT_WRITE_DMA_Z2_FINALIZE = 37;
  765. localparam RESET_DVID = 39;
  766. localparam COLD = 40;
  767. localparam WAIT_READ2B = 41; // delay states
  768. localparam WAIT_READ2C = 42;
  769. localparam WAIT_READ2D = 54;
  770. localparam WAIT_WRITE_DMA_Z3 = 43;
  771. localparam WAIT_WRITE_DMA_Z3_FINALIZE = 44;
  772. localparam Z3_AUTOCONF_READ = 45;
  773. localparam Z3_AUTOCONF_WRITE = 46;
  774. localparam Z3_AUTOCONF_READ_DLY = 47;
  775. localparam Z3_AUTOCONF_READ_DLY2 = 48;
  776. localparam Z3_REGWRITE_PRE = 49;
  777. localparam Z3_REGREAD_PRE = 50;
  778. localparam Z3_WRITE_PRE2 = 51;
  779. localparam WAIT_WRITE_DMA_Z3B = 52;
  780. localparam WAIT_WRITE_DMA_Z3C = 53;
  781. localparam WAIT_READ_DMA_Z3 = 54;
  782. localparam WAIT_READ_DMA_Z3B = 55;
  783. localparam WAIT_READ_DMA_Z3C = 56;
  784. (* mark_debug = "true" *) reg [7:0] zorro_state = COLD;
  785. reg zorro_idle;
  786. reg [7:0] read_counter; // used by Z3
  787. reg [5:0] dtack_timeout = 6; // number of cycles before we turn off our dtack signal
  788. reg [7:0] dataout_time = 'h02;
  789. reg [7:0] datain_time = 'h10;
  790. reg [7:0] datain_counter = 0;
  791. reg [23:0] last_addr;
  792. reg [23:0] last_read_addr;
  793. reg [15:0] last_data;
  794. reg [15:0] last_read_data;
  795. reg [15:0] zaddr_regpart;
  796. reg [15:0] z3addr_regpart;
  797. reg [15:0] regread_addr;
  798. reg [15:0] regwrite_addr;
  799. reg [31:0] axi_reg0;
  800. reg [31:0] axi_reg1;
  801. reg [31:0] axi_reg2;
  802. reg [31:0] axi_reg3;
  803. reg [31:0] video_control_data_zorro;
  804. reg [7:0] video_control_op_zorro;
  805. reg [31:0] video_control_data_axi;
  806. reg [7:0] video_control_op_axi;
  807. reg video_control_axi;
  808. reg [31:0] video_control_data; // to output
  809. reg [7:0] video_control_op; // to output
  810. reg video_control_vblank; // from input
  811. reg video_control_interlace;
  812. reg zorro_ram_read_flag;
  813. reg zorro_ram_write_flag ;
  814. reg videocap_mode;
  815. reg videocap_mode_in;
  816. (* mark_debug = "true" *) reg [6:0] videocap_hs;
  817. (* mark_debug = "true" *) reg [6:0] videocap_vs;
  818. reg [23:0] videocap_rgbin = 0;
  819. (* mark_debug = "true" *) reg [9:0] videocap_x;
  820. (* mark_debug = "true" *) reg [9:0] videocap_y;
  821. (* mark_debug = "true" *) reg [9:0] videocap_x2;
  822. (* mark_debug = "true" *) reg videocap_x_done;
  823. (* mark_debug = "true" *) reg [9:0] videocap_y2;
  824. (* mark_debug = "true" *) reg [9:0] videocap_y_sync;
  825. (* mark_debug = "true" *) reg [9:0] videocap_ymax;
  826. (* mark_debug = "true" *) reg [9:0] videocap_ymax2;
  827. (* mark_debug = "true" *) reg [9:0] videocap_ymax_sync;
  828. (* mark_debug = "true" *) reg [9:0] videocap_y3;
  829. reg vc_next_lace_field = 0;
  830. reg [3:0] vc_shortlines = 0;
  831. parameter VCAPW = 799;
  832. reg [31:0] videocap_buf [0:VCAPW];
  833. reg videocap_lace_field;
  834. (* mark_debug = "true" *) reg videocap_interlace;
  835. (* mark_debug = "true" *) reg videocap_ntsc;
  836. (* mark_debug = "true" *) reg [7:0] videocap_hs_pulse_width;
  837. reg E7M_PSEN = 0;
  838. reg E7M_PSINCDEC = 0;
  839. wire clkfbout_zz9000_ps_clk_wiz_1_0;
  840. wire e7m_shifted;
  841. wire e7m_shifted180;
  842. // video capture clock adjustment
  843. MMCME2_ADV #(
  844. .BANDWIDTH("OPTIMIZED"),
  845. .CLKFBOUT_MULT_F(32.000000),
  846. .CLKFBOUT_PHASE(0.000000),
  847. .CLKFBOUT_USE_FINE_PS("TRUE"),
  848. .CLKIN1_PERIOD(35.000000),
  849. .CLKIN2_PERIOD(0.000000),
  850. .CLKOUT0_DIVIDE_F(16.000000),
  851. .CLKOUT0_DUTY_CYCLE(0.500000),
  852. `ifdef ZORRO3
  853. .CLKOUT0_PHASE(0.000000),
  854. `elsif VARIANT_ZZ9500
  855. .CLKOUT0_PHASE(90.000000),
  856. `else
  857. .CLKOUT0_PHASE(315.000000),
  858. `endif
  859. .CLKOUT0_USE_FINE_PS("TRUE"),
  860. .CLKOUT1_DIVIDE(32),
  861. .CLKOUT1_DUTY_CYCLE(0.500000),
  862. `ifdef ZORRO3
  863. .CLKOUT1_PHASE(0.000000),
  864. `elsif VARIANT_ZZ9500
  865. .CLKOUT1_PHASE(270.000000),
  866. `else
  867. .CLKOUT1_PHASE(135.000000),
  868. `endif
  869. .CLKOUT1_USE_FINE_PS("TRUE"),
  870. .COMPENSATION("ZHOLD"),
  871. .DIVCLK_DIVIDE(1),
  872. .IS_CLKINSEL_INVERTED(1'b0),
  873. .IS_PSEN_INVERTED(1'b0),
  874. .IS_PSINCDEC_INVERTED(1'b0),
  875. .IS_PWRDWN_INVERTED(1'b0),
  876. .IS_RST_INVERTED(1'b0),
  877. .REF_JITTER1(0.001000),
  878. .REF_JITTER2(0.001000),
  879. .SS_EN("FALSE"),
  880. .SS_MODE("CENTER_HIGH"),
  881. .SS_MOD_PERIOD(10000),
  882. .STARTUP_WAIT("FALSE"))
  883. mmcm_adv_inst
  884. (.CLKFBIN(clkfbout_zz9000_ps_clk_wiz_1_0),
  885. .CLKFBOUT(clkfbout_zz9000_ps_clk_wiz_1_0),
  886. //.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
  887. //.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
  888. .CLKIN1(ZORRO_E7M),
  889. .CLKIN2(1'b0),
  890. .CLKINSEL(1'b1),
  891. //.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
  892. .CLKOUT0(e7m_shifted),
  893. //.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
  894. .CLKOUT1(e7m_shifted180),
  895. //.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
  896. .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
  897. .DCLK(1'b0),
  898. .DEN(1'b0),
  899. .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
  900. //.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
  901. //.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
  902. .DWE(1'b0),
  903. //.LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED),
  904. .PSCLK(S_AXI_ACLK),
  905. //.PSDONE(psdone),
  906. .PSEN(E7M_PSEN),
  907. .PSINCDEC(E7M_PSINCDEC),
  908. .PWRDWN(1'b0),
  909. .RST(1'b0));
  910. always @(posedge e7m_shifted) begin
  911. videocap_vs <= {videocap_vs[5:0], VCAP_VSYNC};
  912. videocap_hs <= {videocap_hs[5:0], VCAP_HSYNC};
  913. `ifdef VARIANT_ZZ9500
  914. videocap_rgbin <= {VCAP_R3,VCAP_R2,VCAP_R1,VCAP_R0,VCAP_R3,VCAP_R2,VCAP_R1,VCAP_R0,
  915. VCAP_G3,VCAP_G2,VCAP_G1,VCAP_G0,VCAP_G3,VCAP_G2,VCAP_G1,VCAP_G0,
  916. VCAP_B3,VCAP_B2,VCAP_B1,VCAP_B0,VCAP_B3,VCAP_B2,VCAP_B1,VCAP_B0};
  917. `elsif ZORRO2
  918. videocap_rgbin <= {VCAP_R7,VCAP_R6,VCAP_R5,VCAP_R4,VCAP_R7,VCAP_R6,VCAP_R5,VCAP_R4,
  919. VCAP_G7,VCAP_G6,VCAP_G5,VCAP_G4,VCAP_G7,VCAP_G6,VCAP_G5,VCAP_G4,
  920. VCAP_B7,VCAP_B6,VCAP_B5,VCAP_B4,VCAP_B7,VCAP_B6,VCAP_B5,VCAP_B4};
  921. `else
  922. videocap_rgbin <= {VCAP_R7,VCAP_R6,VCAP_R5,VCAP_R4,VCAP_R3,VCAP_R2,VCAP_R1,VCAP_R0,
  923. VCAP_G7,VCAP_G6,VCAP_G5,VCAP_G4,VCAP_G3,VCAP_G2,VCAP_G1,VCAP_G0,
  924. VCAP_B7,VCAP_B6,VCAP_B5,VCAP_B4,VCAP_B3,VCAP_B2,VCAP_B1,VCAP_B0};
  925. `endif
  926. if (videocap_hs==0) begin
  927. if (videocap_hs_pulse_width<'hff)
  928. videocap_hs_pulse_width<=videocap_hs_pulse_width+1;
  929. end else if (videocap_hs=='b111111)
  930. videocap_hs_pulse_width<=0;
  931. `ifdef VARIANT_ZZ9500
  932. // on A500, HSYNC is really CSYNC and we can recognize vertical sync
  933. // by looking at the pulse width of it
  934. // direct sampling from denise
  935. if(videocap_hs[6:1]=='b000111 && videocap_hs_pulse_width>=128) begin
  936. if (videocap_ymax[0]) begin
  937. videocap_interlace <= 1;
  938. end else begin
  939. videocap_interlace <= 0;
  940. end
  941. videocap_lace_field <= vc_next_lace_field;
  942. if (videocap_ymax>='h130)
  943. videocap_ntsc <= 0;
  944. else
  945. videocap_ntsc <= 1;
  946. if (videocap_interlace) begin
  947. videocap_y2 <= 0;
  948. videocap_y3 <= vc_next_lace_field;
  949. end else begin
  950. videocap_y2 <= 0;
  951. videocap_y3 <= 0;
  952. end
  953. `else
  954. // with videoslot machines, we have a real VSYNC to work with
  955. if (videocap_vs[6:1]=='b111000) begin
  956. if (videocap_ymax[0]!=videocap_ymax2[0])
  957. videocap_interlace <= 1;
  958. else
  959. videocap_interlace <= 0;
  960. videocap_lace_field <= videocap_ymax[0];
  961. if (videocap_ymax>='h138)
  962. videocap_ntsc <= 0;
  963. else
  964. videocap_ntsc <= 1;
  965. if (videocap_interlace) begin
  966. videocap_y2 <= 0;
  967. videocap_y3 <= videocap_lace_field;
  968. end else begin
  969. videocap_y2 <= 0;
  970. videocap_y3 <= 0;
  971. end
  972. `endif
  973. if (videocap_y2!=0) begin
  974. videocap_ymax <= videocap_y2;
  975. videocap_ymax2 <= videocap_ymax;
  976. end
  977. end else if (videocap_hs[6:1]=='b000111) begin
  978. videocap_x <= 0;
  979. videocap_x2 <= 0;
  980. `ifdef VARIANT_ZZ9500
  981. if (videocap_hs_pulse_width < 'h20) begin
  982. // count short pulses terminating lines
  983. vc_shortlines <= vc_shortlines+1;
  984. if (vc_shortlines==0) begin
  985. // first time
  986. if (videocap_x>='h200)
  987. // last line was long?
  988. vc_next_lace_field <= 1;
  989. else
  990. vc_next_lace_field <= 0;
  991. end
  992. end else
  993. vc_shortlines <= 0;
  994. `endif
  995. if (videocap_y2>'h1a) begin
  996. if (videocap_interlace)
  997. videocap_y3 <= videocap_y3 + 2'b10;
  998. else
  999. videocap_y3 <= videocap_y3 + 1'b1;
  1000. end
  1001. videocap_y2 <= videocap_y2 + 1'b1;
  1002. end else if (videocap_x2<'h5e) begin // 5a worked
  1003. // left crop
  1004. videocap_x2 <= videocap_x2 + 1'b1;
  1005. end else begin
  1006. videocap_x <= videocap_x + 1'b1;
  1007. end
  1008. if (videocap_x>2)
  1009. videocap_buf[videocap_x] <= videocap_rgbin;
  1010. else
  1011. videocap_buf[videocap_x] <= 0;
  1012. if (videocap_x>'h200)
  1013. videocap_x_done <= 1;
  1014. else
  1015. videocap_x_done <= 0;
  1016. end
  1017. reg [11:0] videocap_save_x;
  1018. reg [11:0] videocap_save_x2;
  1019. reg [11:0] videocap_save_x3;
  1020. reg [11:0] videocap_yoffset;
  1021. reg [11:0] videocap_xoffset;
  1022. reg [11:0] videocap_pitch;
  1023. reg [11:0] videocap_pitch_sync;
  1024. reg [11:0] videocap_pitch_snoop;
  1025. reg videocap_pitch_snooped;
  1026. reg [9:0] videocap_save_line_done;
  1027. reg [11:0] videocap_save_y;
  1028. reg [31:0] videocap_save_y2;
  1029. reg [31:0] videocap_save_addr;
  1030. reg [3:0] videocap_save_state;
  1031. reg videocap_mode_sync;
  1032. reg [31:0] m01_axi_awaddr_out;
  1033. reg [31:0] m01_axi_wdata_out;
  1034. reg m01_axi_awvalid_out = 0;
  1035. reg m01_axi_wvalid_out = 0;
  1036. reg [31:0] m00_axi_awaddr_z3;
  1037. reg [31:0] m00_axi_wdata_z3;
  1038. reg m00_axi_awvalid_z3 = 0;
  1039. reg m00_axi_wvalid_z3 = 0;
  1040. reg [3:0] m00_axi_wstrb_z3;
  1041. assign m00_axi_awaddr = m00_axi_awaddr_z3;
  1042. assign m00_axi_awvalid = m00_axi_awvalid_z3;
  1043. assign m00_axi_wdata = m00_axi_wdata_z3;
  1044. assign m00_axi_wstrb = m00_axi_wstrb_z3;
  1045. assign m00_axi_wvalid = m00_axi_wvalid_z3;
  1046. assign m01_axi_awaddr = m01_axi_awaddr_out;
  1047. assign m01_axi_awvalid = m01_axi_awvalid_out;
  1048. assign m01_axi_wdata = m01_axi_wdata_out;
  1049. assign m01_axi_wstrb = 4'b1111;
  1050. assign m01_axi_wvalid = m01_axi_wvalid_out;
  1051. // AXI DMA defaults
  1052. always @(posedge S_AXI_ACLK) begin
  1053. m00_axi_awlen <= 'h0; // 1 burst (1 write)
  1054. m00_axi_awsize <= 'h2; // 2^2 == 4 bytes
  1055. m00_axi_awburst <= 'h0; // FIXED (non incrementing)
  1056. m00_axi_awcache <= 'h3;
  1057. m00_axi_awlock <= 'h0;
  1058. m00_axi_awprot <= 'h0;
  1059. //m00_axi_awqos <= 'h0;
  1060. m00_axi_wlast <= 'h1;
  1061. m00_axi_bready <= 'h1;
  1062. m00_axi_arlen <= 'h0;
  1063. m00_axi_arsize <= 'h2;
  1064. m00_axi_arburst <= 'h0;
  1065. m00_axi_arcache <= 'hf; //was 3
  1066. m00_axi_arlock <= 'h0;
  1067. m00_axi_arprot <= 'h0;
  1068. //m00_axi_arqos <= 'h0;
  1069. m00_axi_rready <= 1;
  1070. // FIXME this could use bursts
  1071. m01_axi_awlen <= 'h0; // 1 burst (1 write)
  1072. m01_axi_awsize <= 'h2; //'h2; // 2^2 == 4 bytes
  1073. m01_axi_awburst <= 'h0; // FIXED (non incrementing)
  1074. m01_axi_awcache <= 'h0;
  1075. m01_axi_awlock <= 'h0;
  1076. m01_axi_awprot <= 'h0;
  1077. m01_axi_awqos <= 'h0;
  1078. m01_axi_wlast <= 'h1;
  1079. m01_axi_bready <= 'h1;
  1080. `ifdef ZORRO2
  1081. // ZORRO2 doesn't implement AXI DMA read yet
  1082. m00_axi_araddr <= 0;
  1083. m00_axi_arvalid <= 0;
  1084. m00_axi_rready <= 0;
  1085. `endif
  1086. end
  1087. reg [9:0] videocap_x_sync;
  1088. reg [9:0] vc_saving_line;
  1089. reg [9:0] videocap_y_sync2;
  1090. // pipeline stages for videocap save addr calculation
  1091. reg [31:0] vc_saveaddr1;
  1092. reg [31:0] vc_saveaddr2;
  1093. always @(posedge S_AXI_ACLK) begin
  1094. // VIDEOCAP
  1095. // pass interlace mode to video control block
  1096. video_control_interlace <= videocap_interlace;
  1097. videocap_pitch_sync <= videocap_pitch;
  1098. //videocap_x_sync <= videocap_x;
  1099. videocap_y_sync2 <= videocap_y3;
  1100. videocap_mode_sync <= videocap_mode;
  1101. `ifdef VARIANT_ZZ9500
  1102. if (videocap_interlace)
  1103. videocap_ymax_sync <= (videocap_ymax<<1)-(2*40);
  1104. else
  1105. videocap_ymax_sync <= videocap_ymax-36;
  1106. // letterbox top and bottom to box out noisy lines
  1107. if (videocap_y_sync2<videocap_ymax_sync && videocap_x_done) begin
  1108. videocap_y_sync <= videocap_y_sync2;
  1109. end
  1110. `else
  1111. if (videocap_interlace)
  1112. videocap_ymax_sync <= (videocap_ymax<<1);
  1113. else
  1114. videocap_ymax_sync <= videocap_ymax;
  1115. if (videocap_x_done) begin
  1116. videocap_y_sync <= videocap_y_sync2;
  1117. end
  1118. `endif
  1119. videocap_save_x2 <= videocap_save_x;
  1120. vc_saveaddr1 <= vc_saving_line*videocap_pitch_sync;
  1121. // we shift left by 2 bits to scale from 1 pixel to 4 bytes
  1122. vc_saveaddr2 <= (vc_saveaddr1+videocap_save_x)<<2;
  1123. // FIXME
  1124. if (videocap_save_line_done!=videocap_y_sync) begin
  1125. vc_saving_line <= videocap_y_sync;
  1126. end
  1127. if (m01_axi_aresetn == 0) begin
  1128. videocap_save_state <= 4;
  1129. //m01_axi_wvalid_out <= 0;
  1130. //m01_axi_awvalid_out <= 0;
  1131. end else begin
  1132. m01_axi_awaddr_out <= `VIDEOCAP_ADDR+vc_saveaddr2;
  1133. m01_axi_wdata_out <= videocap_buf[videocap_save_x];
  1134. // one-hot encoded
  1135. case (videocap_save_state)
  1136. 4'h0: begin
  1137. // initial state
  1138. if (m01_axi_awready) begin
  1139. videocap_save_state <= 2;
  1140. end
  1141. end
  1142. 4'h1: begin
  1143. m01_axi_awvalid_out <= 0;
  1144. m01_axi_wvalid_out <= 1;
  1145. if (m01_axi_wready) begin
  1146. videocap_save_state <= 2;
  1147. end
  1148. end
  1149. 4'h2: begin
  1150. // FIXME this was moved from state 1 wready clause
  1151. `ifdef VARIANT_ZZ9500
  1152. if (videocap_save_x >= videocap_pitch_sync-2) begin
  1153. `else
  1154. if (videocap_save_x >= videocap_pitch_sync) begin // 728 FIXME
  1155. `endif
  1156. videocap_save_line_done <= vc_saving_line;
  1157. videocap_save_x <= 0;
  1158. end else if (videocap_save_line_done != vc_saving_line)
  1159. videocap_save_x <= videocap_save_x + 1'b1;
  1160. m01_axi_awvalid_out <= 1;
  1161. m01_axi_wvalid_out <= 0;
  1162. if (m01_axi_awready) begin
  1163. if (videocap_mode_sync)
  1164. videocap_save_state <= 1;
  1165. else
  1166. videocap_save_state <= 4;
  1167. end
  1168. end
  1169. 4'h4: begin
  1170. // videocap is disabled, lets wait here
  1171. if (videocap_mode_sync)
  1172. videocap_save_state <= 0;
  1173. m01_axi_wvalid_out <= 0;
  1174. m01_axi_awvalid_out <= 0;
  1175. end
  1176. endcase
  1177. end
  1178. end
  1179. // -- main zorro fsm ---------------------------------------------
  1180. always @(posedge S_AXI_ACLK) begin
  1181. zorro_idle <= ((zorro_state==Z2_IDLE)||(zorro_state==Z3_IDLE));
  1182. `ifndef VARIANT_FW20
  1183. // FIXME videocap disabled for FW20
  1184. videocap_mode <= videocap_mode_in;
  1185. `endif
  1186. if (/*z_cfgin_lo ||*/ z_reset) begin
  1187. zorro_state <= RESET;
  1188. end //else
  1189. case (zorro_state)
  1190. COLD: begin
  1191. zorro_state <= RESET;
  1192. end
  1193. RESET: begin
  1194. dataout_enable <= 0;
  1195. dataout <= 0;
  1196. dataout_z3 <= 0;
  1197. slaven <= 0;
  1198. dtack <= 0;
  1199. z_ovr <= 0;
  1200. z_confout <= 0;
  1201. z3_confdone <= 0;
  1202. zorro_ram_read_request <= 0;
  1203. zorro_ram_write_request <= 0;
  1204. zorro_ram_read_flag <= 0;
  1205. zorro_ram_write_flag <= 0;
  1206. videocap_mode_in <= 0;
  1207. videocap_pitch <= 720; // FIXME?
  1208. if (!z_reset)
  1209. zorro_state <= DECIDE_Z2_Z3;
  1210. // uncomment this to have native video capture
  1211. // directly on startup, before/without autoconfig.
  1212. // we don't do this by default because it messes
  1213. // up the timing sometimes.
  1214. //videocap_mode_in <= 1;
  1215. end
  1216. DECIDE_Z2_Z3: begin
  1217. `ifdef ZORRO2
  1218. if (z2addr_autoconfig) begin
  1219. //ZORRO3 <= 0;
  1220. zorro_state <= Z2_CONFIGURING;
  1221. end
  1222. `endif
  1223. `ifdef ZORRO3
  1224. if (z3addr_autoconfig) begin
  1225. //ZORRO3 <= 1;
  1226. zorro_state <= Z3_CONFIGURING;
  1227. end
  1228. `endif
  1229. end
  1230. `ifdef ZORRO3
  1231. Z3_AUTOCONF_READ_DLY: begin
  1232. // wait for data to be latched out
  1233. zorro_state <= Z3_AUTOCONF_READ_DLY2;
  1234. end
  1235. Z3_AUTOCONF_READ_DLY2: begin
  1236. // wait for data to be latched out
  1237. zorro_state <= Z3_DTACK;
  1238. end
  1239. Z3_AUTOCONF_READ: begin
  1240. dataout_z3 <= 1;
  1241. slaven <= 1;
  1242. zorro_state <= Z3_AUTOCONF_READ_DLY;
  1243. last_z3addr <= z3addr;
  1244. case (z3addr[15:0])
  1245. 'h0000: data_z3_hi16 <= 'b1000_1111_1111_1111; // zorro 3 (10), no pool link (0), autoboot ROM (1)
  1246. 'h0100: data_z3_hi16 <= 'b0100_1111_1111_1111; // next board unrelated (0), 256MB 1024MB fixme
  1247. 'h0004: data_z3_hi16 <= 'b1111_1111_1111_1111; // product number
  1248. 'h0104: data_z3_hi16 <= 'b1011_1111_1111_1111; // (4)
  1249. 'h0008: data_z3_hi16 <= 'b0000_1111_1111_1111; // flags inverted 0111 io,shutup,extension,reserved(1)
  1250. 'h0108: data_z3_hi16 <= 'b1111_1111_1111_1111; // inverted zero
  1251. 'h000c: data_z3_hi16 <= 'b1111_1111_1111_1111; // reserved?
  1252. 'h010c: data_z3_hi16 <= 'b1111_1111_1111_1111; //
  1253. 'h0010: data_z3_hi16 <= 'b1001_1111_1111_1111; // manufacturer high byte inverted
  1254. 'h0110: data_z3_hi16 <= 'b0010_1111_1111_1111; //
  1255. 'h0014: data_z3_hi16 <= 'b1001_1111_1111_1111; // manufacturer low byte
  1256. 'h0114: data_z3_hi16 <= 'b0001_1111_1111_1111;
  1257. 'h0018: data_z3_hi16 <= 'b1111_1111_1111_1111; // serial 01 01 01 01
  1258. 'h0118: data_z3_hi16 <= 'b1110_1111_1111_1111; //
  1259. 'h001c: data_z3_hi16 <= 'b1111_1111_1111_1111; //
  1260. 'h011c: data_z3_hi16 <= 'b1110_1111_1111_1111; //
  1261. 'h0020: data_z3_hi16 <= 'b1111_1111_1111_1111; //
  1262. 'h0120: data_z3_hi16 <= 'b1110_1111_1111_1111; //
  1263. 'h0024: data_z3_hi16 <= 'b1111_1111_1111_1111; //
  1264. 'h0124: data_z3_hi16 <= 'b1110_1111_1111_1111; //
  1265. /*'h0028: data_z3_hi16 <= 'b1111_1111_1111_1111; // autoboot rom vector (er_InitDiagVec)
  1266. 'h0128: data_z3_hi16 <= 'b1111_1111_1111_1111; // ff7f = ~0080
  1267. 'h002c: data_z3_hi16 <= 'b0111_1111_1111_1111;
  1268. 'h012c: data_z3_hi16 <= 'b1111_1111_1111_1111;*/
  1269. default: data_z3_hi16 <= 'b1111_1111_1111_1110; // FIXME
  1270. endcase
  1271. end
  1272. Z3_AUTOCONF_WRITE: begin
  1273. slaven <= 1;
  1274. if (z3_ds0||z3_ds1||z3_ds2||z3_ds3) begin
  1275. zorro_state <= Z3_DTACK;
  1276. casex (z3addr[15:0])
  1277. 'hXX44: begin
  1278. z3_ram_low[31:16] <= z3_din_high_s2;
  1279. z_confout <= 1;
  1280. z3_confdone <= 1;
  1281. end
  1282. 'hXX48: begin
  1283. end
  1284. 'hXX4c: begin
  1285. // shutup
  1286. z_confout <= 1;
  1287. z3_confdone <= 1;
  1288. end
  1289. endcase
  1290. end
  1291. end
  1292. Z3_CONFIGURING: begin
  1293. // FIXME why?
  1294. //data_z3_low16 <= 'hffff;
  1295. if (z_cfgin && z3addr_autoconfig) begin
  1296. if (zorro_read) begin
  1297. // autoconfig ROM
  1298. zorro_state <= Z3_AUTOCONF_READ;
  1299. end else begin
  1300. // write to autoconfig register
  1301. zorro_state <= Z3_AUTOCONF_WRITE;
  1302. end
  1303. end
  1304. dataout_z3 <= 0;
  1305. slaven <= 0;
  1306. dtack <= 0;
  1307. end
  1308. Z3_DTACK: begin
  1309. if (z3_fcs_state == 1) begin
  1310. dtack <= 0;
  1311. dataout_z3 <= 0;
  1312. slaven <= 0;
  1313. if (z3_confdone) begin
  1314. zorro_state <= CONFIGURED;
  1315. end else
  1316. zorro_state <= Z3_CONFIGURING;
  1317. end else
  1318. dtack <= 1;
  1319. end
  1320. `endif
  1321. CONFIGURED: begin
  1322. ram_high <= ram_low + `RAM_SIZE;
  1323. reg_low <= ram_low + 'h1000;
  1324. reg_high <= ram_low + 'h2000;
  1325. z3_ram_high <= z3_ram_low + `Z3_RAM_SIZE;
  1326. z3_reg_low <= z3_ram_low + 'h1000;
  1327. z3_reg_high <= z3_ram_low + 'h2000;
  1328. zorro_state <= CONFIGURED_CLEAR;
  1329. end
  1330. CONFIGURED_CLEAR: begin
  1331. // this is a fix for the "pixel swap" bug: if AXI HP is getting writes too early,
  1332. // it would sometimes (~10% of cold starts) get confused and swap pairs of writes.
  1333. `ifndef VARIANT_FW20
  1334. videocap_mode_in <= 1;
  1335. `endif
  1336. `ifdef ZORRO3
  1337. zorro_state <= Z3_IDLE;
  1338. `else
  1339. zorro_state <= Z2_IDLE;
  1340. `endif
  1341. end
  1342. // ---------------------------------------------------------------------------------
  1343. `ifdef ZORRO2
  1344. Z2_CONFIGURING: begin
  1345. z_ovr <= 0;
  1346. if (z2_addr_valid && z2addr_autoconfig && z_cfgin) begin
  1347. if (z2_read) begin
  1348. // read iospace 'he80000 (Autoconfig ROM)
  1349. dataout_enable <= 1;
  1350. dataout <= 1;
  1351. slaven <= 1;
  1352. case (z2_mapped_addr[7:0])
  1353. 8'h00: data_out <= 'b1101_1111_1111_1111; // zorro 2 (11), no pool (0) rom (1)
  1354. 8'h02: data_out <= 'b0111_1111_1111_1111; // next board unrelated (0), 4mb (110 for 2mb)
  1355. 8'h04: data_out <= 'b1111_1111_1111_1111; // product number
  1356. 8'h06: data_out <= 'b1100_1111_1111_1111; // (3)
  1357. 8'h08: data_out <= 'b0011_1111_1111_1111; // flags inverted 0011
  1358. 8'h0a: data_out <= 'b1110_1111_1111_1111; // inverted 0001 = OS sized
  1359. 8'h10: data_out <= 'b1001_1111_1111_1111; // manufacturer high byte inverted (02)
  1360. 8'h12: data_out <= 'b0010_1111_1111_1111; //
  1361. 8'h14: data_out <= 'b1001_1111_1111_1111; // manufacturer low byte (9a)
  1362. 8'h16: data_out <= 'b0001_1111_1111_1111;
  1363. 8'h18: data_out <= 'b1111_1111_1111_1111; // serial 01 01 01 01
  1364. 8'h1a: data_out <= 'b1110_1111_1111_1111; //
  1365. 8'h1c: data_out <= 'b1111_1111_1111_1111; //
  1366. 8'h1e: data_out <= 'b1110_1111_1111_1111; //
  1367. 8'h20: data_out <= 'b1111_1111_1111_1111; //
  1368. 8'h22: data_out <= 'b1110_1111_1111_1111; //
  1369. 8'h24: data_out <= 'b1111_1111_1111_1111; //
  1370. 8'h26: data_out <= 'b1110_1111_1111_1111; //
  1371. /*8'h28: data_out <= 'b1111_1111_1111_1111; // autoboot rom vector (er_InitDiagVec)
  1372. 8'h2a: data_out <= 'b1111_1111_1111_1111; // ff7f = ~0080
  1373. 8'h2c: data_out <= 'b0111_1111_1111_1111;
  1374. 8'h2e: data_out <= 'b1111_1111_1111_1111;*/
  1375. //'h000040: data <= 'b0000_0000_0000_0000; // interrupts (not inverted)
  1376. //'h000042: data <= 'b0000_0000_0000_0000; //
  1377. default: data_out <= 'b1111_1111_1111_1111;
  1378. endcase
  1379. end else begin
  1380. // write to autoconfig register
  1381. if (z2_datastrobe_synced) begin
  1382. case (z2_mapped_addr[7:0])
  1383. 8'h48: begin
  1384. ram_low[31:24] <= 8'h0;
  1385. ram_low[23:20] <= z3_din_high_s2[15:12];
  1386. ram_low[15:0] <= 16'h0;
  1387. zorro_state <= Z2_PRE_CONFIGURED; // configured
  1388. end
  1389. 8'h4a: begin
  1390. ram_low[31:24] <= 8'h0;
  1391. ram_low[19:16] <= z3_din_high_s2[15:12];
  1392. ram_low[15:0] <= 16'h0;
  1393. end
  1394. 8'h4c: begin
  1395. zorro_state <= Z2_PRE_CONFIGURED; // configured, shut up
  1396. end
  1397. endcase
  1398. end
  1399. end
  1400. end else begin
  1401. // no address match
  1402. dataout <= 0;
  1403. dataout_enable <= 0;
  1404. slaven <= 0;
  1405. end
  1406. end
  1407. Z2_PRE_CONFIGURED: begin
  1408. if (!z2_addr_valid) begin
  1409. z_confout<=1;
  1410. zorro_state <= CONFIGURED;
  1411. end
  1412. end
  1413. Z2_IDLE: begin
  1414. if (z2_addr_valid) begin
  1415. if (z2_write && z2addr_in_reg) begin
  1416. // write to register
  1417. dataout_enable <= 0;
  1418. dataout <= 0;
  1419. slaven <= 1;
  1420. z_ovr <= 1;
  1421. zaddr_regpart <= z2_mapped_addr;
  1422. zorro_state <= Z2_REGWRITE;
  1423. end else if (z2_read && z2addr_in_reg) begin
  1424. // read from registers
  1425. dataout_enable <= 1;
  1426. dataout <= 1;
  1427. data_out <= default_data; //'hffff;
  1428. slaven <= 1;
  1429. z_ovr <= 1;
  1430. zaddr_regpart <= z2_mapped_addr;
  1431. zorro_state <= Z2_REGREAD;
  1432. end else if (z2_read && z2addr_in_ram) begin
  1433. // read RAM
  1434. // request ram access from arbiter
  1435. last_addr <= z2_mapped_addr-ram_low; // differently done in z3
  1436. data_out <= default_data; //'hffff;
  1437. dataout_enable <= 1;
  1438. dataout <= 1;
  1439. slaven <= 1;
  1440. z_ovr <= 1;
  1441. zorro_state <= WAIT_READ3;
  1442. end else if (z2_write && z2addr_in_ram) begin
  1443. // write RAM
  1444. last_addr <= z2_mapped_addr-ram_low;
  1445. dataout_enable <= 0;
  1446. dataout <= 0;
  1447. datain_counter <= 0;
  1448. slaven <= 1;
  1449. z_ovr <= 1;
  1450. //count_writes <= count_writes + 1;
  1451. zorro_state <= WAIT_WRITE;
  1452. end else begin
  1453. dataout <= 0;
  1454. dataout_enable <= 0;
  1455. slaven <= 0;
  1456. end
  1457. end else begin
  1458. dataout <= 0;
  1459. dataout_enable <= 0;
  1460. slaven <= 0;
  1461. end
  1462. end
  1463. Z2_REGWRITE: begin
  1464. if (z2_datastrobe_synced) begin
  1465. regdata_in <= zdata_in_sync;
  1466. regwrite_addr <= zaddr_regpart;
  1467. zorro_state <= REGWRITE;
  1468. end
  1469. end
  1470. WAIT_READ3: begin
  1471. zorro_ram_read_addr <= last_addr;
  1472. zorro_ram_read_request <= 1;
  1473. zorro_state <= WAIT_READ2;
  1474. end
  1475. WAIT_READ2: begin
  1476. // FIXME there can be a race here where read_request is immediately cancelled
  1477. if (zorro_ram_read_flag) begin
  1478. zorro_ram_read_request <= 0;
  1479. data_out <= axi_reg1[15:0];
  1480. zorro_state <= WAIT_READ2B;
  1481. end
  1482. end
  1483. WAIT_READ2B: begin
  1484. // FIXME trying to fix the race using the same approach as in Z3
  1485. if (!zorro_ram_read_flag) begin
  1486. read_counter <= 0;
  1487. zorro_state <= WAIT_READ2C;
  1488. end
  1489. end
  1490. WAIT_READ2C: begin
  1491. //if (read_counter>7) // FIXME tune this
  1492. zorro_state <= WAIT_READ2D;
  1493. //read_counter <= read_counter + 1'b1;
  1494. end
  1495. WAIT_READ2D: begin
  1496. read_counter <= 0;
  1497. dtack <= 1;
  1498. zorro_state <= Z2_ENDCYCLE;
  1499. end
  1500. WAIT_WRITE: begin
  1501. if (z2_datastrobe_synced) begin
  1502. zorro_write_capture_bytes <= {~znUDS_sync[2],~znLDS_sync[2]}; // FIXME was 1
  1503. zorro_write_capture_data <= zdata_in_sync;
  1504. if (last_addr<'h10000)
  1505. zorro_state <= WAIT_WRITE2;
  1506. else
  1507. zorro_state <= WAIT_WRITE_DMA_Z2;
  1508. end
  1509. end
  1510. WAIT_WRITE2: begin
  1511. zorro_ram_write_addr <= last_addr;
  1512. zorro_ram_write_bytes <= {2'b0,zorro_write_capture_bytes};
  1513. zorro_ram_write_data <= {16'b0,zorro_write_capture_data};
  1514. zorro_ram_write_request <= 1;
  1515. zorro_state <= Z2_WRITE_FINALIZE;
  1516. end
  1517. WAIT_WRITE_DMA_Z2: begin
  1518. if (last_addr[1])
  1519. m00_axi_wstrb_z3 <= {zorro_write_capture_bytes[0],zorro_write_capture_bytes[1],2'b0};
  1520. else
  1521. m00_axi_wstrb_z3 <= {2'b0,zorro_write_capture_bytes[0],zorro_write_capture_bytes[1]};
  1522. m00_axi_awaddr_z3 <= (last_addr+`ARM_MEMORY_START)&'hfffffc;
  1523. m00_axi_wdata_z3 <= {zorro_write_capture_data[7:0],zorro_write_capture_data[15:8],zorro_write_capture_data[7:0],zorro_write_capture_data[15:8]};
  1524. m00_axi_awvalid_z3 <= 1;
  1525. if (m00_axi_awready) begin // TODO wready?
  1526. zorro_state <= WAIT_WRITE_DMA_Z2_FINALIZE;
  1527. end
  1528. end
  1529. WAIT_WRITE_DMA_Z2_FINALIZE: begin
  1530. m00_axi_awvalid_z3 <= 0;
  1531. m00_axi_wvalid_z3 <= 1;
  1532. if (m00_axi_wready) begin
  1533. dtack <= 1;
  1534. zorro_state <= Z2_ENDCYCLE;
  1535. end
  1536. end
  1537. Z2_WRITE_FINALIZE: begin
  1538. if (zorro_ram_write_flag) begin
  1539. dtack <= 1;
  1540. zorro_state <= Z2_ENDCYCLE;
  1541. zorro_ram_write_request <= 0;
  1542. end
  1543. end
  1544. Z2_ENDCYCLE: begin
  1545. m00_axi_wvalid_z3 <= 0;
  1546. z_ovr <= 0;
  1547. // FIXME
  1548. read_counter <= read_counter + 1'b1;
  1549. if (read_counter >= 10) begin
  1550. dtack <= 0;
  1551. end
  1552. if (!z2_addr_valid) begin
  1553. dtack <= 0;
  1554. slaven <= 0;
  1555. dataout_enable <= 0;
  1556. dataout <= 0;
  1557. zorro_state <= Z2_IDLE;
  1558. read_counter <= 0;
  1559. end
  1560. end
  1561. // 16bit reg read
  1562. Z2_REGREAD_POST: begin
  1563. if (zaddr_regpart[1]==1'b1)
  1564. data_out <= rr_data[15:0];
  1565. else
  1566. data_out <= rr_data[31:16];
  1567. dtack <= 1;
  1568. zorro_state <= Z2_ENDCYCLE;
  1569. end
  1570. // relaxing the data pipeline a bit
  1571. Z2_REGREAD: begin
  1572. regread_addr <= zaddr_regpart;
  1573. zorro_state <= REGREAD;
  1574. end
  1575. `endif
  1576. `ifdef ZORRO3
  1577. // =========================================================================
  1578. // ZORRO 3
  1579. // =========================================================================
  1580. Z3_REGWRITE_PRE: begin
  1581. if (z3_ds1) begin
  1582. regdata_in <= z3_din_low_s2;
  1583. z3addr_regpart <= (z3addr[15:0])|16'h2;
  1584. zorro_state <= Z3_REGWRITE;
  1585. end else if (z3_ds3) begin
  1586. regdata_in <= z3_din_high_s2;
  1587. z3addr_regpart <= z3addr[15:0];
  1588. zorro_state <= Z3_REGWRITE;
  1589. end
  1590. end
  1591. Z3_REGREAD_PRE: begin
  1592. z3addr_regpart <= z3addr[15:0]; //|16'h2;
  1593. zorro_state <= Z3_REGREAD;
  1594. dataout_z3 <= 1;
  1595. end
  1596. Z3_IDLE: begin
  1597. read_counter <= 0;
  1598. if (z3_fcs_state==0) begin
  1599. // falling edge of /FCS
  1600. if (zorro_write && z3addr_in_reg) begin
  1601. // FIXME doesn't support 32 bit access
  1602. // write to register
  1603. zorro_state <= Z3_REGWRITE_PRE;
  1604. slaven <= 1;
  1605. end else if (zorro_read && z3addr_in_reg) begin
  1606. // read registers
  1607. data_z3_hi16 <= default_data;
  1608. data_z3_low16 <= default_data;
  1609. zorro_state <= Z3_REGREAD_PRE;
  1610. slaven <= 1;
  1611. end else if (z3addr_in_ram && zorro_write) begin
  1612. // write to memory
  1613. slaven <= 1;
  1614. zorro_state <= Z3_WRITE_PRE;
  1615. end else if (z3addr_in_ram && zorro_read) begin
  1616. // read from memory
  1617. data_z3_hi16 <= default_data;
  1618. data_z3_low16 <= default_data;
  1619. slaven <= 1;
  1620. if (z3_mapped_addr<'h10000)
  1621. zorro_state <= Z3_READ_UPPER;
  1622. else
  1623. zorro_state <= WAIT_READ_DMA_Z3;
  1624. end else begin
  1625. // address not recognized
  1626. slaven <= 0;
  1627. end
  1628. end else begin
  1629. // not in a cycle
  1630. slaven <= 0;
  1631. end
  1632. end
  1633. Z3_REGWRITE: begin
  1634. regwrite_addr <= z3addr_regpart;
  1635. zorro_state <= REGWRITE;
  1636. dtack <= 1;
  1637. end
  1638. Z3_REGREAD: begin
  1639. regread_addr <= z3addr_regpart;
  1640. zorro_state <= REGREAD;
  1641. end
  1642. // 32bit reg read
  1643. Z3_REGREAD_POST: begin
  1644. data_z3_hi16 <= rr_data[31:16];
  1645. data_z3_low16 <= rr_data[15:0];
  1646. zorro_state <= Z3_ENDCYCLE;
  1647. dtack <= 1;
  1648. end
  1649. Z3_READ_UPPER: begin
  1650. zorro_state <= Z3_READ_DELAY1;
  1651. last_z3addr <= z3_mapped_addr;
  1652. zorro_ram_read_addr <= z3_mapped_addr;
  1653. zorro_ram_read_bytes <= 4'b1111;
  1654. zorro_ram_read_request <= 1;
  1655. dataout_z3 <= 1; // enable data output
  1656. // dummy read for debug
  1657. /*dtack <= 1;
  1658. data_z3_hi16 <= 'hffff;
  1659. data_z3_low16 <= 'hffff;
  1660. zorro_state <= Z3_ENDCYCLE;*/
  1661. end
  1662. Z3_READ_DELAY1: begin
  1663. data_z3_hi16 <= axi_reg1[31:16];
  1664. data_z3_low16 <= axi_reg1[15:0];
  1665. if (zorro_ram_read_flag) begin
  1666. zorro_ram_read_request <= 0; // acknowledge read request done
  1667. zorro_state <= Z3_READ_DELAY2; // CHECK DELAY
  1668. end
  1669. end
  1670. Z3_READ_DELAY2: begin
  1671. if (!zorro_ram_read_flag) begin
  1672. zorro_state <= Z3_ENDCYCLE;
  1673. dtack <= 1;
  1674. slaven <= 0;
  1675. end
  1676. end
  1677. Z3_WRITE_PRE: begin
  1678. if (z3_ds0||z3_ds1||z3_ds2||z3_ds3) begin
  1679. zorro_state <= Z3_WRITE_PRE2;
  1680. end
  1681. end
  1682. Z3_WRITE_PRE2: begin
  1683. // FIXME DMA temporarily disabled for FW2.0
  1684. `ifdef VARIANT_FW20
  1685. zorro_state <= Z3_WRITE_UPPER;
  1686. `else
  1687. if (z3_mapped_addr<'h10000)
  1688. zorro_state <= Z3_WRITE_UPPER;
  1689. else
  1690. zorro_state <= WAIT_WRITE_DMA_Z3;
  1691. `endif
  1692. end
  1693. Z3_WRITE_UPPER: begin
  1694. last_z3addr <= z3_mapped_addr;
  1695. zorro_ram_write_addr <= z3_mapped_addr;
  1696. zorro_ram_write_bytes <= {z3_ds3,z3_ds2,z3_ds1,z3_ds0};
  1697. zorro_ram_write_data <= {z3_din_high_s2,z3_din_low_s2};
  1698. zorro_ram_write_request <= 1;
  1699. zorro_state <= Z3_WRITE_FINALIZE;
  1700. end
  1701. Z3_WRITE_FINALIZE: begin
  1702. if (zorro_ram_write_flag) begin
  1703. zorro_ram_write_request <= 0; // acknowledge write request done
  1704. zorro_state <= Z3_ENDCYCLE;
  1705. dtack <= 1;
  1706. slaven <= 0;
  1707. end
  1708. end
  1709. WAIT_READ_DMA_Z3: begin
  1710. m00_axi_araddr <= `ARM_MEMORY_START + (z3_mapped_addr/*&32'hfffffffc*/); // max 256MB
  1711. m00_axi_arvalid <= 1;
  1712. // m00_axi_rready <= 1;
  1713. if (m00_axi_arready) begin
  1714. zorro_state <= WAIT_READ_DMA_Z3B;
  1715. end
  1716. end
  1717. WAIT_READ_DMA_Z3B: begin
  1718. m00_axi_arvalid <= 0;
  1719. // m00_axi_rready <= 1;
  1720. if (m00_axi_rvalid) begin
  1721. zorro_state <= Z3_ENDCYCLE;
  1722. data_z3_hi16 <= {m00_axi_rdata[7:0], m00_axi_rdata[15:8]};
  1723. data_z3_low16 <= {m00_axi_rdata[23:16], m00_axi_rdata[31:24]};
  1724. dataout_z3 <= 1; // enable data output
  1725. dtack <= 1;
  1726. end
  1727. end
  1728. WAIT_WRITE_DMA_Z3: begin
  1729. m00_axi_wstrb_z3 <= {z3_ds0, z3_ds1, z3_ds2, z3_ds3};
  1730. m00_axi_awaddr_z3 <= `ARM_MEMORY_START + (z3_mapped_addr/*&32'hfffffffc*/); // max 256MB
  1731. m00_axi_wdata_z3 <= {z3_din_low_s2[7:0], z3_din_low_s2[15:8], z3_din_high_s2[7:0], z3_din_high_s2[15:8]};
  1732. m00_axi_awvalid_z3 <= 1;
  1733. if (m00_axi_awready) begin
  1734. zorro_state <= WAIT_WRITE_DMA_Z3B;
  1735. end
  1736. end
  1737. WAIT_WRITE_DMA_Z3B: begin
  1738. dtack <= 1;
  1739. m00_axi_awvalid_z3 <= 0;
  1740. m00_axi_wvalid_z3 <= 1;
  1741. if (m00_axi_wready) begin
  1742. zorro_state <= WAIT_WRITE_DMA_Z3C;
  1743. end
  1744. end
  1745. // not sure if this extra state is needed actually
  1746. WAIT_WRITE_DMA_Z3C: begin
  1747. m00_axi_wvalid_z3 <= 0;
  1748. zorro_state <= Z3_ENDCYCLE;
  1749. end
  1750. Z3_ENDCYCLE: begin
  1751. dtack <= 1;
  1752. // we're timing out or own dtack here. because of a zorro
  1753. // bug / subtlety, dtack can be sampled incorrectly to "hang over"
  1754. // into the next amiga zorro cycle.
  1755. // this is because we have a long rise time on our DTACK
  1756. // output/1k pullup.
  1757. read_counter <= read_counter + 1'b1;
  1758. if (read_counter >= dtack_timeout) begin
  1759. dtack <= 0;
  1760. end
  1761. if (z3_fcs_state==1) begin
  1762. dtack <= 0;
  1763. slaven <= 0;
  1764. dataout_z3 <= 0;
  1765. zorro_state <= Z3_IDLE;
  1766. end
  1767. end
  1768. `endif
  1769. // FIXME why is there no dataout time on REGREAD? (see memory reads)
  1770. // now fixed for Z3, still pending for Z2
  1771. REGREAD: begin
  1772. // TODO split up into z3/z2
  1773. `ifdef ZORRO3
  1774. zorro_state <= Z3_REGREAD_POST;
  1775. `else
  1776. zorro_state <= Z2_REGREAD_POST;
  1777. `endif
  1778. case (regread_addr&'hff)
  1779. /*'h00: begin
  1780. rr_data <= video_control_data;
  1781. end
  1782. 'h04: begin
  1783. rr_data <= video_control_op;
  1784. end*/
  1785. 'h00: begin
  1786. // this flag is read by Amiga software to check if all writes are done
  1787. rr_data <= 0; //zorro_ram_write_request;
  1788. end
  1789. default: begin
  1790. rr_data[31:16] <= REVISION;
  1791. rr_data[15:0] <= REVISION;
  1792. end
  1793. endcase
  1794. end
  1795. REGWRITE: begin
  1796. `ifdef ZORRO3
  1797. zorro_state <= Z3_ENDCYCLE;
  1798. `else
  1799. dtack <= 1;
  1800. zorro_state <= Z2_ENDCYCLE;
  1801. `endif
  1802. case (regwrite_addr&'hff)
  1803. 'h00: video_control_data_zorro[31:16] <= regdata_in[15:0];
  1804. 'h02: video_control_data_zorro[15:0] <= regdata_in[15:0];
  1805. 'h04: video_control_op_zorro[7:0] <= regdata_in[7:0]; // FIXME
  1806. 'h06: videocap_mode_in <= regdata_in[0];
  1807. //'h20: if (regdata_in[5:0]>0) dtack_timeout <= regdata_in[5:0];
  1808. //'h14: zorro_interrupt <= regdata_in[0];
  1809. //'h10: E7M_PSINCDEC <= regdata_in[0];
  1810. //'h12: E7M_PSEN <= regdata_in[0];
  1811. endcase
  1812. end
  1813. endcase
  1814. // PSEN reset
  1815. //if (E7M_PSEN==1'b1) E7M_PSEN <= 1'b0;
  1816. // ARM video control
  1817. if (axi_reg2[31]==1'b1) begin
  1818. video_control_data_axi <= axi_reg3[31:0];
  1819. video_control_op_axi <= axi_reg2[7:0];
  1820. video_control_axi <= 1;
  1821. end else
  1822. video_control_axi <= 0;
  1823. if (axi_reg2[30]==1'b1) begin
  1824. zorro_interrupt <= axi_reg2[0];
  1825. end
  1826. // read / write request acknowledged by ARM
  1827. zorro_ram_read_flag <= axi_reg0[30];
  1828. zorro_ram_write_flag <= axi_reg0[31];
  1829. axi_reg0 <= slv_reg0;
  1830. axi_reg1 <= slv_reg1;
  1831. axi_reg2 <= slv_reg2;
  1832. axi_reg3 <= slv_reg3;
  1833. if (video_control_axi) begin
  1834. video_control_data <= video_control_data_axi;
  1835. video_control_op <= video_control_op_axi;
  1836. end else begin
  1837. video_control_data <= video_control_data_zorro;
  1838. video_control_op <= video_control_op_zorro;
  1839. end
  1840. video_control_data_out <= video_control_data;
  1841. video_control_op_out <= video_control_op;
  1842. video_control_vblank <= video_control_vblank_in;
  1843. video_control_interlace_out <= video_control_interlace;
  1844. // snoop the screen width for correct capture pitch
  1845. if (video_control_op == 2) begin
  1846. // OP_DIMENSIONS = 2
  1847. videocap_pitch_snoop <= video_control_data[11:0];
  1848. end
  1849. videocap_pitch <= videocap_pitch_snoop;
  1850. out_reg0 <= ZORRO3 ? last_z3addr : last_addr;
  1851. out_reg1 <= zorro_ram_write_data;
  1852. out_reg2 <= last_z3addr;
  1853. //out_reg3 <= {zorro_ram_write_request, zorro_ram_read_request, zorro_ram_write_bytes, ZORRO3,
  1854. // video_control_interlace, videocap_mode, 15'b0, zorro_state};
  1855. // `-- 24 `-- 23 `-- 22 `-- 7:0
  1856. out_reg3 <= {zorro_ram_write_request, zorro_ram_read_request, zorro_ram_write_bytes, ZORRO3,
  1857. video_control_interlace, videocap_mode, videocap_ntsc, video_control_vblank, 13'b0, zorro_state};
  1858. end
  1859. assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
  1860. always @(*)
  1861. begin
  1862. // Address decoding for reading registers
  1863. case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
  1864. 2'h0 : reg_data_out <= out_reg0;
  1865. 2'h1 : reg_data_out <= out_reg1;
  1866. 2'h2 : reg_data_out <= out_reg2;
  1867. 2'h3 : reg_data_out <= out_reg3;
  1868. default : reg_data_out <= 'h0;
  1869. endcase
  1870. end
  1871. endmodule