Firmware for MNT ZZ9000 graphics and ARM coprocessor card for Amiga computers.
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mntzorro.v 61KB

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  1. `timescale 1 ns / 1 ps
  2. /*
  3. * MNT ZZ9000 Amiga Graphics and Coprocessor Card Firmware
  4. * Zorro 2/3 AXI4-Lite Interface, 24-bit Video Capture (AXI DMA)
  5. *
  6. * Copyright (C) 2019, Lukas F. Hartmann <lukas@mntre.com>
  7. * MNT Research GmbH, Berlin
  8. * https://mntre.com
  9. *
  10. * More Info: https://mntre.com/zz9000
  11. *
  12. * SPDX-License-Identifier: GPL-3.0-or-later
  13. * GNU General Public License v3.0 or later
  14. *
  15. * https://spdx.org/licenses/GPL-3.0-or-later.html
  16. *
  17. */
  18. // ZORRO2/3 switch
  19. //`define ZORRO2
  20. `define ZORRO3
  21. `define C_S_AXI_DATA_WIDTH 32
  22. `define C_S_AXI_ADDR_WIDTH 4
  23. `define RAM_SIZE 32'h400000 // 4MB for Zorro 2
  24. `define REG_SIZE 32'h01000
  25. `define AUTOCONF_LOW 24'he80000
  26. `define AUTOCONF_HIGH 24'he80080
  27. `define Z3_RAM_SIZE 32'h10000000 // 256MB for Zorro 3
  28. `define ARM_MEMORY_START 32'h00200000
  29. `define VIDEOCAP_ADDR 32'h01000000 // ARM_MEMORY_START+0xe0_0000
  30. `define C_M00_AXI_TARGET_SLAVE_BASE_ADDR 32'h10000000
  31. `define C_M00_AXI_ID_WIDTH 1
  32. `define C_M00_AXI_ADDR_WIDTH 32
  33. `define C_M00_AXI_DATA_WIDTH 32
  34. `define C_M00_AXI_AWUSER_WIDTH 0
  35. `define C_M00_AXI_ARUSER_WIDTH 0
  36. `define C_M00_AXI_WUSER_WIDTH 0
  37. `define C_M00_AXI_RUSER_WIDTH 0
  38. `define C_M00_AXI_BUSER_WIDTH 0
  39. module MNTZorro_v0_1_S00_AXI
  40. (
  41. inout wire [22:0] ZORRO_ADDR,
  42. inout wire [15:0] ZORRO_DATA,
  43. output wire ZORRO_INT6,
  44. output wire ZORRO_DATADIR,
  45. output wire ZORRO_ADDRDIR,
  46. output wire ZORRO_ADDRDIR2,
  47. output wire ZORRO_NBRN,
  48. input wire ZORRO_NBGN,
  49. input wire ZORRO_READ,
  50. //input wire ZORRO_NMTCR,
  51. input wire ZORRO_NUDS,
  52. input wire ZORRO_NLDS,
  53. input wire ZORRO_NDS1,
  54. input wire ZORRO_NDS0,
  55. input wire ZORRO_NCCS,
  56. input wire ZORRO_NFCS,
  57. input wire ZORRO_DOE,
  58. input wire ZORRO_NIORST,
  59. input wire ZORRO_NCFGIN,
  60. input wire ZORRO_E7M,
  61. input wire ZORRO_C28D,
  62. input wire VCAP_VSYNC,
  63. input wire VCAP_HSYNC,
  64. input wire VCAP_G0,
  65. input wire VCAP_G1,
  66. input wire VCAP_G2,
  67. input wire VCAP_G3,
  68. input wire VCAP_G4,
  69. input wire VCAP_G5,
  70. input wire VCAP_G6,
  71. input wire VCAP_G7,
  72. input wire VCAP_B7,
  73. input wire VCAP_B6,
  74. input wire VCAP_B5,
  75. input wire VCAP_B4,
  76. input wire VCAP_B3,
  77. input wire VCAP_B2,
  78. input wire VCAP_B1,
  79. input wire VCAP_B0,
  80. input wire VCAP_R7,
  81. input wire VCAP_R6,
  82. input wire VCAP_R5,
  83. input wire VCAP_R4,
  84. input wire VCAP_R3,
  85. input wire VCAP_R2,
  86. input wire VCAP_R1,
  87. input wire VCAP_R0,
  88. output wire ZORRO_NCFGOUT,
  89. (* mark_debug = "true" *) output wire ZORRO_NSLAVE,
  90. (* mark_debug = "true" *) output wire ZORRO_NCINH,
  91. (* mark_debug = "true" *) output wire ZORRO_NDTACK,
  92. // HP master interface to write to PS memory directly
  93. input wire m00_axi_aclk,
  94. input wire m00_axi_aresetn,
  95. // write address channel
  96. input wire m00_axi_awready,
  97. //output reg [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_awid,
  98. output reg [`C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr,
  99. output reg [7:0] m00_axi_awlen,
  100. output reg [2:0] m00_axi_awsize,
  101. output reg [1:0] m00_axi_awburst,
  102. output reg m00_axi_awlock,
  103. output reg [3:0] m00_axi_awcache,
  104. output reg [2:0] m00_axi_awprot,
  105. output reg [3:0] m00_axi_awqos,
  106. output reg m00_axi_awvalid,
  107. // write channel
  108. input wire m00_axi_wready,
  109. //output reg [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_wid,
  110. output reg [`C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata,
  111. output reg [`C_M00_AXI_DATA_WIDTH/8-1 : 0] m00_axi_wstrb,
  112. output reg m00_axi_wlast,
  113. output reg m00_axi_wvalid,
  114. // buffered write response channel
  115. //input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_bid,
  116. input wire [1 : 0] m00_axi_bresp,
  117. input wire m00_axi_bvalid,
  118. output reg m00_axi_bready,
  119. // read address channel
  120. /*input wire m00_axi_arready,
  121. output reg [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_arid,
  122. output reg [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
  123. output reg [7 : 0] m00_axi_arlen,
  124. output reg [2 : 0] m00_axi_arsize,
  125. output reg [1 : 0] m00_axi_arburst,
  126. output reg m00_axi_arlock,
  127. output reg [3 : 0] m00_axi_arcache,
  128. output reg [2 : 0] m00_axi_arprot,
  129. output reg [3 : 0] m00_axi_arqos,
  130. output reg m00_axi_arvalid,
  131. output reg m00_axi_rready,
  132. input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_rid,
  133. input wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
  134. input wire [1 : 0] m00_axi_rresp,
  135. input wire m00_axi_rlast,
  136. input wire m00_axi_rvalid,*/
  137. // video_formatter control interface
  138. output reg [31:0] video_control_data,
  139. output reg [7:0] video_control_op,
  140. output reg video_control_interlace,
  141. // Xilinx AXI4-Lite implementation starts here ==============================
  142. // Global Clock Signal
  143. input wire S_AXI_ACLK,
  144. // Global Reset Signal. This Signal is Active LOW
  145. input wire S_AXI_ARESETN,
  146. // Write address (issued by master, acceped by Slave)
  147. input wire [`C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
  148. // Write channel Protection type. This signal indicates the
  149. // privilege and security level of the transaction, and whether
  150. // the transaction is a data access or an instruction access.
  151. input wire [2 : 0] S_AXI_AWPROT,
  152. // Write address valid. This signal indicates that the master signaling
  153. // valid write address and control information.
  154. input wire S_AXI_AWVALID,
  155. // Write address ready. This signal indicates that the slave is ready
  156. // to accept an address and associated control signals.
  157. output wire S_AXI_AWREADY,
  158. // Write data (issued by master, acceped by Slave)
  159. input wire [`C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
  160. // Write strobes. This signal indicates which byte lanes hold
  161. // valid data. There is one write strobe bit for each eight
  162. // bits of the write data bus.
  163. input wire [(`C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
  164. // Write valid. This signal indicates that valid write
  165. // data and strobes are available.
  166. input wire S_AXI_WVALID,
  167. // Write ready. This signal indicates that the slave
  168. // can accept the write data.
  169. output wire S_AXI_WREADY,
  170. // Write response. This signal indicates the status
  171. // of the write transaction.
  172. output wire [1 : 0] S_AXI_BRESP,
  173. // Write response valid. This signal indicates that the channel
  174. // is signaling a valid write response.
  175. output wire S_AXI_BVALID,
  176. // Response ready. This signal indicates that the master
  177. // can accept a write response.
  178. input wire S_AXI_BREADY,
  179. // Read address (issued by master, acceped by Slave)
  180. input wire [`C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
  181. // Protection type. This signal indicates the privilege
  182. // and security level of the transaction, and whether the
  183. // transaction is a data access or an instruction access.
  184. input wire [2 : 0] S_AXI_ARPROT,
  185. // Read address valid. This signal indicates that the channel
  186. // is signaling valid read address and control information.
  187. input wire S_AXI_ARVALID,
  188. // Read address ready. This signal indicates that the slave is
  189. // ready to accept an address and associated control signals.
  190. output wire S_AXI_ARREADY,
  191. // Read data (issued by slave)
  192. output wire [`C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
  193. // Read response. This signal indicates the status of the
  194. // read transfer.
  195. output wire [1 : 0] S_AXI_RRESP,
  196. // Read valid. This signal indicates that the channel is
  197. // signaling the required read data.
  198. output wire S_AXI_RVALID,
  199. // Read ready. This signal indicates that the master can
  200. // accept the read data and response information.
  201. input wire S_AXI_RREADY
  202. );
  203. // AXI4LITE signals
  204. reg [`C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
  205. reg axi_awready;
  206. reg axi_wready;
  207. reg [1 : 0] axi_bresp;
  208. reg axi_bvalid;
  209. reg [`C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
  210. reg axi_arready;
  211. reg [`C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
  212. reg [1 : 0] axi_rresp;
  213. reg axi_rvalid;
  214. // Example-specific design signals
  215. // local localparam for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
  216. // ADDR_LSB is used for addressing 32/64 bit registers/memories
  217. // ADDR_LSB = 2 for 32 bits (n downto 2)
  218. // ADDR_LSB = 3 for 64 bits (n downto 3)
  219. localparam integer ADDR_LSB = (`C_S_AXI_DATA_WIDTH/32) + 1;
  220. localparam integer OPT_MEM_ADDR_BITS = 1;
  221. //----------------------------------------------
  222. //-- Signals for user logic register space example
  223. //------------------------------------------------
  224. //-- Number of Slave Registers 4
  225. reg [`C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
  226. reg [`C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
  227. reg [`C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
  228. reg [`C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
  229. wire slv_reg_rden;
  230. wire slv_reg_wren;
  231. reg [`C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
  232. integer byte_index;
  233. reg aw_en;
  234. reg [`C_S_AXI_DATA_WIDTH-1:0] out_reg0;
  235. reg [`C_S_AXI_DATA_WIDTH-1:0] out_reg1;
  236. reg [`C_S_AXI_DATA_WIDTH-1:0] out_reg2;
  237. reg [`C_S_AXI_DATA_WIDTH-1:0] out_reg3;
  238. // I/O Connections assignments
  239. assign S_AXI_AWREADY = axi_awready;
  240. assign S_AXI_WREADY = axi_wready;
  241. assign S_AXI_BRESP = axi_bresp;
  242. assign S_AXI_BVALID = axi_bvalid;
  243. assign S_AXI_ARREADY = axi_arready;
  244. assign S_AXI_RDATA = axi_rdata;
  245. assign S_AXI_RRESP = axi_rresp;
  246. assign S_AXI_RVALID = axi_rvalid;
  247. // Implement axi_awready generation
  248. // axi_awready is asserted for one S_AXI_ACLK clock cycle when both
  249. // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
  250. // de-asserted when reset is low.
  251. always @( posedge S_AXI_ACLK )
  252. begin
  253. if ( S_AXI_ARESETN == 1'b0 )
  254. begin
  255. axi_awready <= 1'b0;
  256. aw_en <= 1'b1;
  257. end
  258. else
  259. begin
  260. if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
  261. begin
  262. // slave is ready to accept write address when
  263. // there is a valid write address and write data
  264. // on the write address and data bus. This design
  265. // expects no outstanding transactions.
  266. axi_awready <= 1'b1;
  267. aw_en <= 1'b0;
  268. end
  269. else if (S_AXI_BREADY && axi_bvalid)
  270. begin
  271. aw_en <= 1'b1;
  272. axi_awready <= 1'b0;
  273. end
  274. else
  275. begin
  276. axi_awready <= 1'b0;
  277. end
  278. end
  279. end
  280. // Implement axi_awaddr latching
  281. // This process is used to latch the address when both
  282. // S_AXI_AWVALID and S_AXI_WVALID are valid.
  283. always @( posedge S_AXI_ACLK )
  284. begin
  285. if ( S_AXI_ARESETN == 1'b0 )
  286. begin
  287. axi_awaddr <= 0;
  288. end
  289. else
  290. begin
  291. if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
  292. begin
  293. // Write Address latching
  294. axi_awaddr <= S_AXI_AWADDR;
  295. end
  296. end
  297. end
  298. // Implement axi_wready generation
  299. // axi_wready is asserted for one S_AXI_ACLK clock cycle when both
  300. // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
  301. // de-asserted when reset is low.
  302. always @( posedge S_AXI_ACLK )
  303. begin
  304. if ( S_AXI_ARESETN == 1'b0 )
  305. begin
  306. axi_wready <= 1'b0;
  307. end
  308. else
  309. begin
  310. if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
  311. begin
  312. // slave is ready to accept write data when
  313. // there is a valid write address and write data
  314. // on the write address and data bus. This design
  315. // expects no outstanding transactions.
  316. axi_wready <= 1'b1;
  317. end
  318. else
  319. begin
  320. axi_wready <= 1'b0;
  321. end
  322. end
  323. end
  324. // Implement memory mapped register select and write logic generation
  325. // The write data is accepted and written to memory mapped registers when
  326. // axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
  327. // select byte enables of slave registers while writing.
  328. // These registers are cleared when reset (active low) is applied.
  329. // Slave register write enable is asserted when valid address and data are available
  330. // and the slave is ready to accept the write address and write data.
  331. assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
  332. always @( posedge S_AXI_ACLK )
  333. begin
  334. if ( S_AXI_ARESETN == 1'b0 )
  335. begin
  336. slv_reg0 <= 0;
  337. slv_reg1 <= 0;
  338. slv_reg2 <= 0;
  339. slv_reg3 <= 0;
  340. end
  341. else begin
  342. if (slv_reg_wren)
  343. begin
  344. case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
  345. 2'h0:
  346. for ( byte_index = 0; byte_index <= (`C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
  347. if ( S_AXI_WSTRB[byte_index] == 1 ) begin
  348. // Respective byte enables are asserted as per write strobes
  349. // Slave register 0
  350. slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
  351. end
  352. 2'h1:
  353. for ( byte_index = 0; byte_index <= (`C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
  354. if ( S_AXI_WSTRB[byte_index] == 1 ) begin
  355. // Respective byte enables are asserted as per write strobes
  356. // Slave register 1
  357. slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
  358. end
  359. 2'h2:
  360. for ( byte_index = 0; byte_index <= (`C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
  361. if ( S_AXI_WSTRB[byte_index] == 1 ) begin
  362. // Respective byte enables are asserted as per write strobes
  363. // Slave register 2
  364. slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
  365. end
  366. 2'h3:
  367. for ( byte_index = 0; byte_index <= (`C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
  368. if ( S_AXI_WSTRB[byte_index] == 1 ) begin
  369. // Respective byte enables are asserted as per write strobes
  370. // Slave register 3
  371. slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
  372. end
  373. default : begin
  374. slv_reg0 <= slv_reg0;
  375. slv_reg1 <= slv_reg1;
  376. slv_reg2 <= slv_reg2;
  377. slv_reg3 <= slv_reg3;
  378. end
  379. endcase
  380. end
  381. end
  382. end
  383. // Implement write response logic generation
  384. // The write response and response valid signals are asserted by the slave
  385. // when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
  386. // This marks the acceptance of address and indicates the status of
  387. // write transaction.
  388. always @( posedge S_AXI_ACLK )
  389. begin
  390. if ( S_AXI_ARESETN == 1'b0 )
  391. begin
  392. axi_bvalid <= 0;
  393. axi_bresp <= 2'b0;
  394. end
  395. else
  396. begin
  397. if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
  398. begin
  399. // indicates a valid write response is available
  400. axi_bvalid <= 1'b1;
  401. axi_bresp <= 2'b0; // 'OKAY' response
  402. end // work error responses in future
  403. else
  404. begin
  405. if (S_AXI_BREADY && axi_bvalid)
  406. //check if bready is asserted while bvalid is high)
  407. //(there is a possibility that bready is always asserted high)
  408. begin
  409. axi_bvalid <= 1'b0;
  410. end
  411. end
  412. end
  413. end
  414. // Implement axi_arready generation
  415. // axi_arready is asserted for one S_AXI_ACLK clock cycle when
  416. // S_AXI_ARVALID is asserted. axi_awready is
  417. // de-asserted when reset (active low) is asserted.
  418. // The read address is also latched when S_AXI_ARVALID is
  419. // asserted. axi_araddr is reset to zero on reset assertion.
  420. always @( posedge S_AXI_ACLK )
  421. begin
  422. if ( S_AXI_ARESETN == 1'b0 )
  423. begin
  424. axi_arready <= 1'b0;
  425. axi_araddr <= 32'b0;
  426. end
  427. else
  428. begin
  429. if (~axi_arready && S_AXI_ARVALID)
  430. begin
  431. // indicates that the slave has acceped the valid read address
  432. axi_arready <= 1'b1;
  433. // Read address latching
  434. axi_araddr <= S_AXI_ARADDR;
  435. end
  436. else
  437. begin
  438. axi_arready <= 1'b0;
  439. end
  440. end
  441. end
  442. // Implement axi_arvalid generation
  443. // axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
  444. // S_AXI_ARVALID and axi_arready are asserted. The slave registers
  445. // data are available on the axi_rdata bus at this instance. The
  446. // assertion of axi_rvalid marks the validity of read data on the
  447. // bus and axi_rresp indicates the status of read transaction.axi_rvalid
  448. // is deasserted on reset (active low). axi_rresp and axi_rdata are
  449. // cleared to zero on reset (active low).
  450. always @( posedge S_AXI_ACLK )
  451. begin
  452. if ( S_AXI_ARESETN == 1'b0 )
  453. begin
  454. axi_rvalid <= 0;
  455. axi_rresp <= 0;
  456. end
  457. else
  458. begin
  459. if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
  460. begin
  461. // Valid read data is available at the read data bus
  462. axi_rvalid <= 1'b1;
  463. axi_rresp <= 2'b0; // 'OKAY' response
  464. end
  465. else if (axi_rvalid && S_AXI_RREADY)
  466. begin
  467. // Read data is accepted by the master
  468. axi_rvalid <= 1'b0;
  469. end
  470. end
  471. end
  472. // Output register or memory read data
  473. always @( posedge S_AXI_ACLK )
  474. begin
  475. if ( S_AXI_ARESETN == 1'b0 )
  476. begin
  477. axi_rdata <= 0;
  478. end
  479. else
  480. begin
  481. // When there is a valid read address (S_AXI_ARVALID) with
  482. // acceptance of read address by the slave (axi_arready),
  483. // output the read dada
  484. if (slv_reg_rden)
  485. begin
  486. axi_rdata <= reg_data_out; // register read data
  487. end
  488. end
  489. end
  490. // end of AXI-Lite interface ==================================================
  491. reg [3:0] znAS_sync = 3'b111;
  492. reg [2:0] znUDS_sync = 3'b000;
  493. reg [2:0] znLDS_sync = 3'b000;
  494. reg [2:0] zREAD_sync = 3'b000;
  495. reg [2:0] znFCS_sync = 3'b111;
  496. reg [2:0] znDS1_sync = 3'b000;
  497. reg [2:0] znDS0_sync = 3'b000;
  498. reg [1:0] znRST_sync = 2'b11;
  499. reg [1:0] zDOE_sync = 2'b00;
  500. reg [4:0] zE7M_sync = 5'b00000;
  501. reg [2:0] znCFGIN_sync = 3'b000;
  502. reg [23:0] zaddr; // zorro 2 address
  503. reg [23:0] zaddr_sync;
  504. reg [23:0] zaddr_sync2;
  505. reg [15:0] zdata_in_sync;
  506. reg z2_addr_valid = 0;
  507. reg [23:0] z2_mapped_addr;
  508. reg z2_read = 0;
  509. reg z2_write = 0;
  510. reg z2_datastrobe_synced = 0;
  511. reg z2addr_in_ram = 0;
  512. reg z2addr_in_reg = 0;
  513. reg z2addr_autoconfig = 0;
  514. reg [31:0] ram_low = 32'h600000;
  515. reg [31:0] ram_high = 32'ha00000;
  516. reg [31:0] reg_low = 32'h601000;
  517. reg [31:0] reg_high = 32'h602000;
  518. reg z2_uds = 0;
  519. reg z2_lds = 0;
  520. reg [31:0] z3_ram_low = 32'h50000000;
  521. reg [31:0] z3_ram_high = 32'h50000000 + `Z3_RAM_SIZE -4;
  522. reg [31:0] z3_reg_low = 32'h50001000;
  523. reg [31:0] z3_reg_high = 32'h50002000;
  524. reg [15:0] data_z3_hi16;
  525. reg [15:0] data_z3_low16;
  526. reg [15:0] data_z3_hi16_latched;
  527. reg [15:0] data_z3_low16_latched;
  528. reg [15:0] data_in_z3_low16;
  529. reg [15:0] z3_din_high_s2;
  530. reg [15:0] z3_din_low_s2;
  531. reg [31:0] z3addr;
  532. reg [31:0] last_z3addr;
  533. reg [31:0] z3addr2;
  534. reg [31:0] z3addr3;
  535. reg [31:0] z3_mapped_addr;
  536. reg [31:0] z3_read_addr;
  537. reg [15:0] z3_read_data;
  538. reg z3_din_latch = 0;
  539. reg z3_fcs_state = 1;
  540. reg z3_end_cycle = 0;
  541. reg z3addr_in_ram = 0;
  542. reg z3addr_in_reg = 0;
  543. reg z3addr_autoconfig = 0;
  544. `ifdef ZORRO3
  545. reg ZORRO3 = 1;
  546. `else
  547. reg ZORRO3 = 0;
  548. `endif
  549. reg dataout = 0;
  550. reg dataout_z3 = 0;
  551. reg dataout_enable = 0;
  552. reg slaven = 0;
  553. reg dtack = 0;
  554. reg dtack_latched = 0;
  555. reg z_reset = 0;
  556. reg z_cfgin = 0;
  557. reg z_cfgin_lo = 0;
  558. reg z3_confdone = 0;
  559. reg zorro_read = 0;
  560. reg zorro_write = 0;
  561. reg zorro_interrupt = 0;
  562. assign ZORRO_INT6 = zorro_interrupt;
  563. reg [15:0] data_in;
  564. reg [31:0] rr_data;
  565. reg [15:0] data_out;
  566. reg [15:0] regdata_in;
  567. // ram arbiter
  568. (* mark_debug = "true" *) reg zorro_ram_read_request = 0;
  569. (* mark_debug = "true" *) reg zorro_ram_write_request = 0;
  570. reg [31:0] zorro_ram_read_addr;
  571. reg [3:0] zorro_ram_read_bytes;
  572. reg [31:0] zorro_ram_write_addr;
  573. reg [31:0] zorro_ram_write_data;
  574. reg [3:0] zorro_ram_write_bytes;
  575. reg [15:0] default_data = 'hffff; // causes read/write glitches on A2000 (data bus interference) when 0
  576. reg [1:0] zorro_write_capture_bytes = 0;
  577. reg [15:0] zorro_write_capture_data = 0;
  578. // z3 strobes
  579. reg z3_ds3=0;
  580. reg z3_ds2=0;
  581. reg z3_ds1=0;
  582. reg z3_ds0=0;
  583. // level shifter direction pins
  584. assign ZORRO_DATADIR = ZORRO_DOE & (dataout_enable | dataout_z3); // d2-d9 d10-15, d0-d1
  585. assign ZORRO_ADDRDIR = ZORRO_DOE & (dataout_z3); // a16-a23 <- input a8-a15 <- input
  586. assign ZORRO_ADDRDIR2 = 0; //ZORRO_DOE & (dataout_z3_latched);
  587. assign ZORRO_NBRN = 1; // TODO busmastering
  588. // data/addr out signals are gated by master's DOE signal
  589. wire ZORRO_DATA_T = ~(ZORRO_DOE & (dataout_enable | dataout_z3));
  590. wire ZORRO_ADDR_T = ~(ZORRO_DOE & dataout_z3);
  591. reg z_ovr = 0;
  592. assign ZORRO_NCINH = z_ovr?1'b1:1'b0; // inverse
  593. // "slave" signals are gated by master's FCS signal
  594. assign ZORRO_NSLAVE = (ZORRO_DOE & slaven)?1'b0:1'b1; // cannot gate by FCS for Z2
  595. assign ZORRO_NDTACK = (ZORRO_DOE & dtack) ?1'b1:1'b0; // inverse, pull-down transistor on output
  596. wire [22:0] z3_addr_out = {data_z3_low16_latched, 7'bZZZ_ZZZZ}; // FIXME this creates tri-cell warning?
  597. //wire [22:0] z3_addr_out = {data_z3_low16_latched, 7'b111_1111}; // FIXME this creates tri-cell warning?
  598. (* mark_debug = "true" *) wire [15:0] ZORRO_DATA_IN;
  599. (* mark_debug = "true" *) wire [22:0] ZORRO_ADDR_IN;
  600. //assign ZORRO_ADDR_IN = ZORRO_ADDR;
  601. //assign ZORRO_ADDR = (ZORRO_ADDR_T ? z3_addr_out : 23'bZZZ_ZZZZ_ZZZZ_ZZZZ_ZZZZ_ZZZZ);
  602. genvar i;
  603. generate
  604. for (i=0; i < 16; i=i+1) begin : ZORRO_DATABUS
  605. IOBUF u_iobuf_dq
  606. (
  607. .I (ZORRO3 ? data_z3_hi16_latched[i] : data_out[i]),
  608. .T (ZORRO_DATA_T),
  609. .IO (ZORRO_DATA[i]),
  610. .O (ZORRO_DATA_IN[i])
  611. );
  612. end
  613. endgenerate
  614. generate
  615. for (i=0; i < 23; i=i+1) begin : ZORRO_ADDRBUS
  616. IOBUF u_iobuf_dq
  617. (
  618. .I (z3_addr_out[i]),
  619. .T (ZORRO_ADDR_T),
  620. .IO (ZORRO_ADDR[i]),
  621. .O (ZORRO_ADDR_IN[i])
  622. );
  623. end
  624. endgenerate
  625. // autoconf output signal
  626. reg z_confout = 0;
  627. assign ZORRO_NCFGOUT = ZORRO_NCFGIN?1'b1:(~z_confout);
  628. reg [7:0] video_debug_reg;
  629. // -- synchronizers ------------------------------------------
  630. always @(posedge S_AXI_ACLK) begin
  631. znUDS_sync <= {znUDS_sync[1:0],ZORRO_NUDS};
  632. znLDS_sync <= {znLDS_sync[1:0],ZORRO_NLDS};
  633. znAS_sync <= {znAS_sync[1:0],ZORRO_NCCS};
  634. zREAD_sync <= {zREAD_sync[1:0],ZORRO_READ};
  635. znDS1_sync <= {znDS1_sync[1:0],ZORRO_NDS1};
  636. znDS0_sync <= {znDS0_sync[1:0],ZORRO_NDS0};
  637. znFCS_sync <= {znFCS_sync[1:0],ZORRO_NFCS};
  638. znCFGIN_sync<= {znCFGIN_sync[1:0],ZORRO_NCFGIN};
  639. zDOE_sync <= {zDOE_sync[0],ZORRO_DOE};
  640. znRST_sync <= {znRST_sync[0],ZORRO_NIORST};
  641. // Z2 ------------------------------------------------
  642. `ifndef ZORRO3
  643. z2_addr_valid <= (znAS_sync[2]==0 && znAS_sync[1]==0);
  644. zaddr <= ZORRO_ADDR_IN[22:0];
  645. zaddr_sync <= zaddr;
  646. zaddr_sync2 <= zaddr_sync;
  647. z2_mapped_addr <= {zaddr_sync2[22:0],1'b0};
  648. z2_read <= (zREAD_sync[0] == 1'b1);
  649. z2_write <= (zREAD_sync[0] == 1'b0);
  650. z2_datastrobe_synced <= (znUDS_sync==0 || znLDS_sync==0);
  651. z2_uds <= (znUDS_sync==0);
  652. z2_lds <= (znLDS_sync==0);
  653. z2addr_in_ram <= (z2_mapped_addr>=ram_low && z2_mapped_addr<ram_high);
  654. z2addr_in_reg <= (z2_mapped_addr>=reg_low && z2_mapped_addr<reg_high);
  655. if (znAS_sync[1]==0 && z2_mapped_addr>=`AUTOCONF_LOW && z2_mapped_addr<`AUTOCONF_HIGH)
  656. z2addr_autoconfig <= 1'b1;
  657. else
  658. z2addr_autoconfig <= 1'b0;
  659. `endif
  660. // Z3 ------------------------------------------------
  661. `ifdef ZORRO3
  662. z3addr2 <= {ZORRO_DATA_IN[15:8],ZORRO_ADDR_IN[22:1],2'b00};
  663. //z3addr2 <= {zD[15:8],zaddr[23:2],2'b00};
  664. // sample z3addr on falling edge of /FCS
  665. // A4000 needs [0] here, [1] worked for A3000
  666. case (znFCS_sync[1:0])
  667. 2'b01: begin
  668. // these guards are here so that the values are only sampled
  669. // on the edges of this signal
  670. //if (z3_fcs_state == 0) begin
  671. z3_fcs_state <= 1;
  672. z3addr <= 0;
  673. //end
  674. end
  675. 2'b10: begin
  676. // CHECK: if responding too quickly, this causes crashes
  677. //if (z3_fcs_state == 1) begin
  678. z3_fcs_state <= 0;
  679. z3addr <= z3addr2;
  680. //end
  681. end
  682. endcase
  683. z3addr_in_ram <= (z3addr >= z3_ram_low) && (z3addr < z3_ram_high);
  684. z3addr_in_reg <= (z3addr >= z3_reg_low) && (z3addr < z3_reg_high);
  685. z3addr_autoconfig <= (z3addr[31:16]=='hff00);
  686. z3_mapped_addr <= (z3addr-z3_ram_low);
  687. data_in_z3_low16 <= ZORRO_ADDR_IN[22:7]; //zA[22:7]; // FIXME why sample this twice?
  688. if (znUDS_sync[1]==0 || znLDS_sync[1]==0 || znDS1_sync[1]==0 || znDS0_sync[1]==0)
  689. z3_din_latch <= 1;
  690. else
  691. z3_din_latch <= 0;
  692. // pipelined for better timing
  693. if (z3_din_latch) begin
  694. z3_din_high_s2 <= zdata_in_sync; //zD;
  695. z3_din_low_s2 <= data_in_z3_low16; //zA[22:7];
  696. end
  697. // pipelined for better timing
  698. data_z3_hi16_latched <= data_z3_hi16;
  699. data_z3_low16_latched <= data_z3_low16;
  700. `endif
  701. // FIXME shared by z2/z3 with high load, split up?
  702. zdata_in_sync <= ZORRO_DATA_IN;
  703. zorro_read <= zREAD_sync[0];
  704. zorro_write <= ~zREAD_sync[0];
  705. //dtack_latched <= dtack;
  706. z_reset <= (znRST_sync==2'b00);
  707. z_cfgin <= (znCFGIN_sync==3'b000);
  708. z_cfgin_lo <= (znCFGIN_sync==3'b111);
  709. //video_debug_reg <= video_debug;
  710. end // always @ (posedge S_AXI_ACLK)
  711. reg [15:0] REVISION = 'h7a09; // z9
  712. // main FSM
  713. localparam RESET = 0;
  714. localparam Z2_CONFIGURING = 1;
  715. localparam Z2_IDLE = 2;
  716. localparam WAIT_WRITE = 3;
  717. localparam WAIT_WRITE2 = 4;
  718. localparam Z2_WRITE_FINALIZE = 5;
  719. localparam WAIT_READ = 6;
  720. localparam WAIT_READ2 = 7;
  721. localparam WAIT_READ3 = 8;
  722. localparam CONFIGURED = 9;
  723. localparam CONFIGURED_CLEAR = 10;
  724. localparam DECIDE_Z2_Z3 = 11;
  725. localparam Z3_IDLE = 12;
  726. localparam Z3_WRITE_UPPER = 13;
  727. localparam Z3_WRITE_LOWER = 14;
  728. localparam Z3_READ_UPPER = 15;
  729. localparam Z3_READ_LOWER = 16;
  730. localparam Z3_READ_DELAY = 17;
  731. localparam Z3_READ_DELAY1 = 18;
  732. localparam Z3_READ_DELAY2 = 19;
  733. localparam Z3_WRITE_PRE = 20;
  734. localparam Z3_WRITE_FINALIZE = 21;
  735. localparam Z3_ENDCYCLE = 22;
  736. localparam Z3_DTACK = 23;
  737. localparam Z3_CONFIGURING = 24;
  738. localparam Z2_REGWRITE = 25;
  739. localparam REGWRITE = 26;
  740. localparam REGREAD = 27;
  741. localparam Z2_REGREAD_POST = 28;
  742. localparam Z3_REGREAD_POST = 29;
  743. localparam Z3_REGWRITE = 30;
  744. localparam Z2_REGREAD = 31;
  745. localparam Z3_REGREAD = 32;
  746. localparam Z2_PRE_CONFIGURED = 34;
  747. localparam Z2_ENDCYCLE = 35;
  748. localparam WAIT_WRITE_DMA_Z2 = 36;
  749. localparam WAIT_WRITE_DMA_Z2_FINALIZE = 37;
  750. localparam RESET_DVID = 39;
  751. localparam COLD = 40;
  752. localparam WAIT_READ2B = 41; // delay states
  753. localparam WAIT_READ2C = 42;
  754. localparam WAIT_WRITE_DMA_Z3 = 43;
  755. localparam WAIT_WRITE_DMA_Z3_FINALIZE = 44;
  756. localparam Z3_AUTOCONF_READ = 45;
  757. localparam Z3_AUTOCONF_WRITE = 46;
  758. localparam Z3_AUTOCONF_READ_DLY = 47;
  759. localparam Z3_AUTOCONF_READ_DLY2 = 48;
  760. localparam Z3_REGWRITE_PRE = 49;
  761. localparam Z3_REGREAD_PRE = 50;
  762. localparam Z3_WRITE_PRE2 = 51;
  763. (* mark_debug = "true" *) reg [7:0] zorro_state = COLD;
  764. reg zorro_idle = 0;
  765. reg [7:0] read_counter = 0; // used by Z3
  766. reg [7:0] dataout_time = 'h02;
  767. reg [7:0] datain_time = 'h10;
  768. reg [7:0] datain_counter = 0;
  769. reg [23:0] last_addr = 0;
  770. reg [23:0] last_read_addr = 0;
  771. reg [15:0] last_data = 0;
  772. reg [15:0] last_read_data = 0;
  773. reg [15:0] zaddr_regpart = 0;
  774. reg [15:0] z3addr_regpart = 0;
  775. reg [15:0] regread_addr = 0;
  776. reg [15:0] regwrite_addr = 0;
  777. reg [31:0] axi_reg0 = 0;
  778. reg [31:0] axi_reg1 = 0;
  779. reg [31:0] axi_reg2 = 0;
  780. reg [31:0] axi_reg3 = 0;
  781. reg [31:0] video_control_data_zorro = 0;
  782. reg [7:0] video_control_op_zorro = 0;
  783. reg [31:0] video_control_data_axi = 0;
  784. reg [7:0] video_control_op_axi = 0;
  785. reg video_control_axi = 0;
  786. reg zorro_ram_read_flag = 0;
  787. reg zorro_ram_write_flag = 0;
  788. reg videocap_mode = 0;
  789. reg videocap_mode_in = 0;
  790. reg [9:0] videocap_hs = 0;
  791. reg [9:0] videocap_vs = 0;
  792. reg [2:0] videocap_state = 0;
  793. reg [23:0] videocap_rgbin = 0;
  794. reg [23:0] videocap_rgbin2 = 0;
  795. reg [9:0] videocap_x = 0;
  796. reg [9:0] videocap_x2 = 0;
  797. reg [9:0] videocap_y = 0;
  798. reg [9:0] videocap_y2 = 0;
  799. reg [9:0] videocap_ymax = 0;
  800. reg [9:0] videocap_ymax2 = 0;
  801. reg [9:0] videocap_ymax_sync = 0;
  802. reg [9:0] videocap_y3 = 0;
  803. reg [9:0] videocap_voffset = 'h1a; //'h2a;
  804. reg [9:0] videocap_prex_in = 'h33; //'h42;
  805. reg [9:0] videocap_prex = 'h33; //'h42;
  806. reg [9:0] videocap_height = 'h200; //'h117; // 'h127;
  807. parameter VCAPW = 399;
  808. reg [31:0] videocap_buf [0:VCAPW];
  809. reg [31:0] videocap_buf2 [0:VCAPW];
  810. reg videocap_lace_field=0;
  811. reg videocap_interlace=0;
  812. reg videocap_ntsc=0;
  813. reg [9:0] videocap_voffset2=0;
  814. reg E7M_PSEN = 0;
  815. reg E7M_PSINCDEC = 0;
  816. wire clkfbout_zz9000_ps_clk_wiz_1_0;
  817. wire e7m_shifted;
  818. wire e7m_shifted180;
  819. // video capture clock adjustment
  820. MMCME2_ADV #(
  821. .BANDWIDTH("OPTIMIZED"),
  822. .CLKFBOUT_MULT_F(32.000000),
  823. .CLKFBOUT_PHASE(0.000000),
  824. .CLKFBOUT_USE_FINE_PS("TRUE"),
  825. .CLKIN1_PERIOD(35.000000),
  826. .CLKIN2_PERIOD(0.000000),
  827. .CLKOUT0_DIVIDE_F(32.000000),
  828. .CLKOUT0_DUTY_CYCLE(0.500000),
  829. `ifdef ZORRO3
  830. .CLKOUT0_PHASE(90.000000),
  831. `else
  832. .CLKOUT0_PHASE(315.000000),
  833. `endif
  834. .CLKOUT0_USE_FINE_PS("TRUE"),
  835. .CLKOUT1_DIVIDE(32),
  836. .CLKOUT1_DUTY_CYCLE(0.500000),
  837. `ifdef ZORRO3
  838. .CLKOUT1_PHASE(270.000000),
  839. `else
  840. .CLKOUT1_PHASE(135.000000),
  841. `endif
  842. .CLKOUT1_USE_FINE_PS("TRUE"),
  843. .COMPENSATION("INTERNAL"),
  844. .DIVCLK_DIVIDE(1),
  845. .IS_CLKINSEL_INVERTED(1'b0),
  846. .IS_PSEN_INVERTED(1'b0),
  847. .IS_PSINCDEC_INVERTED(1'b0),
  848. .IS_PWRDWN_INVERTED(1'b0),
  849. .IS_RST_INVERTED(1'b0),
  850. .REF_JITTER1(0.001000),
  851. .REF_JITTER2(0.001000),
  852. .SS_EN("FALSE"),
  853. .SS_MODE("CENTER_HIGH"),
  854. .SS_MOD_PERIOD(10000),
  855. .STARTUP_WAIT("FALSE"))
  856. mmcm_adv_inst
  857. (.CLKFBIN(clkfbout_zz9000_ps_clk_wiz_1_0),
  858. .CLKFBOUT(clkfbout_zz9000_ps_clk_wiz_1_0),
  859. //.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
  860. //.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
  861. .CLKIN1(ZORRO_E7M),
  862. .CLKIN2(1'b0),
  863. .CLKINSEL(1'b1),
  864. //.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
  865. .CLKOUT0(e7m_shifted),
  866. //.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
  867. .CLKOUT1(e7m_shifted180),
  868. //.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
  869. .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
  870. .DCLK(1'b0),
  871. .DEN(1'b0),
  872. .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
  873. //.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
  874. //.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
  875. .DWE(1'b0),
  876. //.LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED),
  877. .PSCLK(S_AXI_ACLK),
  878. //.PSDONE(psdone),
  879. .PSEN(E7M_PSEN),
  880. .PSINCDEC(E7M_PSINCDEC),
  881. .PWRDWN(1'b0),
  882. .RST(1'b0));
  883. always @(posedge e7m_shifted) begin
  884. videocap_hs <= {videocap_hs[8:0], VCAP_HSYNC};
  885. videocap_vs <= {videocap_vs[8:0], VCAP_VSYNC};
  886. videocap_rgbin <= {VCAP_R7,VCAP_R6,VCAP_R5,VCAP_R4,VCAP_R3,VCAP_R2,VCAP_R1,VCAP_R0,
  887. VCAP_G7,VCAP_G6,VCAP_G5,VCAP_G4,VCAP_G3,VCAP_G2,VCAP_G1,VCAP_G0,
  888. VCAP_B7,VCAP_B6,VCAP_B5,VCAP_B4,VCAP_B3,VCAP_B2,VCAP_B1,VCAP_B0};
  889. //videocap_prex <= videocap_prex_in;
  890. if (videocap_vs[6:1]=='b111000) begin
  891. if (videocap_ymax[0]!=videocap_ymax2[0])
  892. videocap_interlace <= 1;
  893. else
  894. videocap_interlace <= 0;
  895. if (videocap_ymax>='h138)
  896. videocap_ntsc <= 0;
  897. else
  898. videocap_ntsc <= 1;
  899. videocap_lace_field <= videocap_ymax[0];
  900. if (videocap_interlace) begin
  901. videocap_y2 <= videocap_lace_field;
  902. videocap_voffset2 <= videocap_voffset<<1;
  903. end else begin
  904. videocap_y2 <= 0;
  905. videocap_voffset2 <= videocap_voffset;
  906. end
  907. videocap_ymax <= videocap_y3;
  908. videocap_ymax2 <= videocap_ymax;
  909. videocap_y3 <= 0;
  910. end else if (videocap_hs[6:1]=='b000011) begin
  911. videocap_x <= 0;
  912. if (videocap_interlace)
  913. videocap_y2 <= videocap_y2 + 2'b10;
  914. else
  915. videocap_y2 <= videocap_y2 + 1'b1;
  916. videocap_y3 <= videocap_y3 + 1'b1;
  917. end else if (videocap_x<VCAPW) begin
  918. videocap_x <= videocap_x + 1'b1;
  919. videocap_buf2[videocap_x-videocap_prex] <= {8'b0,videocap_rgbin};
  920. end
  921. end
  922. always @(posedge e7m_shifted180) begin
  923. videocap_rgbin2 <= {VCAP_R7,VCAP_R6,VCAP_R5,VCAP_R4,VCAP_R3,VCAP_R2,VCAP_R1,VCAP_R0,
  924. VCAP_G7,VCAP_G6,VCAP_G5,VCAP_G4,VCAP_G3,VCAP_G2,VCAP_G1,VCAP_G0,
  925. VCAP_B7,VCAP_B6,VCAP_B5,VCAP_B4,VCAP_B3,VCAP_B2,VCAP_B1,VCAP_B0};
  926. if (videocap_hs[6:1]=='b000011) begin
  927. videocap_x2 <= 0;
  928. end else if (videocap_x2<VCAPW) begin
  929. videocap_x2 <= videocap_x2 + 1'b1;
  930. videocap_buf[videocap_x2-videocap_prex] <= videocap_rgbin2;
  931. end
  932. end
  933. reg [11:0] videocap_save_x=0;
  934. reg [11:0] videocap_save_x2=0;
  935. reg [11:0] videocap_save_x3=0;
  936. reg [11:0] videocap_yoffset=0;
  937. reg [11:0] videocap_xoffset=0;
  938. reg [11:0] videocap_pitch=720;
  939. reg [9:0] videocap_save_line_done=1;
  940. reg [11:0] videocap_save_y=0;
  941. reg [31:0] videocap_save_y2=0;
  942. reg [31:0] videocap_save_addr=0;
  943. reg [3:0] videocap_save_state=0; // FIXME
  944. reg m00_axi_awready_reg;
  945. reg m00_axi_wready_reg;
  946. reg videocap_mode_sync;
  947. reg [31:0] m00_axi_awaddr_out;
  948. reg [31:0] m00_axi_wdata_out;
  949. reg m00_axi_awvalid_out;
  950. reg m00_axi_wvalid_out;
  951. always @(posedge S_AXI_ACLK) begin
  952. // VIDEOCAP
  953. videocap_mode_sync <= videocap_mode;
  954. m00_axi_awlen <= 'h0; // 1 burst (1 write)
  955. m00_axi_awsize <= 'h2; // 2^2 == 4 bytes
  956. m00_axi_awburst <= 'h0; // FIXED (non incrementing)
  957. m00_axi_awcache <= 'h1;
  958. m00_axi_awlock <= 'h0;
  959. m00_axi_awprot <= 'h0;
  960. m00_axi_awqos <= 'h0;
  961. m00_axi_wlast <= 'h1;
  962. m00_axi_bready <= 'h1;
  963. m00_axi_awready_reg <= m00_axi_awready;
  964. m00_axi_wready_reg <= m00_axi_wready;
  965. videocap_save_x2 <= (videocap_save_x);
  966. videocap_save_x3 <= (videocap_save_x);
  967. videocap_save_y2 <= (videocap_y2-videocap_voffset2);
  968. videocap_save_addr <= (videocap_save_y2)*videocap_pitch+videocap_save_x2;
  969. video_control_interlace <= videocap_interlace;
  970. m00_axi_awaddr_out <= `VIDEOCAP_ADDR+(videocap_save_addr<<2); // <<2 = *4 FIXME select sane area and protect it
  971. // FIXME for some computers (?) buf and buf2 are swapped... some timing race condition
  972. if (videocap_save_x3[0])
  973. m00_axi_wdata_out <= videocap_buf2[videocap_save_x3>>1];
  974. else
  975. m00_axi_wdata_out <= videocap_buf[videocap_save_x3>>1];
  976. if (videocap_mode_sync) begin
  977. m00_axi_awaddr <= m00_axi_awaddr_out;
  978. m00_axi_wdata <= m00_axi_wdata_out;
  979. m00_axi_awvalid <= m00_axi_awvalid_out;
  980. m00_axi_wvalid <= m00_axi_wvalid_out;
  981. m00_axi_wstrb <= 4'b1111;
  982. // save newly captured line
  983. case (videocap_save_state)
  984. 0:
  985. if (videocap_save_line_done!=videocap_y2 && videocap_x>8) begin
  986. m00_axi_awvalid_out <= 1;
  987. m00_axi_wvalid_out <= 1;
  988. if (m00_axi_awready) begin
  989. videocap_save_state <= 1;
  990. end
  991. end
  992. 1: begin
  993. m00_axi_awvalid_out <= 0;
  994. m00_axi_wvalid_out <= 0;
  995. videocap_save_x <= videocap_save_x + 1'b1;
  996. if (videocap_save_x > videocap_pitch + 1'b1) begin // FIXME was 722
  997. videocap_save_line_done <= videocap_y2;
  998. videocap_save_x <= 0;
  999. end
  1000. videocap_save_state <= 2;
  1001. end
  1002. 2: begin
  1003. //if (m00_axi_bvalid) begin
  1004. videocap_save_state <= 0;
  1005. //end
  1006. end
  1007. endcase
  1008. end else begin
  1009. m00_axi_awvalid <= 0;
  1010. m00_axi_wvalid <= 0;
  1011. end
  1012. end
  1013. // -- main zorro fsm ---------------------------------------------
  1014. always @(posedge S_AXI_ACLK) begin
  1015. zorro_idle <= ((zorro_state==Z2_IDLE)||(zorro_state==Z3_IDLE));
  1016. videocap_mode <= videocap_mode_in;
  1017. if (/*z_cfgin_lo ||*/ z_reset) begin
  1018. zorro_state <= RESET;
  1019. end else
  1020. case (zorro_state)
  1021. COLD: begin
  1022. zorro_state <= RESET;
  1023. end
  1024. RESET: begin
  1025. dataout_enable <= 0;
  1026. dataout <= 0;
  1027. dataout_z3 <= 0;
  1028. slaven <= 0;
  1029. z_ovr <= 0;
  1030. z_confout <= 0;
  1031. z3_confdone <= 0;
  1032. zorro_ram_read_request <= 0;
  1033. zorro_ram_write_request <= 0;
  1034. zorro_interrupt <= 0;
  1035. video_control_data_zorro <= 0;
  1036. video_control_op_zorro <= 0;
  1037. video_control_data_axi <= 0;
  1038. video_control_op_axi <= 0;
  1039. if (!z_reset)
  1040. zorro_state <= DECIDE_Z2_Z3;
  1041. //count_writes <= 0;
  1042. videocap_mode_in <= 1;
  1043. last_z3addr <= 0;
  1044. // RESET video controller
  1045. //video_control_op <= 11;
  1046. end
  1047. DECIDE_Z2_Z3: begin
  1048. //video_control_op <= 0;
  1049. `ifndef ZORRO3
  1050. if (z2addr_autoconfig) begin
  1051. //ZORRO3 <= 0;
  1052. zorro_state <= Z2_CONFIGURING;
  1053. end
  1054. `endif
  1055. `ifdef ZORRO3
  1056. if (z3addr_autoconfig) begin
  1057. //ZORRO3 <= 1;
  1058. zorro_state <= Z3_CONFIGURING;
  1059. end
  1060. `endif
  1061. end
  1062. `ifdef ZORRO3
  1063. Z3_AUTOCONF_READ_DLY: begin
  1064. // wait for data to be latched out
  1065. zorro_state <= Z3_AUTOCONF_READ_DLY2;
  1066. end
  1067. Z3_AUTOCONF_READ_DLY2: begin
  1068. // wait for data to be latched out
  1069. zorro_state <= Z3_DTACK;
  1070. end
  1071. Z3_AUTOCONF_READ: begin
  1072. dataout_z3 <= 1;
  1073. slaven <= 1;
  1074. zorro_state <= Z3_AUTOCONF_READ_DLY;
  1075. last_z3addr <= z3addr;
  1076. case (z3addr[15:0])
  1077. 'h0000: data_z3_hi16 <= 'b1000_1111_1111_1111; // zorro 3 (10), no pool link (0), autoboot ROM (1)
  1078. 'h0100: data_z3_hi16 <= 'b0100_1111_1111_1111; // next board unrelated (0), 256MB
  1079. 'h0004: data_z3_hi16 <= 'b1111_1111_1111_1111; // product number
  1080. 'h0104: data_z3_hi16 <= 'b1011_1111_1111_1111; // (4)
  1081. 'h0008: data_z3_hi16 <= 'b0000_1111_1111_1111; // flags inverted 0111 io,shutup,extension,reserved(1)
  1082. 'h0108: data_z3_hi16 <= 'b1111_1111_1111_1111; // inverted zero
  1083. 'h000c: data_z3_hi16 <= 'b1111_1111_1111_1111; // reserved?
  1084. 'h010c: data_z3_hi16 <= 'b1111_1111_1111_1111; //
  1085. 'h0010: data_z3_hi16 <= 'b1001_1111_1111_1111; // manufacturer high byte inverted
  1086. 'h0110: data_z3_hi16 <= 'b0010_1111_1111_1111; //
  1087. 'h0014: data_z3_hi16 <= 'b1001_1111_1111_1111; // manufacturer low byte
  1088. 'h0114: data_z3_hi16 <= 'b0001_1111_1111_1111;
  1089. 'h0018: data_z3_hi16 <= 'b1111_1111_1111_1111; // serial 01 01 01 01
  1090. 'h0118: data_z3_hi16 <= 'b1110_1111_1111_1111; //
  1091. 'h001c: data_z3_hi16 <= 'b1111_1111_1111_1111; //
  1092. 'h011c: data_z3_hi16 <= 'b1110_1111_1111_1111; //
  1093. 'h0020: data_z3_hi16 <= 'b1111_1111_1111_1111; //
  1094. 'h0120: data_z3_hi16 <= 'b1110_1111_1111_1111; //
  1095. 'h0024: data_z3_hi16 <= 'b1111_1111_1111_1111; //
  1096. 'h0124: data_z3_hi16 <= 'b1110_1111_1111_1111; //
  1097. /*'h0028: data_z3_hi16 <= 'b1111_1111_1111_1111; // autoboot rom vector (er_InitDiagVec)
  1098. 'h0128: data_z3_hi16 <= 'b1111_1111_1111_1111; // ff7f = ~0080
  1099. 'h002c: data_z3_hi16 <= 'b0111_1111_1111_1111;
  1100. 'h012c: data_z3_hi16 <= 'b1111_1111_1111_1111;*/
  1101. default: data_z3_hi16 <= 'b1111_1111_1111_1110; // FIXME
  1102. endcase
  1103. end
  1104. Z3_AUTOCONF_WRITE: begin
  1105. slaven <= 1;
  1106. // was [2] for A3000
  1107. if (z3_din_latch) begin
  1108. zorro_state <= Z3_DTACK;
  1109. casex (z3addr[15:0])
  1110. 'hXX44: begin
  1111. z3_ram_low[31:16] <= zdata_in_sync;
  1112. z_confout <= 1;
  1113. z3_confdone <= 1;
  1114. end
  1115. 'hXX48: begin
  1116. end
  1117. 'hXX4c: begin
  1118. // shutup
  1119. z_confout <= 1;
  1120. z3_confdone <= 1;
  1121. end
  1122. endcase
  1123. end
  1124. end
  1125. Z3_CONFIGURING: begin
  1126. // FIXME why?
  1127. //data_z3_low16 <= 'hffff;
  1128. // was [2] for A3000
  1129. if (z_cfgin && z3addr_autoconfig) begin
  1130. if (zorro_read) begin
  1131. // autoconfig ROM
  1132. zorro_state <= Z3_AUTOCONF_READ;
  1133. end else begin
  1134. // write to autoconfig register
  1135. zorro_state <= Z3_AUTOCONF_WRITE;
  1136. end
  1137. end
  1138. dataout_z3 <= 0;
  1139. slaven <= 0;
  1140. dtack <= 0;
  1141. end
  1142. Z3_DTACK: begin
  1143. if (z3_fcs_state == 1) begin
  1144. dtack <= 0;
  1145. dataout_z3 <= 0;
  1146. slaven <= 0;
  1147. if (z3_confdone) begin
  1148. zorro_state <= CONFIGURED;
  1149. end else
  1150. zorro_state <= Z3_CONFIGURING;
  1151. end else
  1152. dtack <= 1;
  1153. end
  1154. `endif
  1155. CONFIGURED: begin
  1156. ram_high <= ram_low + `RAM_SIZE;
  1157. reg_low <= ram_low + 'h1000;
  1158. reg_high <= ram_low + 'h2000;
  1159. z3_ram_high <= z3_ram_low + `Z3_RAM_SIZE;
  1160. z3_reg_low <= z3_ram_low + 'h1000;
  1161. z3_reg_high <= z3_ram_low + 'h2000;
  1162. zorro_state <= CONFIGURED_CLEAR;
  1163. end
  1164. CONFIGURED_CLEAR: begin
  1165. `ifdef ZORRO3
  1166. zorro_state <= Z3_IDLE;
  1167. `else
  1168. zorro_state <= Z2_IDLE;
  1169. `endif
  1170. end
  1171. // ---------------------------------------------------------------------------------
  1172. `ifndef ZORRO3
  1173. Z2_CONFIGURING: begin
  1174. z_ovr <= 0;
  1175. if (z2addr_autoconfig && z_cfgin) begin
  1176. if (z2_read) begin
  1177. // read iospace 'he80000 (Autoconfig ROM)
  1178. dataout_enable <= 1;
  1179. dataout <= 1;
  1180. slaven <= 1;
  1181. case (z2_mapped_addr[7:0])
  1182. 8'h00: data_out <= 'b1101_1111_1111_1111; // zorro 2 (11), no pool (0) rom (1)
  1183. 8'h02: data_out <= 'b0111_1111_1111_1111; // next board unrelated (0), 4mb (110 for 2mb)
  1184. 8'h04: data_out <= 'b1111_1111_1111_1111; // product number
  1185. 8'h06: data_out <= 'b1100_1111_1111_1111; // (3)
  1186. 8'h08: data_out <= 'b0011_1111_1111_1111; // flags inverted 0011
  1187. 8'h0a: data_out <= 'b1110_1111_1111_1111; // inverted 0001 = OS sized
  1188. 8'h10: data_out <= 'b1001_1111_1111_1111; // manufacturer high byte inverted (02)
  1189. 8'h12: data_out <= 'b0010_1111_1111_1111; //
  1190. 8'h14: data_out <= 'b1001_1111_1111_1111; // manufacturer low byte (9a)
  1191. 8'h16: data_out <= 'b0001_1111_1111_1111;
  1192. 8'h18: data_out <= 'b1111_1111_1111_1111; // serial 01 01 01 01
  1193. 8'h1a: data_out <= 'b1110_1111_1111_1111; //
  1194. 8'h1c: data_out <= 'b1111_1111_1111_1111; //
  1195. 8'h1e: data_out <= 'b1110_1111_1111_1111; //
  1196. 8'h20: data_out <= 'b1111_1111_1111_1111; //
  1197. 8'h22: data_out <= 'b1110_1111_1111_1111; //
  1198. 8'h24: data_out <= 'b1111_1111_1111_1111; //
  1199. 8'h26: data_out <= 'b1110_1111_1111_1111; //
  1200. /*8'h28: data_out <= 'b1111_1111_1111_1111; // autoboot rom vector (er_InitDiagVec)
  1201. 8'h2a: data_out <= 'b1111_1111_1111_1111; // ff7f = ~0080
  1202. 8'h2c: data_out <= 'b0111_1111_1111_1111;
  1203. 8'h2e: data_out <= 'b1111_1111_1111_1111;*/
  1204. //'h000040: data <= 'b0000_0000_0000_0000; // interrupts (not inverted)
  1205. //'h000042: data <= 'b0000_0000_0000_0000; //
  1206. default: data_out <= 'b1111_1111_1111_1111;
  1207. endcase
  1208. end else begin
  1209. // write to autoconfig register
  1210. if (z2_datastrobe_synced) begin
  1211. case (z2_mapped_addr[7:0])
  1212. 8'h48: begin
  1213. ram_low[31:24] <= 8'h0;
  1214. ram_low[23:20] <= zdata_in_sync[15:12];
  1215. ram_low[15:0] <= 16'h0;
  1216. zorro_state <= Z2_PRE_CONFIGURED; // configured
  1217. end
  1218. 8'h4a: begin
  1219. ram_low[31:24] <= 8'h0;
  1220. ram_low[19:16] <= zdata_in_sync[15:12];
  1221. ram_low[15:0] <= 16'h0;
  1222. end
  1223. 8'h4c: begin
  1224. zorro_state <= Z2_PRE_CONFIGURED; // configured, shut up
  1225. end
  1226. endcase
  1227. end
  1228. end
  1229. end else begin
  1230. // no address match
  1231. dataout <= 0;
  1232. dataout_enable <= 0;
  1233. slaven <= 0;
  1234. end
  1235. end
  1236. Z2_PRE_CONFIGURED: begin
  1237. if (znAS_sync[2]==1) begin
  1238. z_confout<=1;
  1239. zorro_state <= CONFIGURED;
  1240. end
  1241. end
  1242. Z2_IDLE: begin
  1243. if (z2_addr_valid) begin
  1244. if (z2_write && z2addr_in_reg) begin
  1245. // write to register
  1246. dataout_enable <= 0;
  1247. dataout <= 0;
  1248. slaven <= 1;
  1249. z_ovr <= 1;
  1250. zaddr_regpart <= z2_mapped_addr;
  1251. zorro_state <= Z2_REGWRITE;
  1252. end else if (z2_read && z2addr_in_reg) begin
  1253. // read from registers
  1254. dataout_enable <= 1;
  1255. dataout <= 1;
  1256. data_out <= default_data; //'hffff;
  1257. slaven <= 1;
  1258. z_ovr <= 1;
  1259. zaddr_regpart <= z2_mapped_addr;
  1260. zorro_state <= Z2_REGREAD;
  1261. end else if (z2_read && z2addr_in_ram) begin
  1262. // read RAM
  1263. // request ram access from arbiter
  1264. last_addr <= z2_mapped_addr-ram_low; // differently done in z3
  1265. data_out <= default_data; //'hffff;
  1266. dataout_enable <= 1;
  1267. dataout <= 1;
  1268. slaven <= 1;
  1269. z_ovr <= 1;
  1270. zorro_state <= WAIT_READ3;
  1271. end else if (z2_write && z2addr_in_ram) begin
  1272. // write RAM
  1273. last_addr <= z2_mapped_addr-ram_low;
  1274. dataout_enable <= 0;
  1275. dataout <= 0;
  1276. datain_counter <= 0;
  1277. slaven <= 1;
  1278. z_ovr <= 1;
  1279. //count_writes <= count_writes + 1;
  1280. zorro_state <= WAIT_WRITE;
  1281. end else begin
  1282. dataout <= 0;
  1283. dataout_enable <= 0;
  1284. slaven <= 0;
  1285. end
  1286. end else begin
  1287. dataout <= 0;
  1288. dataout_enable <= 0;
  1289. slaven <= 0;
  1290. end
  1291. end
  1292. Z2_REGWRITE: begin
  1293. if (z2_datastrobe_synced) begin
  1294. regdata_in <= zdata_in_sync;
  1295. regwrite_addr <= zaddr_regpart;
  1296. zorro_state <= REGWRITE;
  1297. end
  1298. end
  1299. WAIT_READ3: begin
  1300. zorro_ram_read_addr <= last_addr;
  1301. zorro_ram_read_request <= 1;
  1302. zorro_state <= WAIT_READ2;
  1303. end
  1304. WAIT_READ2: begin
  1305. if (zorro_ram_read_flag) begin
  1306. zorro_ram_read_request <= 0;
  1307. data_out <= axi_reg1[15:0];
  1308. zorro_state <= WAIT_READ2B;
  1309. end
  1310. end
  1311. WAIT_READ2B: begin
  1312. zorro_state <= WAIT_READ2C;
  1313. end
  1314. WAIT_READ2C: begin
  1315. zorro_state <= Z2_ENDCYCLE;
  1316. end
  1317. WAIT_WRITE: begin
  1318. if (z2_datastrobe_synced) begin
  1319. zorro_write_capture_bytes <= {~znUDS_sync[1],~znLDS_sync[1]};
  1320. zorro_write_capture_data <= zdata_in_sync; //_sync;
  1321. //if (last_addr<'h10000 || videocap_mode)
  1322. zorro_state <= WAIT_WRITE2;
  1323. //else
  1324. // zorro_state <= WAIT_WRITE_DMA_Z2;
  1325. end
  1326. end
  1327. WAIT_WRITE2: begin
  1328. zorro_ram_write_addr <= last_addr;
  1329. zorro_ram_write_bytes <= {2'b0,zorro_write_capture_bytes};
  1330. zorro_ram_write_data <= {16'b0,zorro_write_capture_data};
  1331. zorro_ram_write_request <= 1;
  1332. zorro_state <= Z2_WRITE_FINALIZE;
  1333. end
  1334. /*WAIT_WRITE_DMA_Z2: begin
  1335. if (last_addr[1])
  1336. m00_axi_wstrb <= {zorro_write_capture_bytes[0],zorro_write_capture_bytes[1],2'b0};
  1337. else
  1338. m00_axi_wstrb <= {2'b0,zorro_write_capture_bytes[0],zorro_write_capture_bytes[1]};
  1339. // FIXME
  1340. m00_axi_awaddr <= (last_addr+`ARM_MEMORY_START)&'hfffffc;
  1341. m00_axi_wdata <= {zorro_write_capture_data[7:0],zorro_write_capture_data[15:8],zorro_write_capture_data[7:0],zorro_write_capture_data[15:8]};
  1342. m00_axi_awvalid <= 1;
  1343. m00_axi_wvalid <= 1;
  1344. if (m00_axi_awready) begin // TODO wready?
  1345. zorro_state <= WAIT_WRITE_DMA_Z2_FINALIZE;
  1346. end
  1347. end*/
  1348. /*WAIT_WRITE_DMA_Z2_FINALIZE: begin
  1349. if (m00_axi_wready) begin
  1350. m00_axi_awvalid <= 0;
  1351. m00_axi_wvalid <= 0;
  1352. zorro_state <= Z2_ENDCYCLE;
  1353. end
  1354. end*/
  1355. Z2_WRITE_FINALIZE: begin
  1356. if (zorro_ram_write_flag) begin
  1357. zorro_state <= Z2_ENDCYCLE;
  1358. zorro_ram_write_request <= 0;
  1359. end
  1360. end
  1361. Z2_ENDCYCLE: begin
  1362. z_ovr <= 0;
  1363. if (!z2_addr_valid) begin
  1364. dtack <= 0;
  1365. slaven <= 0;
  1366. dataout_enable <= 0;
  1367. dataout <= 0;
  1368. zorro_state <= Z2_IDLE;
  1369. end else
  1370. dtack <= 1;
  1371. end
  1372. // 16bit reg read
  1373. Z2_REGREAD_POST: begin
  1374. if (zaddr_regpart[1]==1'b1)
  1375. data_out <= rr_data[15:0];
  1376. else
  1377. data_out <= rr_data[31:16];
  1378. zorro_state <= Z2_ENDCYCLE;
  1379. end
  1380. // relaxing the data pipeline a bit
  1381. Z2_REGREAD: begin
  1382. regread_addr <= zaddr_regpart;
  1383. zorro_state <= REGREAD;
  1384. end
  1385. `endif
  1386. `ifdef ZORRO3
  1387. // =========================================================================
  1388. // ZORRO 3
  1389. // =========================================================================
  1390. // questionable direct access
  1391. Z3_REGWRITE_PRE: begin
  1392. if (znDS1_sync[2]==0) begin
  1393. regdata_in <= data_in_z3_low16;
  1394. z3addr_regpart <= (z3addr[15:0])|16'h2;
  1395. zorro_state <= Z3_REGWRITE;
  1396. end else if (znUDS_sync[2]==0) begin
  1397. regdata_in <= zdata_in_sync;
  1398. z3addr_regpart <= z3addr[15:0];
  1399. zorro_state <= Z3_REGWRITE;
  1400. end
  1401. end
  1402. Z3_REGREAD_PRE: begin
  1403. z3addr_regpart <= z3addr[15:0]; //|16'h2;
  1404. //if (z3_din_latch) begin
  1405. zorro_state <= Z3_REGREAD;
  1406. //end
  1407. dataout_z3 <= 1;
  1408. end
  1409. Z3_IDLE: begin
  1410. read_counter <= 0;
  1411. if (z3_fcs_state==0) begin
  1412. // falling edge of /FCS
  1413. if (zorro_write && z3addr_in_reg) begin
  1414. // FIXME doesn't support 32 bit access
  1415. // write to register
  1416. zorro_state <= Z3_REGWRITE_PRE;
  1417. slaven <= 1;
  1418. end else if (zorro_read && z3addr_in_reg) begin
  1419. // read registers
  1420. data_z3_hi16 <= default_data;
  1421. data_z3_low16 <= default_data;
  1422. zorro_state <= Z3_REGREAD_PRE;
  1423. slaven <= 1;
  1424. end else if (z3addr_in_ram && zorro_write) begin
  1425. // write to memory
  1426. //read_counter <= 0;
  1427. slaven <= 1;
  1428. zorro_state <= Z3_WRITE_PRE;
  1429. end else if (z3addr_in_ram && zorro_read) begin
  1430. // read from memory
  1431. data_z3_hi16 <= default_data;
  1432. data_z3_low16 <= default_data;
  1433. slaven <= 1;
  1434. zorro_state <= Z3_READ_UPPER;
  1435. end else begin
  1436. // address not recognized
  1437. slaven <= 0;
  1438. end
  1439. end else begin
  1440. // not in a cycle
  1441. slaven <= 0;
  1442. end
  1443. end
  1444. Z3_REGWRITE: begin
  1445. regwrite_addr <= z3addr_regpart;
  1446. zorro_state <= REGWRITE;
  1447. dtack <= 1;
  1448. end
  1449. Z3_REGREAD: begin
  1450. regread_addr <= z3addr_regpart;
  1451. zorro_state <= REGREAD;
  1452. end
  1453. // 32bit reg read
  1454. Z3_REGREAD_POST: begin
  1455. data_z3_hi16 <= rr_data[31:16];
  1456. data_z3_low16 <= rr_data[15:0];
  1457. zorro_state <= Z3_ENDCYCLE;
  1458. dtack <= 1;
  1459. end
  1460. Z3_READ_UPPER: begin
  1461. zorro_state <= Z3_READ_DELAY1;
  1462. last_z3addr <= z3_mapped_addr;
  1463. zorro_ram_read_addr <= z3_mapped_addr;
  1464. zorro_ram_read_bytes <= 4'b1111;
  1465. zorro_ram_read_request <= 1;
  1466. dataout_z3 <= 1; // enable data output
  1467. // dummy read
  1468. /*dtack <= 1;
  1469. data_z3_hi16 <= 'hffff;
  1470. data_z3_low16 <= 'hffff;
  1471. zorro_state <= Z3_ENDCYCLE;*/
  1472. end
  1473. Z3_READ_DELAY1: begin
  1474. data_z3_hi16 <= axi_reg1[31:16];
  1475. data_z3_low16 <= axi_reg1[15:0];
  1476. //read_counter <= 0;
  1477. if (zorro_ram_read_flag) begin
  1478. zorro_ram_read_request <= 0; // acknowledge read request done
  1479. zorro_state <= Z3_READ_DELAY2; // CHECK DELAY
  1480. end
  1481. end
  1482. Z3_READ_DELAY2: begin
  1483. if (!zorro_ram_read_flag) begin
  1484. zorro_state <= Z3_ENDCYCLE;
  1485. dtack <= 1;
  1486. slaven <= 0;
  1487. end
  1488. end
  1489. Z3_WRITE_PRE: begin
  1490. // FIXME was [2] for A3000
  1491. z3_ds0 <= ~znDS0_sync[1];
  1492. z3_ds1 <= ~znDS1_sync[1];
  1493. z3_ds2 <= ~znLDS_sync[1];
  1494. z3_ds3 <= ~znUDS_sync[1];
  1495. if (~znDS0_sync[1]||~znDS1_sync[1]||~znLDS_sync[1]||~znUDS_sync[1]) begin
  1496. //if (z3_mapped_addr<'h10000 || videocap_mode)
  1497. zorro_state <= Z3_WRITE_PRE2;
  1498. //else
  1499. // zorro_state <= WAIT_WRITE_DMA_Z3;
  1500. end
  1501. end
  1502. Z3_WRITE_PRE2: begin
  1503. // 1 more time for good measure
  1504. z3_ds0 <= ~znDS0_sync[1];
  1505. z3_ds1 <= ~znDS1_sync[1];
  1506. z3_ds2 <= ~znLDS_sync[1];
  1507. z3_ds3 <= ~znUDS_sync[1];
  1508. zorro_state <= Z3_WRITE_UPPER;
  1509. end
  1510. Z3_WRITE_UPPER: begin
  1511. last_z3addr <= z3_mapped_addr;
  1512. zorro_ram_write_addr <= z3_mapped_addr;
  1513. zorro_ram_write_bytes <= {z3_ds3,z3_ds2,z3_ds1,z3_ds0};
  1514. zorro_ram_write_data <= {z3_din_high_s2,z3_din_low_s2};
  1515. zorro_ram_write_request <= 1;
  1516. zorro_state <= Z3_WRITE_FINALIZE;
  1517. end
  1518. Z3_WRITE_FINALIZE: begin
  1519. if (zorro_ram_write_flag) begin
  1520. zorro_ram_write_request <= 0; // acknowledge write request done
  1521. zorro_state <= Z3_ENDCYCLE;
  1522. dtack <= 1;
  1523. slaven <= 0;
  1524. end
  1525. end
  1526. /*WAIT_WRITE_DMA_Z3: begin
  1527. m00_axi_wstrb <= {z3_ds0,z3_ds1,z3_ds2,z3_ds3};
  1528. // FIXME
  1529. m00_axi_awaddr <= (z3_mapped_addr&'h1ffffffc)+`ARM_MEMORY_START; // max 256MB
  1530. m00_axi_wdata <= {z3_din_low_s2[7:0],z3_din_low_s2[15:8],z3_din_high_s2[7:0],z3_din_high_s2[15:8]};
  1531. m00_axi_awvalid <= 1;
  1532. m00_axi_wvalid <= 1;
  1533. if (m00_axi_awready) begin // TODO wready?
  1534. zorro_state <= WAIT_WRITE_DMA_Z3_FINALIZE;
  1535. end
  1536. end*/
  1537. /*WAIT_WRITE_DMA_Z3_FINALIZE: begin
  1538. if (m00_axi_wready) begin
  1539. m00_axi_awvalid <= 0;
  1540. m00_axi_wvalid <= 0;
  1541. zorro_state <= Z3_ENDCYCLE;
  1542. //dtack <= 1; // CHECKME
  1543. end
  1544. end*/
  1545. Z3_ENDCYCLE: begin
  1546. read_counter <= read_counter + 1'b1;
  1547. if (read_counter >= 10) begin
  1548. dtack <= 0;
  1549. end
  1550. if (z3_fcs_state==1) begin
  1551. dtack <= 0;
  1552. slaven <= 0;
  1553. dataout_z3 <= 0;
  1554. zorro_state <= Z3_IDLE;
  1555. end
  1556. end
  1557. `endif
  1558. // FIXME why is there no dataout time on REGREAD? (see memory reads)
  1559. // now fixed for Z3, still pending for Z2
  1560. REGREAD: begin
  1561. // TODO split up into z3/z2
  1562. `ifdef ZORRO3
  1563. zorro_state <= Z3_REGREAD_POST;
  1564. `else
  1565. zorro_state <= Z2_REGREAD_POST;
  1566. `endif
  1567. case (regread_addr&'hff)
  1568. /*'h00: begin
  1569. rr_data <= video_control_data;
  1570. end
  1571. 'h04: begin
  1572. rr_data <= video_control_op;
  1573. end*/
  1574. 'h00: begin
  1575. // this flag is read by Amiga software to check if all writes are done
  1576. rr_data <= 0; //zorro_ram_write_request;
  1577. end
  1578. default: begin
  1579. rr_data[31:16] <= REVISION;
  1580. rr_data[15:0] <= REVISION;
  1581. end
  1582. endcase
  1583. end
  1584. REGWRITE: begin
  1585. `ifdef ZORRO3
  1586. zorro_state <= Z3_ENDCYCLE;
  1587. `else
  1588. zorro_state <= Z2_ENDCYCLE;
  1589. `endif
  1590. case (regwrite_addr&'hff)
  1591. 'h00: video_control_data_zorro[31:16] <= regdata_in[15:0];
  1592. 'h02: video_control_data_zorro[15:0] <= regdata_in[15:0];
  1593. 'h04: video_control_op_zorro[7:0] <= regdata_in[7:0]; // FIXME
  1594. 'h06: videocap_mode_in <= regdata_in[0];
  1595. //'h14: zorro_interrupt <= regdata_in[0];
  1596. //'h08: videocap_prex_in <= regdata_in;
  1597. //'h10: E7M_PSINCDEC <= regdata_in[0];
  1598. //'h12: E7M_PSEN <= regdata_in[0];
  1599. endcase
  1600. end
  1601. endcase
  1602. // PSEN reset
  1603. if (E7M_PSEN==1'b1) E7M_PSEN <= 1'b0;
  1604. // ARM video control
  1605. if (axi_reg2[31]==1'b1) begin
  1606. video_control_data_axi <= axi_reg3[31:0];
  1607. video_control_op_axi <= axi_reg2[7:0];
  1608. video_control_axi <= 1;
  1609. end else
  1610. video_control_axi <= 0;
  1611. if (axi_reg2[30]==1'b1) begin
  1612. zorro_interrupt <= axi_reg2[0];
  1613. end
  1614. // read / write request acknowledged by ARM
  1615. zorro_ram_read_flag <= axi_reg0[30];
  1616. zorro_ram_write_flag <= axi_reg0[31];
  1617. axi_reg0 <= slv_reg0;
  1618. axi_reg1 <= slv_reg1;
  1619. axi_reg2 <= slv_reg2;
  1620. axi_reg3 <= slv_reg3;
  1621. if (video_control_axi) begin
  1622. video_control_data <= video_control_data_axi;
  1623. video_control_op <= video_control_op_axi;
  1624. end else begin
  1625. video_control_data <= video_control_data_zorro;
  1626. video_control_op <= video_control_op_zorro;
  1627. end
  1628. // snoop the screen width for correct capture pitch
  1629. if (video_control_op_axi == 2) begin
  1630. // OP_DIMENSIONS = 2
  1631. videocap_pitch <= video_control_data_axi[11:0];
  1632. end
  1633. videocap_ymax_sync <= videocap_ymax;
  1634. out_reg0 <= ZORRO3 ? last_z3addr : last_addr;
  1635. out_reg1 <= zorro_ram_write_data;
  1636. out_reg2 <= last_z3addr;
  1637. out_reg3 <= {zorro_ram_write_request, zorro_ram_read_request, zorro_ram_write_bytes, ZORRO3,
  1638. video_control_interlace, videocap_mode, 15'b0, zorro_state};
  1639. // `-- 24 `-- 23 `-- 22 `-- 7:0
  1640. /*out_reg3 <= {zorro_ram_write_request, zorro_ram_read_request, zorro_ram_write_bytes, ZORRO3,
  1641. video_control_interlace, videocap_mode, 5'b0, videocap_ymax_sync, zorro_state};*/
  1642. end
  1643. assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
  1644. always @(*)
  1645. begin
  1646. // Address decoding for reading registers
  1647. case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
  1648. 2'h0 : reg_data_out <= out_reg0;
  1649. 2'h1 : reg_data_out <= out_reg1;
  1650. 2'h2 : reg_data_out <= out_reg2;
  1651. 2'h3 : reg_data_out <= out_reg3;
  1652. default : reg_data_out <= 'h0;
  1653. endcase
  1654. end
  1655. endmodule