Firmware for MNT ZZ9000 graphics and ARM coprocessor card for Amiga computers.
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  1. `timescale 1 ns / 1 ps
  2. /*
  3. * MNT ZZ9000 Amiga Graphics and Coprocessor Card Firmware
  4. * Zorro 2/3 AXI4-Lite Interface, 24-bit Video Capture (AXI DMA)
  5. *
  6. * Copyright (C) 2019-2020, Lukas F. Hartmann <lukas@mntre.com>
  7. * MNT Research GmbH, Berlin
  8. * https://mntre.com
  9. *
  10. * Contributors: _Bnu, shanshe
  11. *
  12. * More Info: https://mntre.com/zz9000
  13. *
  14. * SPDX-License-Identifier: GPL-3.0-or-later
  15. * GNU General Public License v3.0 or later
  16. *
  17. * https://spdx.org/licenses/GPL-3.0-or-later.html
  18. *
  19. */
  20. // ZORRO2/3 switch
  21. //`define ZORRO2
  22. `define ZORRO3
  23. // use together with ZORRO2:
  24. //`define VARIANT_ZZ9500 // uses Denise adapter/A500 specific video capture
  25. //`define VARIANT_2MB // uses only 2MB address space
  26. //`define VARIANT_SUPERDENISE // for A500+ and super denise
  27. //`define VARIANT_FW20
  28. `define C_S_AXI_DATA_WIDTH 32
  29. `define C_S_AXI_ADDR_WIDTH 5
  30. `ifdef VARIANT_2MB
  31. `define RAM_SIZE 32'h200000 // 2MB for Zorro 2
  32. `else
  33. `define RAM_SIZE 32'h400000 // 4MB for Zorro 2
  34. `endif
  35. `define REG_SIZE 32'h01000
  36. `define AUTOCONF_LOW 24'he80000
  37. `define AUTOCONF_HIGH 24'he80080
  38. `define Z3_RAM_SIZE 32'h10000000 // 256MB for Zorro 3
  39. `define ARM_MEMORY_START 32'h001f0000
  40. `define VIDEOCAP_ADDR 32'h01000000 // ARM_MEMORY_START+0xe0_0000
  41. `define TX_FRAME_ADDRESS 32'h0fd10000
  42. `define RX_FRAME_ADDRESS 32'h0fd20000
  43. `define RX_BACKLOG_ADDRESS 32'h0fe00000
  44. `define FRAME_SIZE 24'h2048
  45. `define USB_BLOCK_STORAGE_ADDRESS 32'h0fe10000
  46. `define C_M00_AXI_TARGET_SLAVE_BASE_ADDR 32'h10000000
  47. `define C_M00_AXI_ID_WIDTH 1
  48. `define C_M00_AXI_ADDR_WIDTH 32
  49. `define C_M00_AXI_DATA_WIDTH 32
  50. `define C_M00_AXI_AWUSER_WIDTH 0
  51. `define C_M00_AXI_ARUSER_WIDTH 0
  52. `define C_M00_AXI_WUSER_WIDTH 0
  53. `define C_M00_AXI_RUSER_WIDTH 0
  54. `define C_M00_AXI_BUSER_WIDTH 0
  55. module MNTZorro_v0_1_S00_AXI
  56. (
  57. output wire arm_interrupt,
  58. inout wire [22:0] ZORRO_ADDR,
  59. inout wire [15:0] ZORRO_DATA,
  60. output wire ZORRO_INT6,
  61. output wire ZORRO_DATADIR,
  62. output wire ZORRO_ADDRDIR,
  63. output wire ZORRO_ADDRDIR2,
  64. output wire ZORRO_NBRN,
  65. input wire ZORRO_NBGN,
  66. input wire ZORRO_READ,
  67. //input wire ZORRO_NMTCR,
  68. input wire ZORRO_NUDS,
  69. input wire ZORRO_NLDS,
  70. input wire ZORRO_NDS1,
  71. input wire ZORRO_NDS0,
  72. input wire ZORRO_NCCS,
  73. input wire ZORRO_NFCS,
  74. input wire ZORRO_DOE,
  75. input wire ZORRO_NIORST,
  76. input wire ZORRO_NCFGIN,
  77. input wire ZORRO_E7M,
  78. input wire ZORRO_C28D,
  79. input wire VCAP_VSYNC,
  80. input wire VCAP_HSYNC,
  81. input wire VCAP_G0,
  82. input wire VCAP_G1,
  83. input wire VCAP_G2,
  84. input wire VCAP_G3,
  85. input wire VCAP_G4,
  86. input wire VCAP_G5,
  87. input wire VCAP_G6,
  88. input wire VCAP_G7,
  89. input wire VCAP_B7,
  90. input wire VCAP_B6,
  91. input wire VCAP_B5,
  92. input wire VCAP_B4,
  93. input wire VCAP_B3,
  94. input wire VCAP_B2,
  95. input wire VCAP_B1,
  96. input wire VCAP_B0,
  97. input wire VCAP_R7,
  98. input wire VCAP_R6,
  99. input wire VCAP_R5,
  100. input wire VCAP_R4,
  101. input wire VCAP_R3,
  102. input wire VCAP_R2,
  103. input wire VCAP_R1,
  104. input wire VCAP_R0,
  105. output wire ZORRO_NCFGOUT,
  106. output wire ZORRO_NSLAVE,
  107. output wire ZORRO_NCINH,
  108. output wire ZORRO_NDTACK,
  109. // HP master interface to write to PS memory directly
  110. input wire m00_axi_aclk,
  111. input wire m00_axi_aresetn,
  112. // write address channel
  113. input wire m00_axi_awready,
  114. output wire [`C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr,
  115. output reg [3:0] m00_axi_awlen,
  116. output reg [2:0] m00_axi_awsize,
  117. output reg [1:0] m00_axi_awburst,
  118. output reg m00_axi_awlock,
  119. output reg [3:0] m00_axi_awcache,
  120. output reg [2:0] m00_axi_awprot,
  121. //output reg [3:0] m00_axi_awqos,
  122. output wire m00_axi_awvalid,
  123. // write channel
  124. input wire m00_axi_wready,
  125. output wire [`C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata,
  126. output wire [`C_M00_AXI_DATA_WIDTH/8-1 : 0] m00_axi_wstrb,
  127. output reg m00_axi_wlast,
  128. output wire m00_axi_wvalid,
  129. // buffered write response channel
  130. input wire [1 : 0] m00_axi_bresp,
  131. input wire m00_axi_bvalid,
  132. output reg m00_axi_bready,
  133. // read address channel
  134. input wire m00_axi_arready,
  135. output reg [`C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
  136. output reg [3 : 0] m00_axi_arlen,
  137. output reg [2 : 0] m00_axi_arsize,
  138. output reg [1 : 0] m00_axi_arburst,
  139. output reg m00_axi_arlock,
  140. output reg [3 : 0] m00_axi_arcache,
  141. output reg [2 : 0] m00_axi_arprot,
  142. //output reg [3 : 0] m00_axi_arqos,
  143. output reg m00_axi_arvalid,
  144. output reg m00_axi_rready,
  145. input wire [`C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
  146. input wire [1 : 0] m00_axi_rresp,
  147. input wire m00_axi_rlast,
  148. input wire m00_axi_rvalid,
  149. // HP master interface 2 to write to PS memory directly (for videocap)
  150. input wire m01_axi_aclk,
  151. input wire m01_axi_aresetn,
  152. // write address channel
  153. input wire m01_axi_awready,
  154. output wire [`C_M00_AXI_ADDR_WIDTH-1 : 0] m01_axi_awaddr,
  155. output reg [7:0] m01_axi_awlen,
  156. output reg [2:0] m01_axi_awsize,
  157. output reg [1:0] m01_axi_awburst,
  158. output reg m01_axi_awlock,
  159. output reg [3:0] m01_axi_awcache,
  160. output reg [2:0] m01_axi_awprot,
  161. output reg [3:0] m01_axi_awqos,
  162. output wire m01_axi_awvalid,
  163. // write channel
  164. input wire m01_axi_wready,
  165. output wire [`C_M00_AXI_DATA_WIDTH-1 : 0] m01_axi_wdata,
  166. output wire [`C_M00_AXI_DATA_WIDTH/8-1 : 0] m01_axi_wstrb,
  167. output reg m01_axi_wlast,
  168. output wire m01_axi_wvalid,
  169. // buffered write response channel
  170. input wire [1 : 0] m01_axi_bresp,
  171. input wire m01_axi_bvalid,
  172. output reg m01_axi_bready,
  173. // video_formatter control interface
  174. output reg [31:0] video_control_data_out,
  175. output reg [7:0] video_control_op_out,
  176. output reg video_control_interlace_out,
  177. input wire video_control_vblank_in,
  178. // Xilinx AXI4-Lite implementation starts here ==============================
  179. // Global Clock Signal
  180. input wire S_AXI_ACLK,
  181. // Global Reset Signal. This Signal is Active LOW
  182. input wire S_AXI_ARESETN,
  183. // Write address (issued by master, acceped by Slave)
  184. input wire [`C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
  185. // Write channel Protection type. This signal indicates the
  186. // privilege and security level of the transaction, and whether
  187. // the transaction is a data access or an instruction access.
  188. input wire [2 : 0] S_AXI_AWPROT,
  189. // Write address valid. This signal indicates that the master signaling
  190. // valid write address and control information.
  191. input wire S_AXI_AWVALID,
  192. // Write address ready. This signal indicates that the slave is ready
  193. // to accept an address and associated control signals.
  194. output wire S_AXI_AWREADY,
  195. // Write data (issued by master, acceped by Slave)
  196. input wire [`C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
  197. // Write strobes. This signal indicates which byte lanes hold
  198. // valid data. There is one write strobe bit for each eight
  199. // bits of the write data bus.
  200. input wire [(`C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
  201. // Write valid. This signal indicates that valid write
  202. // data and strobes are available.
  203. input wire S_AXI_WVALID,
  204. // Write ready. This signal indicates that the slave
  205. // can accept the write data.
  206. output wire S_AXI_WREADY,
  207. // Write response. This signal indicates the status
  208. // of the write transaction.
  209. output wire [1 : 0] S_AXI_BRESP,
  210. // Write response valid. This signal indicates that the channel
  211. // is signaling a valid write response.
  212. output wire S_AXI_BVALID,
  213. // Response ready. This signal indicates that the master
  214. // can accept a write response.
  215. input wire S_AXI_BREADY,
  216. // Read address (issued by master, acceped by Slave)
  217. input wire [`C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
  218. // Protection type. This signal indicates the privilege
  219. // and security level of the transaction, and whether the
  220. // transaction is a data access or an instruction access.
  221. input wire [2 : 0] S_AXI_ARPROT,
  222. // Read address valid. This signal indicates that the channel
  223. // is signaling valid read address and control information.
  224. input wire S_AXI_ARVALID,
  225. // Read address ready. This signal indicates that the slave is
  226. // ready to accept an address and associated control signals.
  227. output wire S_AXI_ARREADY,
  228. // Read data (issued by slave)
  229. output wire [`C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
  230. // Read response. This signal indicates the status of the
  231. // read transfer.
  232. output wire [1 : 0] S_AXI_RRESP,
  233. // Read valid. This signal indicates that the channel is
  234. // signaling the required read data.
  235. output wire S_AXI_RVALID,
  236. // Read ready. This signal indicates that the master can
  237. // accept the read data and response information.
  238. input wire S_AXI_RREADY
  239. );
  240. // AXI4LITE signals
  241. reg [`C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
  242. reg axi_awready;
  243. reg axi_wready;
  244. reg [1 : 0] axi_bresp;
  245. reg axi_bvalid;
  246. reg [`C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
  247. reg axi_arready;
  248. reg [`C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
  249. reg [1 : 0] axi_rresp;
  250. reg axi_rvalid;
  251. // Example-specific design signals
  252. // local localparam for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
  253. // ADDR_LSB is used for addressing 32/64 bit registers/memories
  254. // ADDR_LSB = 2 for 32 bits (n downto 2)
  255. // ADDR_LSB = 3 for 64 bits (n downto 3)
  256. localparam integer ADDR_LSB = (`C_S_AXI_DATA_WIDTH/32) + 1;
  257. localparam integer OPT_MEM_ADDR_BITS = 2;
  258. //----------------------------------------------
  259. //-- Signals for user logic register space example
  260. //------------------------------------------------
  261. //-- Number of Slave Registers 4
  262. reg [`C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
  263. reg [`C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
  264. reg [`C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
  265. reg [`C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
  266. reg [`C_S_AXI_DATA_WIDTH-1:0] slv_reg4;
  267. reg [`C_S_AXI_DATA_WIDTH-1:0] slv_reg5;
  268. wire slv_reg_rden;
  269. wire slv_reg_wren;
  270. reg [`C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
  271. integer byte_index;
  272. reg aw_en;
  273. reg [`C_S_AXI_DATA_WIDTH-1:0] out_reg0;
  274. reg [`C_S_AXI_DATA_WIDTH-1:0] out_reg1;
  275. reg [`C_S_AXI_DATA_WIDTH-1:0] out_reg2;
  276. reg [`C_S_AXI_DATA_WIDTH-1:0] out_reg3;
  277. // I/O Connections assignments
  278. assign S_AXI_AWREADY = axi_awready;
  279. assign S_AXI_WREADY = axi_wready;
  280. assign S_AXI_BRESP = axi_bresp;
  281. assign S_AXI_BVALID = axi_bvalid;
  282. assign S_AXI_ARREADY = axi_arready;
  283. assign S_AXI_RDATA = axi_rdata;
  284. assign S_AXI_RRESP = axi_rresp;
  285. assign S_AXI_RVALID = axi_rvalid;
  286. // Implement axi_awready generation
  287. // axi_awready is asserted for one S_AXI_ACLK clock cycle when both
  288. // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
  289. // de-asserted when reset is low.
  290. always @( posedge S_AXI_ACLK )
  291. begin
  292. if ( S_AXI_ARESETN == 1'b0 )
  293. begin
  294. axi_awready <= 1'b0;
  295. aw_en <= 1'b1;
  296. end
  297. else
  298. begin
  299. if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
  300. begin
  301. // slave is ready to accept write address when
  302. // there is a valid write address and write data
  303. // on the write address and data bus. This design
  304. // expects no outstanding transactions.
  305. axi_awready <= 1'b1;
  306. aw_en <= 1'b0;
  307. end
  308. else if (S_AXI_BREADY && axi_bvalid)
  309. begin
  310. aw_en <= 1'b1;
  311. axi_awready <= 1'b0;
  312. end
  313. else
  314. begin
  315. axi_awready <= 1'b0;
  316. end
  317. end
  318. end
  319. // Implement axi_awaddr latching
  320. // This process is used to latch the address when both
  321. // S_AXI_AWVALID and S_AXI_WVALID are valid.
  322. always @( posedge S_AXI_ACLK )
  323. begin
  324. if ( S_AXI_ARESETN == 1'b0 )
  325. begin
  326. axi_awaddr <= 0;
  327. end
  328. else
  329. begin
  330. if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
  331. begin
  332. // Write Address latching
  333. axi_awaddr <= S_AXI_AWADDR;
  334. end
  335. end
  336. end
  337. // Implement axi_wready generation
  338. // axi_wready is asserted for one S_AXI_ACLK clock cycle when both
  339. // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
  340. // de-asserted when reset is low.
  341. always @( posedge S_AXI_ACLK )
  342. begin
  343. if ( S_AXI_ARESETN == 1'b0 )
  344. begin
  345. axi_wready <= 1'b0;
  346. end
  347. else
  348. begin
  349. if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
  350. begin
  351. // slave is ready to accept write data when
  352. // there is a valid write address and write data
  353. // on the write address and data bus. This design
  354. // expects no outstanding transactions.
  355. axi_wready <= 1'b1;
  356. end
  357. else
  358. begin
  359. axi_wready <= 1'b0;
  360. end
  361. end
  362. end
  363. // Implement memory mapped register select and write logic generation
  364. // The write data is accepted and written to memory mapped registers when
  365. // axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
  366. // select byte enables of slave registers while writing.
  367. // These registers are cleared when reset (active low) is applied.
  368. // Slave register write enable is asserted when valid address and data are available
  369. // and the slave is ready to accept the write address and write data.
  370. assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
  371. always @( posedge S_AXI_ACLK )
  372. begin
  373. if ( S_AXI_ARESETN == 1'b0 )
  374. begin
  375. slv_reg0 <= 0;
  376. slv_reg1 <= 0;
  377. slv_reg2 <= 0;
  378. slv_reg3 <= 0;
  379. slv_reg4 <= 0;
  380. slv_reg5 <= 0;
  381. end
  382. else begin
  383. if (slv_reg_wren)
  384. begin
  385. case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
  386. 3'h0:
  387. for ( byte_index = 0; byte_index <= (`C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
  388. if ( S_AXI_WSTRB[byte_index] == 1 ) begin
  389. // Respective byte enables are asserted as per write strobes
  390. // Slave register 0
  391. slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
  392. end
  393. 3'h1:
  394. for ( byte_index = 0; byte_index <= (`C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
  395. if ( S_AXI_WSTRB[byte_index] == 1 ) begin
  396. // Respective byte enables are asserted as per write strobes
  397. // Slave register 1
  398. slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
  399. end
  400. 3'h2:
  401. for ( byte_index = 0; byte_index <= (`C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
  402. if ( S_AXI_WSTRB[byte_index] == 1 ) begin
  403. // Respective byte enables are asserted as per write strobes
  404. // Slave register 2
  405. slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
  406. end
  407. 3'h3:
  408. for ( byte_index = 0; byte_index <= (`C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
  409. if ( S_AXI_WSTRB[byte_index] == 1 ) begin
  410. // Respective byte enables are asserted as per write strobes
  411. // Slave register 3
  412. slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
  413. end
  414. 3'h4:
  415. for ( byte_index = 0; byte_index <= (`C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
  416. if ( S_AXI_WSTRB[byte_index] == 1 ) begin
  417. // Respective byte enables are asserted as per write strobes
  418. // Slave register 4
  419. slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
  420. end
  421. 3'h5:
  422. for ( byte_index = 0; byte_index <= (`C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
  423. if ( S_AXI_WSTRB[byte_index] == 1 ) begin
  424. // Respective byte enables are asserted as per write strobes
  425. // Slave register 4
  426. slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
  427. end
  428. default : begin
  429. slv_reg0 <= slv_reg0;
  430. slv_reg1 <= slv_reg1;
  431. slv_reg2 <= slv_reg2;
  432. slv_reg3 <= slv_reg3;
  433. slv_reg4 <= slv_reg4;
  434. slv_reg5 <= slv_reg5;
  435. end
  436. endcase
  437. end
  438. end
  439. end
  440. // Implement write response logic generation
  441. // The write response and response valid signals are asserted by the slave
  442. // when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
  443. // This marks the acceptance of address and indicates the status of
  444. // write transaction.
  445. always @( posedge S_AXI_ACLK )
  446. begin
  447. if ( S_AXI_ARESETN == 1'b0 )
  448. begin
  449. axi_bvalid <= 0;
  450. axi_bresp <= 2'b0;
  451. end
  452. else
  453. begin
  454. if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
  455. begin
  456. // indicates a valid write response is available
  457. axi_bvalid <= 1'b1;
  458. axi_bresp <= 2'b0; // 'OKAY' response
  459. end // work error responses in future
  460. else
  461. begin
  462. if (S_AXI_BREADY && axi_bvalid)
  463. //check if bready is asserted while bvalid is high)
  464. //(there is a possibility that bready is always asserted high)
  465. begin
  466. axi_bvalid <= 1'b0;
  467. end
  468. end
  469. end
  470. end
  471. // Implement axi_arready generation
  472. // axi_arready is asserted for one S_AXI_ACLK clock cycle when
  473. // S_AXI_ARVALID is asserted. axi_awready is
  474. // de-asserted when reset (active low) is asserted.
  475. // The read address is also latched when S_AXI_ARVALID is
  476. // asserted. axi_araddr is reset to zero on reset assertion.
  477. always @( posedge S_AXI_ACLK )
  478. begin
  479. if ( S_AXI_ARESETN == 1'b0 )
  480. begin
  481. axi_arready <= 1'b0;
  482. axi_araddr <= 32'b0;
  483. end
  484. else
  485. begin
  486. if (~axi_arready && S_AXI_ARVALID)
  487. begin
  488. // indicates that the slave has acceped the valid read address
  489. axi_arready <= 1'b1;
  490. // Read address latching
  491. axi_araddr <= S_AXI_ARADDR;
  492. end
  493. else
  494. begin
  495. axi_arready <= 1'b0;
  496. end
  497. end
  498. end
  499. // Implement axi_arvalid generation
  500. // axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
  501. // S_AXI_ARVALID and axi_arready are asserted. The slave registers
  502. // data are available on the axi_rdata bus at this instance. The
  503. // assertion of axi_rvalid marks the validity of read data on the
  504. // bus and axi_rresp indicates the status of read transaction.axi_rvalid
  505. // is deasserted on reset (active low). axi_rresp and axi_rdata are
  506. // cleared to zero on reset (active low).
  507. always @( posedge S_AXI_ACLK )
  508. begin
  509. if ( S_AXI_ARESETN == 1'b0 )
  510. begin
  511. axi_rvalid <= 0;
  512. axi_rresp <= 0;
  513. end
  514. else
  515. begin
  516. if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
  517. begin
  518. // Valid read data is available at the read data bus
  519. axi_rvalid <= 1'b1;
  520. axi_rresp <= 2'b0; // 'OKAY' response
  521. end
  522. else if (axi_rvalid && S_AXI_RREADY)
  523. begin
  524. // Read data is accepted by the master
  525. axi_rvalid <= 1'b0;
  526. end
  527. end
  528. end
  529. // Output register or memory read data
  530. always @( posedge S_AXI_ACLK )
  531. begin
  532. if ( S_AXI_ARESETN == 1'b0 )
  533. begin
  534. axi_rdata <= 0;
  535. end
  536. else
  537. begin
  538. // When there is a valid read address (S_AXI_ARVALID) with
  539. // acceptance of read address by the slave (axi_arready),
  540. // output the read dada
  541. if (slv_reg_rden)
  542. begin
  543. axi_rdata <= reg_data_out; // register read data
  544. end
  545. end
  546. end
  547. // end of AXI-Lite interface ==================================================
  548. (* mark_debug = "true" *) reg [4:0] znAS_sync;
  549. (* mark_debug = "true" *) reg [2:0] znUDS_sync;
  550. (* mark_debug = "true" *) reg [2:0] znLDS_sync;
  551. (* mark_debug = "true" *) reg [2:0] zREAD_sync;
  552. (* mark_debug = "true" *) reg [4:0] znFCS_sync;
  553. (* mark_debug = "true" *) reg [2:0] znDS1_sync;
  554. (* mark_debug = "true" *) reg [2:0] znDS0_sync;
  555. reg [1:0] znRST_sync;
  556. (* mark_debug = "true" *) reg [1:0] zDOE_sync;
  557. (* mark_debug = "true" *) reg [4:0] zE7M_sync;
  558. reg [2:0] znCFGIN_sync;
  559. (* mark_debug = "true" *) reg [23:0] zaddr; // zorro 2 address
  560. (* mark_debug = "true" *) reg [23:0] zaddr_sync;
  561. (* mark_debug = "true" *) reg [23:0] zaddr_sync2;
  562. (* mark_debug = "true" *) reg [15:0] zdata_in_sync;
  563. (* mark_debug = "true" *) reg [15:0] zdata_in_sync2;
  564. reg z2_addr_valid;
  565. reg [23:0] z2_mapped_addr;
  566. reg z2_read;
  567. reg z2_write;
  568. reg z2_datastrobe_synced;
  569. reg z2addr_in_ram;
  570. reg z2addr_in_reg;
  571. reg z2addr_autoconfig;
  572. reg [31:0] ram_low ;//= 32'h600000;
  573. reg [31:0] ram_high ;//= 32'ha00000;
  574. reg [31:0] reg_low ;//= 32'h601000;
  575. reg [31:0] reg_high ;//= 32'h602000;
  576. reg z2_uds;
  577. reg z2_lds;
  578. reg [31:0] z3_ram_low ;//= 32'h50000000;
  579. reg [31:0] z3_ram_high ;//= 32'h50000000 + `Z3_RAM_SIZE -4;
  580. reg [31:0] z3_reg_low ;//= 32'h50001000;
  581. reg [31:0] z3_reg_high ;//= 32'h50002000;
  582. reg [15:0] data_z3_hi16;
  583. reg [15:0] data_z3_low16;
  584. (* mark_debug = "true" *) reg [15:0] data_z3_hi16_latched;
  585. (* mark_debug = "true" *) reg [15:0] data_z3_low16_latched;
  586. (* mark_debug = "true" *) reg [15:0] z3_din_high_s2;
  587. (* mark_debug = "true" *) reg [15:0] z3_din_low_s2;
  588. (* mark_debug = "true" *) reg [31:0] z3addr;
  589. (* mark_debug = "true" *) reg [31:0] last_z3addr;
  590. (* mark_debug = "true" *) reg [31:0] z3addr2;
  591. (* mark_debug = "true" *) reg [31:0] z3_mapped_addr;
  592. (* mark_debug = "true" *) reg [31:0] z3_read_addr;
  593. (* mark_debug = "true" *) reg [15:0] z3_read_data;
  594. reg z3_din_latch;
  595. (* mark_debug = "true" *) reg z3_fcs_state;
  596. (* mark_debug = "true" *) reg z3_end_cycle;
  597. (* mark_debug = "true" *) reg z3addr_in_ram;
  598. (* mark_debug = "true" *) reg z3addr_in_reg;
  599. (* mark_debug = "true" *) reg z3addr_autoconfig;
  600. `ifdef ZORRO3
  601. reg ZORRO3 = 1;
  602. `else
  603. reg ZORRO3 = 0;
  604. `endif
  605. (* mark_debug = "true" *) reg dataout;
  606. (* mark_debug = "true" *) reg dataout_z3;
  607. (* mark_debug = "true" *) reg dataout_enable;
  608. (* mark_debug = "true" *) reg slaven;
  609. (* mark_debug = "true" *) reg dtack;
  610. reg z_reset;
  611. reg z_reset_delayed;
  612. reg z_cfgin;
  613. reg z_cfgin_lo;
  614. reg z3_confdone;
  615. reg zorro_read;
  616. reg zorro_write;
  617. reg zorro_interrupt;
  618. reg clear_interrupt;
  619. assign ZORRO_INT6 = zorro_interrupt;
  620. reg [15:0] data_in;
  621. reg [31:0] rr_data;
  622. reg [15:0] data_out;
  623. reg [15:0] regdata_in;
  624. // ram arbiter
  625. (* mark_debug = "true" *) reg zorro_ram_read_request;
  626. (* mark_debug = "true" *) reg zorro_ram_write_request;
  627. reg [31:0] zorro_ram_read_addr;
  628. reg [3:0] zorro_ram_read_bytes;
  629. reg [31:0] zorro_ram_write_addr;
  630. reg [31:0] zorro_ram_write_data;
  631. reg [3:0] zorro_ram_write_bytes;
  632. reg [15:0] default_data = 'hffff; // causes read/write glitches on A2000 (data bus interference) when 0
  633. reg [1:0] zorro_write_capture_bytes;
  634. reg [15:0] zorro_write_capture_data;
  635. // z3 strobes
  636. reg z3_ds3;
  637. reg z3_ds2;
  638. reg z3_ds1;
  639. reg z3_ds0;
  640. // level shifter direction pins
  641. assign ZORRO_DATADIR = ZORRO_DOE & (dataout_enable | dataout_z3); // d2-d9 d10-15, d0-d1
  642. assign ZORRO_ADDRDIR = ZORRO_DOE & (dataout_z3); // a16-a23 <- input a8-a15 <- input
  643. assign ZORRO_ADDRDIR2 = 0; //ZORRO_DOE & (dataout_z3_latched);
  644. assign ZORRO_NBRN = 1; // TODO busmastering
  645. // data/addr out signals are gated by master's DOE signal
  646. wire ZORRO_DATA_T = ~(ZORRO_DOE & (dataout_enable | dataout_z3));
  647. wire ZORRO_ADDR_T = ~(ZORRO_DOE & dataout_z3);
  648. reg z_ovr = 0;
  649. assign ZORRO_NCINH = z_ovr?1'b1:1'b0; // inverse
  650. // "slave" signals are gated by master's FCS signal
  651. assign ZORRO_NSLAVE = (ZORRO_DOE & slaven)?1'b0:1'b1; // cannot gate by FCS for Z2
  652. assign ZORRO_NDTACK = (ZORRO_DOE & dtack) ?1'b1:1'b0; // inverse, pull-down transistor on output
  653. wire [22:0] z3_addr_out = {data_z3_low16_latched, 7'bZZZ_ZZZZ}; // FIXME this creates tri-cell warning?
  654. //wire [22:0] z3_addr_out = {data_z3_low16_latched, 7'b111_1111}; // FIXME this creates tri-cell warning?
  655. wire [15:0] ZORRO_DATA_IN;
  656. wire [22:0] ZORRO_ADDR_IN;
  657. genvar i;
  658. generate
  659. for (i=0; i < 16; i=i+1) begin : ZORRO_DATABUS
  660. IOBUF u_iobuf_dq
  661. (
  662. .I (ZORRO3 ? data_z3_hi16_latched[i] : data_out[i]),
  663. .T (ZORRO_DATA_T),
  664. .IO (ZORRO_DATA[i]),
  665. .O (ZORRO_DATA_IN[i])
  666. );
  667. end
  668. endgenerate
  669. generate
  670. for (i=0; i < 23; i=i+1) begin : ZORRO_ADDRBUS
  671. IOBUF u_iobuf_dq
  672. (
  673. .I (z3_addr_out[i]),
  674. .T (ZORRO_ADDR_T),
  675. .IO (ZORRO_ADDR[i]),
  676. .O (ZORRO_ADDR_IN[i])
  677. );
  678. end
  679. endgenerate
  680. // autoconf output signal
  681. reg z_confout = 0;
  682. assign ZORRO_NCFGOUT = ZORRO_NCFGIN?1'b1:(~z_confout);
  683. reg [7:0] video_debug_reg;
  684. assign arm_interrupt = zorro_ram_write_request | zorro_ram_read_request;
  685. // -- synchronizers ------------------------------------------
  686. always @(posedge S_AXI_ACLK) begin
  687. znUDS_sync <= {znUDS_sync[1:0],ZORRO_NUDS};
  688. znLDS_sync <= {znLDS_sync[1:0],ZORRO_NLDS};
  689. znAS_sync <= {znAS_sync[3:0],ZORRO_NCCS};
  690. zREAD_sync <= {zREAD_sync[1:0],ZORRO_READ};
  691. znDS1_sync <= {znDS1_sync[1:0],ZORRO_NDS1};
  692. znDS0_sync <= {znDS0_sync[1:0],ZORRO_NDS0};
  693. znFCS_sync <= {znFCS_sync[3:0],ZORRO_NFCS};
  694. znCFGIN_sync<= {znCFGIN_sync[1:0],ZORRO_NCFGIN};
  695. zDOE_sync <= {zDOE_sync[0],ZORRO_DOE};
  696. znRST_sync <= {znRST_sync[0],ZORRO_NIORST};
  697. // Z2 ------------------------------------------------
  698. `ifdef ZORRO2
  699. // READ and nAS can happen dangerously close to each other. so we delay
  700. // the recognition of a valid Z2 cycle 2 clocks more than the other signals.
  701. z2_addr_valid <= (znAS_sync[4]==0 && znAS_sync[3]==0);
  702. z2_read <= (zREAD_sync[2] == 1'b1);
  703. z2_write <= (zREAD_sync[2] == 1'b0);
  704. zaddr <= ZORRO_ADDR_IN[22:0];
  705. zaddr_sync <= zaddr;
  706. zaddr_sync2 <= zaddr_sync;
  707. z2_mapped_addr <= {zaddr_sync2[22:0],1'b0};
  708. z2_datastrobe_synced <= ((znUDS_sync[2]==0 && znUDS_sync[1]==0) || (znLDS_sync[2]==0 && znLDS_sync[1]==0));
  709. z2_uds <= (znUDS_sync[2]==0 && znUDS_sync[1]==0);
  710. z2_lds <= (znLDS_sync[2]==0 && znLDS_sync[1]==0);
  711. zdata_in_sync2 <= ZORRO_DATA_IN;
  712. zdata_in_sync <= zdata_in_sync2;
  713. z2addr_in_ram <= (z2_mapped_addr>=ram_low && z2_mapped_addr<ram_high);
  714. z2addr_in_reg <= (z2_mapped_addr>=reg_low && z2_mapped_addr<reg_high);
  715. // FIXME was 1
  716. if (znAS_sync[4]==0 && z2_mapped_addr>=`AUTOCONF_LOW && z2_mapped_addr<`AUTOCONF_HIGH)
  717. z2addr_autoconfig <= 1'b1;
  718. else
  719. z2addr_autoconfig <= 1'b0;
  720. `endif
  721. // Z3 ------------------------------------------------
  722. `ifdef ZORRO3
  723. // sample z3addr on falling edge of /FCS
  724. // according to Z3 spec, we have max 25ns to react to falling FCS.
  725. case (znFCS_sync[1:0])
  726. 2'b01: begin
  727. z3_fcs_state <= 1;
  728. z3addr <= 0;
  729. end
  730. 2'b10: begin
  731. z3_fcs_state <= 0;
  732. z3addr <= z3addr2;
  733. end
  734. endcase
  735. z3addr2 <= {ZORRO_DATA_IN[15:8],ZORRO_ADDR_IN[22:1],2'b00};
  736. z3addr_in_ram <= (z3addr >= z3_ram_low) && (z3addr < z3_ram_high);
  737. z3addr_in_reg <= (z3addr >= z3_reg_low) && (z3addr < z3_reg_high);
  738. z3_ds0 <= ~znDS0_sync[1];
  739. z3_ds1 <= ~znDS1_sync[1];
  740. z3_ds2 <= ~znLDS_sync[1];
  741. z3_ds3 <= ~znUDS_sync[1];
  742. z3addr_autoconfig <= (z3addr[31:16]=='hff00);
  743. z3_mapped_addr <= (z3addr-z3_ram_low);
  744. z3_din_high_s2 <= ZORRO_DATA_IN; //zD[15:0];
  745. z3_din_low_s2 <= ZORRO_ADDR_IN[22:7]; //zA[22:7];
  746. // pipelined for better timing
  747. data_z3_hi16_latched <= data_z3_hi16;
  748. data_z3_low16_latched <= data_z3_low16;
  749. zorro_read <= zREAD_sync[0];
  750. zorro_write <= ~zREAD_sync[0];
  751. `endif
  752. z_reset_delayed <= (znRST_sync==2'b00);
  753. z_reset <= z_reset_delayed;
  754. z_cfgin <= (znCFGIN_sync==3'b000);
  755. z_cfgin_lo <= (znCFGIN_sync==3'b111);
  756. //video_debug_reg <= video_debug;
  757. end // always @ (posedge S_AXI_ACLK)
  758. reg [15:0] REVISION = 'h7a09; // z9
  759. // main FSM
  760. localparam RESET = 0;
  761. localparam Z2_CONFIGURING = 1;
  762. localparam Z2_IDLE = 2;
  763. localparam WAIT_WRITE = 3;
  764. localparam WAIT_WRITE2 = 4;
  765. localparam Z2_WRITE_FINALIZE = 5;
  766. localparam WAIT_READ = 6;
  767. localparam WAIT_READ2 = 7;
  768. localparam WAIT_READ3 = 8;
  769. localparam CONFIGURED = 9;
  770. localparam CONFIGURED_CLEAR = 10;
  771. localparam DECIDE_Z2_Z3 = 11;
  772. localparam Z3_IDLE = 12;
  773. localparam Z3_WRITE_UPPER = 13;
  774. localparam Z3_WRITE_LOWER = 14;
  775. localparam Z3_READ_UPPER = 15;
  776. localparam Z3_READ_LOWER = 16;
  777. localparam Z3_READ_DELAY = 17;
  778. localparam Z3_READ_DELAY1 = 18;
  779. localparam Z3_READ_DELAY2 = 19;
  780. localparam Z3_WRITE_PRE = 20;
  781. localparam Z3_WRITE_FINALIZE = 21;
  782. localparam Z3_ENDCYCLE = 22;
  783. localparam Z3_DTACK = 23;
  784. localparam Z3_CONFIGURING = 24;
  785. localparam Z2_REGWRITE = 25;
  786. localparam REGWRITE = 26;
  787. localparam REGREAD = 27;
  788. localparam Z2_REGREAD_POST = 28;
  789. localparam Z3_REGREAD_POST = 29;
  790. localparam Z3_REGWRITE = 30;
  791. localparam Z2_REGREAD = 31;
  792. localparam Z3_REGREAD = 32;
  793. localparam Z2_PRE_CONFIGURED = 34;
  794. localparam Z2_ENDCYCLE = 35;
  795. localparam WAIT_WRITE_DMA_Z2 = 36;
  796. localparam WAIT_WRITE_DMA_Z2_FINALIZE = 37;
  797. localparam RESET_DVID = 39;
  798. localparam COLD = 40;
  799. localparam WAIT_READ2B = 41; // delay states
  800. localparam WAIT_READ2C = 42;
  801. localparam WAIT_READ2D = 54;
  802. localparam WAIT_WRITE_DMA_Z3 = 43;
  803. localparam WAIT_WRITE_DMA_Z3_FINALIZE = 44;
  804. localparam Z3_AUTOCONF_READ = 45;
  805. localparam Z3_AUTOCONF_WRITE = 46;
  806. localparam Z3_AUTOCONF_READ_DLY = 47;
  807. localparam Z3_AUTOCONF_READ_DLY2 = 48;
  808. localparam Z3_REGWRITE_PRE = 49;
  809. localparam Z3_REGREAD_PRE = 50;
  810. localparam Z3_WRITE_PRE2 = 51;
  811. localparam WAIT_WRITE_DMA_Z3B = 52;
  812. localparam WAIT_WRITE_DMA_Z3C = 53;
  813. localparam WAIT_READ_DMA_Z3 = 54;
  814. localparam WAIT_READ_DMA_Z3B = 55;
  815. localparam WAIT_READ_DMA_Z3C = 56;
  816. (* mark_debug = "true" *) reg [7:0] zorro_state = COLD;
  817. reg zorro_idle;
  818. reg [7:0] read_counter; // used by Z3
  819. reg [5:0] dtack_timeout = 6; // number of cycles before we turn off our dtack signal
  820. reg [7:0] dataout_time = 'h02;
  821. reg [7:0] datain_time = 'h10;
  822. reg [7:0] datain_counter = 0;
  823. reg [23:0] last_addr;
  824. reg [23:0] last_read_addr;
  825. reg [15:0] last_data;
  826. reg [15:0] last_read_data;
  827. reg [15:0] zaddr_regpart;
  828. reg [15:0] z3addr_regpart;
  829. reg [15:0] regread_addr;
  830. reg [15:0] regwrite_addr;
  831. reg [31:0] axi_reg0;
  832. reg [31:0] axi_reg1;
  833. reg [31:0] axi_reg2;
  834. reg [31:0] axi_reg3;
  835. reg [31:0] axi_reg4;
  836. reg [31:0] axi_reg5;
  837. reg [31:0] frfb;
  838. reg [31:0] usbb;
  839. reg [31:0] video_control_data_zorro;
  840. reg [7:0] video_control_op_zorro;
  841. reg [31:0] video_control_data_axi;
  842. reg [7:0] video_control_op_axi;
  843. reg video_control_axi;
  844. reg [31:0] video_control_data; // to output
  845. reg [7:0] video_control_op; // to output
  846. reg video_control_vblank; // from input
  847. reg video_control_interlace;
  848. reg zorro_ram_read_flag;
  849. reg zorro_ram_write_flag ;
  850. reg videocap_mode;
  851. reg videocap_mode_in;
  852. (* mark_debug = "true" *) reg [6:0] videocap_hs;
  853. (* mark_debug = "true" *) reg [6:0] videocap_vs;
  854. reg [23:0] videocap_rgbin = 0;
  855. (* mark_debug = "true" *) reg [9:0] videocap_x;
  856. (* mark_debug = "true" *) reg [9:0] videocap_y;
  857. (* mark_debug = "true" *) reg [9:0] videocap_x2;
  858. (* mark_debug = "true" *) reg videocap_x_done;
  859. (* mark_debug = "true" *) reg [9:0] videocap_y2;
  860. (* mark_debug = "true" *) reg [9:0] videocap_y_sync;
  861. (* mark_debug = "true" *) reg [9:0] videocap_ymax;
  862. (* mark_debug = "true" *) reg [9:0] videocap_ymax2;
  863. (* mark_debug = "true" *) reg [9:0] videocap_ymax_sync;
  864. (* mark_debug = "true" *) reg [9:0] videocap_y3;
  865. reg vc_next_lace_field = 0;
  866. reg [3:0] vc_shortlines = 0;
  867. parameter VCAPW = 799;
  868. reg [31:0] videocap_buf [0:VCAPW];
  869. reg videocap_lace_field;
  870. (* mark_debug = "true" *) reg videocap_interlace;
  871. (* mark_debug = "true" *) reg videocap_ntsc;
  872. (* mark_debug = "true" *) reg [7:0] videocap_hs_pulse_width;
  873. reg E7M_PSEN = 0;
  874. reg E7M_PSINCDEC = 0;
  875. wire clkfbout_zz9000_ps_clk_wiz_1_0;
  876. wire e7m_shifted;
  877. wire e7m_shifted180;
  878. // video capture clock adjustment
  879. MMCME2_ADV #(
  880. .BANDWIDTH("OPTIMIZED"),
  881. .CLKFBOUT_MULT_F(32.000000),
  882. .CLKFBOUT_PHASE(0.000000),
  883. .CLKFBOUT_USE_FINE_PS("TRUE"),
  884. .CLKIN1_PERIOD(35.000000),
  885. .CLKIN2_PERIOD(0.000000),
  886. .CLKOUT0_DIVIDE_F(16.000000),
  887. .CLKOUT0_DUTY_CYCLE(0.500000),
  888. `ifdef ZORRO3
  889. .CLKOUT0_PHASE(0.000000),
  890. `elsif VARIANT_SUPERDENISE
  891. .CLKOUT0_PHASE(0.000000),
  892. `elsif VARIANT_ZZ9500
  893. .CLKOUT0_PHASE(90.000000),
  894. `else
  895. .CLKOUT0_PHASE(315.000000),
  896. `endif
  897. .CLKOUT0_USE_FINE_PS("TRUE"),
  898. .CLKOUT1_DIVIDE(32),
  899. .CLKOUT1_DUTY_CYCLE(0.500000),
  900. `ifdef ZORRO3
  901. .CLKOUT1_PHASE(0.000000),
  902. `elsif VARIANT_SUPERDENISE
  903. .CLKOUT1_PHASE(0.000000),
  904. `elsif VARIANT_ZZ9500
  905. .CLKOUT1_PHASE(270.000000),
  906. `else
  907. .CLKOUT1_PHASE(135.000000),
  908. `endif
  909. .CLKOUT1_USE_FINE_PS("TRUE"),
  910. .COMPENSATION("ZHOLD"),
  911. .DIVCLK_DIVIDE(1),
  912. .IS_CLKINSEL_INVERTED(1'b0),
  913. .IS_PSEN_INVERTED(1'b0),
  914. .IS_PSINCDEC_INVERTED(1'b0),
  915. .IS_PWRDWN_INVERTED(1'b0),
  916. .IS_RST_INVERTED(1'b0),
  917. .REF_JITTER1(0.001000),
  918. .REF_JITTER2(0.001000),
  919. .SS_EN("FALSE"),
  920. .SS_MODE("CENTER_HIGH"),
  921. .SS_MOD_PERIOD(10000),
  922. .STARTUP_WAIT("FALSE"))
  923. mmcm_adv_inst
  924. (.CLKFBIN(clkfbout_zz9000_ps_clk_wiz_1_0),
  925. .CLKFBOUT(clkfbout_zz9000_ps_clk_wiz_1_0),
  926. //.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
  927. //.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
  928. .CLKIN1(ZORRO_E7M),
  929. .CLKIN2(1'b0),
  930. .CLKINSEL(1'b1),
  931. //.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
  932. .CLKOUT0(e7m_shifted),
  933. //.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
  934. .CLKOUT1(e7m_shifted180),
  935. //.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
  936. .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
  937. .DCLK(1'b0),
  938. .DEN(1'b0),
  939. .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
  940. //.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
  941. //.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
  942. .DWE(1'b0),
  943. //.LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED),
  944. .PSCLK(S_AXI_ACLK),
  945. //.PSDONE(psdone),
  946. .PSEN(E7M_PSEN),
  947. .PSINCDEC(E7M_PSINCDEC),
  948. .PWRDWN(1'b0),
  949. .RST(1'b0));
  950. always @(posedge e7m_shifted) begin
  951. videocap_vs <= {videocap_vs[5:0], VCAP_VSYNC};
  952. videocap_hs <= {videocap_hs[5:0], VCAP_HSYNC};
  953. `ifdef VARIANT_ZZ9500
  954. videocap_rgbin <= {VCAP_R3,VCAP_R2,VCAP_R1,VCAP_R0,VCAP_R3,VCAP_R2,VCAP_R1,VCAP_R0,
  955. VCAP_G3,VCAP_G2,VCAP_G1,VCAP_G0,VCAP_G3,VCAP_G2,VCAP_G1,VCAP_G0,
  956. VCAP_B3,VCAP_B2,VCAP_B1,VCAP_B0,VCAP_B3,VCAP_B2,VCAP_B1,VCAP_B0};
  957. `elsif ZORRO2
  958. videocap_rgbin <= {VCAP_R7,VCAP_R6,VCAP_R5,VCAP_R4,VCAP_R7,VCAP_R6,VCAP_R5,VCAP_R4,
  959. VCAP_G7,VCAP_G6,VCAP_G5,VCAP_G4,VCAP_G7,VCAP_G6,VCAP_G5,VCAP_G4,
  960. VCAP_B7,VCAP_B6,VCAP_B5,VCAP_B4,VCAP_B7,VCAP_B6,VCAP_B5,VCAP_B4};
  961. `else
  962. videocap_rgbin <= {VCAP_R7,VCAP_R6,VCAP_R5,VCAP_R4,VCAP_R3,VCAP_R2,VCAP_R1,VCAP_R0,
  963. VCAP_G7,VCAP_G6,VCAP_G5,VCAP_G4,VCAP_G3,VCAP_G2,VCAP_G1,VCAP_G0,
  964. VCAP_B7,VCAP_B6,VCAP_B5,VCAP_B4,VCAP_B3,VCAP_B2,VCAP_B1,VCAP_B0};
  965. `endif
  966. if (videocap_hs==0) begin
  967. if (videocap_hs_pulse_width<'hff)
  968. videocap_hs_pulse_width<=videocap_hs_pulse_width+1;
  969. end else if (videocap_hs=='b111111)
  970. videocap_hs_pulse_width<=0;
  971. `ifdef VARIANT_ZZ9500
  972. // on A500, HSYNC is really CSYNC and we can recognize vertical sync
  973. // by looking at the pulse width of it
  974. // direct sampling from denise
  975. if(videocap_hs[6:1]=='b000111 && videocap_hs_pulse_width>=128) begin
  976. if (videocap_ymax[0]) begin
  977. videocap_interlace <= 1;
  978. end else begin
  979. videocap_interlace <= 0;
  980. end
  981. videocap_lace_field <= vc_next_lace_field;
  982. if (videocap_ymax>='h130)
  983. videocap_ntsc <= 0;
  984. else
  985. videocap_ntsc <= 1;
  986. if (videocap_interlace) begin
  987. videocap_y2 <= 0;
  988. videocap_y3 <= vc_next_lace_field;
  989. end else begin
  990. videocap_y2 <= 0;
  991. videocap_y3 <= 0;
  992. end
  993. `else
  994. // with videoslot machines, we have a real VSYNC to work with
  995. if (videocap_vs[6:1]=='b111000) begin
  996. if (videocap_ymax[0]!=videocap_ymax2[0])
  997. videocap_interlace <= 1;
  998. else
  999. videocap_interlace <= 0;
  1000. videocap_lace_field <= videocap_ymax[0];
  1001. if (videocap_ymax>='h138)
  1002. videocap_ntsc <= 0;
  1003. else
  1004. videocap_ntsc <= 1;
  1005. if (videocap_interlace) begin
  1006. videocap_y2 <= 0;
  1007. videocap_y3 <= videocap_lace_field;
  1008. end else begin
  1009. videocap_y2 <= 0;
  1010. videocap_y3 <= 0;
  1011. end
  1012. `endif
  1013. if (videocap_y2!=0) begin
  1014. videocap_ymax <= videocap_y2;
  1015. videocap_ymax2 <= videocap_ymax;
  1016. end
  1017. end else if (videocap_hs[6:1]=='b000111) begin
  1018. videocap_x <= 0;
  1019. videocap_x2 <= 0;
  1020. `ifdef VARIANT_ZZ9500
  1021. if (videocap_hs_pulse_width < 'h20) begin
  1022. // count short pulses terminating lines
  1023. vc_shortlines <= vc_shortlines+1;
  1024. if (vc_shortlines==0) begin
  1025. // first time
  1026. if (videocap_x>='h200)
  1027. // last line was long?
  1028. vc_next_lace_field <= 1;
  1029. else
  1030. vc_next_lace_field <= 0;
  1031. end
  1032. end else
  1033. vc_shortlines <= 0;
  1034. `endif
  1035. if (videocap_y2>'h1a) begin
  1036. if (videocap_interlace)
  1037. videocap_y3 <= videocap_y3 + 2'b10;
  1038. else
  1039. videocap_y3 <= videocap_y3 + 1'b1;
  1040. end
  1041. videocap_y2 <= videocap_y2 + 1'b1;
  1042. end else if (videocap_x2<'h5e) begin // 5a worked
  1043. // left crop
  1044. videocap_x2 <= videocap_x2 + 1'b1;
  1045. end else begin
  1046. videocap_x <= videocap_x + 1'b1;
  1047. end
  1048. if (videocap_x>2)
  1049. videocap_buf[videocap_x] <= videocap_rgbin;
  1050. else
  1051. videocap_buf[videocap_x] <= 0;
  1052. if (videocap_x>'h200)
  1053. videocap_x_done <= 1;
  1054. else
  1055. videocap_x_done <= 0;
  1056. end
  1057. reg [11:0] videocap_save_x;
  1058. reg [11:0] videocap_save_x2;
  1059. reg [11:0] videocap_save_x3;
  1060. reg [11:0] videocap_yoffset;
  1061. reg [11:0] videocap_xoffset;
  1062. reg [11:0] videocap_pitch;
  1063. reg [11:0] videocap_pitch_sync;
  1064. reg [11:0] videocap_pitch_snoop;
  1065. reg videocap_pitch_snooped;
  1066. reg [9:0] videocap_save_line_done;
  1067. reg [11:0] videocap_save_y;
  1068. reg [31:0] videocap_save_y2;
  1069. reg [31:0] videocap_save_addr;
  1070. reg [3:0] videocap_save_state;
  1071. reg videocap_mode_sync;
  1072. reg [31:0] m01_axi_awaddr_out;
  1073. reg [31:0] m01_axi_wdata_out;
  1074. reg m01_axi_awvalid_out = 0;
  1075. reg m01_axi_wvalid_out = 0;
  1076. reg [31:0] m00_axi_awaddr_z3;
  1077. reg [31:0] m00_axi_wdata_z3;
  1078. reg m00_axi_awvalid_z3 = 0;
  1079. reg m00_axi_wvalid_z3 = 0;
  1080. reg [3:0] m00_axi_wstrb_z3;
  1081. assign m00_axi_awaddr = m00_axi_awaddr_z3;
  1082. assign m00_axi_awvalid = m00_axi_awvalid_z3;
  1083. assign m00_axi_wdata = m00_axi_wdata_z3;
  1084. assign m00_axi_wstrb = m00_axi_wstrb_z3;
  1085. assign m00_axi_wvalid = m00_axi_wvalid_z3;
  1086. assign m01_axi_awaddr = m01_axi_awaddr_out;
  1087. assign m01_axi_awvalid = m01_axi_awvalid_out;
  1088. assign m01_axi_wdata = m01_axi_wdata_out;
  1089. assign m01_axi_wstrb = 4'b1111;
  1090. assign m01_axi_wvalid = m01_axi_wvalid_out;
  1091. // AXI DMA defaults
  1092. always @(posedge S_AXI_ACLK) begin
  1093. m00_axi_awlen <= 'h0; // 1 burst (1 write)
  1094. m00_axi_awsize <= 'h2; // 2^2 == 4 bytes
  1095. m00_axi_awburst <= 'h0; // FIXED (non incrementing)
  1096. m00_axi_awcache <= 'h3;
  1097. m00_axi_awlock <= 'h0;
  1098. m00_axi_awprot <= 'h0;
  1099. //m00_axi_awqos <= 'h0;
  1100. m00_axi_wlast <= 'h1;
  1101. m00_axi_bready <= 'h1;
  1102. m00_axi_arlen <= 'h0;
  1103. m00_axi_arsize <= 'h2;
  1104. m00_axi_arburst <= 'h0;
  1105. m00_axi_arcache <= 'hf; //was 3
  1106. m00_axi_arlock <= 'h0;
  1107. m00_axi_arprot <= 'h0;
  1108. //m00_axi_arqos <= 'h0;
  1109. m00_axi_rready <= 1;
  1110. // FIXME this could use bursts
  1111. m01_axi_awlen <= 'h0; // 1 burst (1 write)
  1112. m01_axi_awsize <= 'h2; //'h2; // 2^2 == 4 bytes
  1113. m01_axi_awburst <= 'h0; // FIXED (non incrementing)
  1114. m01_axi_awcache <= 'h0;
  1115. m01_axi_awlock <= 'h0;
  1116. m01_axi_awprot <= 'h0;
  1117. m01_axi_awqos <= 'h0;
  1118. m01_axi_wlast <= 'h1;
  1119. m01_axi_bready <= 'h1;
  1120. `ifdef ZORRO2
  1121. // ZORRO2 doesn't implement AXI DMA read yet
  1122. m00_axi_araddr <= 0;
  1123. m00_axi_arvalid <= 0;
  1124. m00_axi_rready <= 0;
  1125. `endif
  1126. end
  1127. reg [9:0] videocap_x_sync;
  1128. reg [9:0] vc_saving_line;
  1129. reg [9:0] videocap_y_sync2;
  1130. // pipeline stages for videocap save addr calculation
  1131. reg [31:0] vc_saveaddr1;
  1132. reg [31:0] vc_saveaddr2;
  1133. always @(posedge S_AXI_ACLK) begin
  1134. // VIDEOCAP
  1135. // pass interlace mode to video control block
  1136. video_control_interlace <= videocap_interlace;
  1137. videocap_pitch_sync <= videocap_pitch;
  1138. //videocap_x_sync <= videocap_x;
  1139. videocap_y_sync2 <= videocap_y3;
  1140. videocap_mode_sync <= videocap_mode;
  1141. `ifdef VARIANT_ZZ9500
  1142. if (videocap_interlace)
  1143. videocap_ymax_sync <= (videocap_ymax<<1)-(2*40);
  1144. else
  1145. videocap_ymax_sync <= videocap_ymax-36;
  1146. // letterbox top and bottom to box out noisy lines
  1147. if (videocap_y_sync2<videocap_ymax_sync && videocap_x_done) begin
  1148. videocap_y_sync <= videocap_y_sync2;
  1149. end
  1150. `else
  1151. if (videocap_interlace)
  1152. videocap_ymax_sync <= (videocap_ymax<<1);
  1153. else
  1154. videocap_ymax_sync <= videocap_ymax;
  1155. if (videocap_x_done) begin
  1156. videocap_y_sync <= videocap_y_sync2;
  1157. end
  1158. `endif
  1159. videocap_save_x2 <= videocap_save_x;
  1160. vc_saveaddr1 <= vc_saving_line*videocap_pitch_sync;
  1161. // we shift left by 2 bits to scale from 1 pixel to 4 bytes
  1162. vc_saveaddr2 <= (vc_saveaddr1+videocap_save_x)<<2;
  1163. // FIXME
  1164. if (videocap_save_line_done!=videocap_y_sync) begin
  1165. vc_saving_line <= videocap_y_sync;
  1166. end
  1167. if (m01_axi_aresetn == 0) begin
  1168. videocap_save_state <= 4;
  1169. //m01_axi_wvalid_out <= 0;
  1170. //m01_axi_awvalid_out <= 0;
  1171. end else begin
  1172. m01_axi_awaddr_out <= `VIDEOCAP_ADDR+vc_saveaddr2;
  1173. m01_axi_wdata_out <= videocap_buf[videocap_save_x];
  1174. // one-hot encoded
  1175. case (videocap_save_state)
  1176. 4'h0: begin
  1177. // initial state
  1178. if (m01_axi_awready) begin
  1179. videocap_save_state <= 2;
  1180. end
  1181. end
  1182. 4'h1: begin
  1183. m01_axi_awvalid_out <= 0;
  1184. m01_axi_wvalid_out <= 1;
  1185. if (m01_axi_wready) begin
  1186. videocap_save_state <= 2;
  1187. end
  1188. end
  1189. 4'h2: begin
  1190. // FIXME this was moved from state 1 wready clause
  1191. `ifdef VARIANT_ZZ9500
  1192. if (videocap_save_x >= videocap_pitch_sync-2) begin
  1193. `else
  1194. if (videocap_save_x >= videocap_pitch_sync) begin // 728 FIXME
  1195. `endif
  1196. videocap_save_line_done <= vc_saving_line;
  1197. videocap_save_x <= 0;
  1198. end else if (videocap_save_line_done != vc_saving_line)
  1199. videocap_save_x <= videocap_save_x + 1'b1;
  1200. m01_axi_awvalid_out <= 1;
  1201. m01_axi_wvalid_out <= 0;
  1202. if (m01_axi_awready) begin
  1203. if (videocap_mode_sync)
  1204. videocap_save_state <= 1;
  1205. else
  1206. videocap_save_state <= 4;
  1207. end
  1208. end
  1209. 4'h4: begin
  1210. // videocap is disabled, lets wait here
  1211. if (videocap_mode_sync)
  1212. videocap_save_state <= 0;
  1213. m01_axi_wvalid_out <= 0;
  1214. m01_axi_awvalid_out <= 0;
  1215. end
  1216. endcase
  1217. end
  1218. end
  1219. // -- main zorro fsm ---------------------------------------------
  1220. always @(posedge S_AXI_ACLK) begin
  1221. zorro_idle <= ((zorro_state==Z2_IDLE)||(zorro_state==Z3_IDLE));
  1222. `ifndef VARIANT_FW20
  1223. // FIXME videocap disabled for FW20
  1224. videocap_mode <= videocap_mode_in;
  1225. `endif
  1226. if (/*z_cfgin_lo ||*/ z_reset) begin
  1227. zorro_state <= RESET;
  1228. end //else
  1229. case (zorro_state)
  1230. COLD: begin
  1231. zorro_state <= RESET;
  1232. end
  1233. RESET: begin
  1234. dataout_enable <= 0;
  1235. dataout <= 0;
  1236. dataout_z3 <= 0;
  1237. slaven <= 0;
  1238. dtack <= 0;
  1239. z_ovr <= 0;
  1240. z_confout <= 0;
  1241. z3_confdone <= 0;
  1242. zorro_ram_read_request <= 0;
  1243. zorro_ram_write_request <= 0;
  1244. zorro_ram_read_flag <= 0;
  1245. zorro_ram_write_flag <= 0;
  1246. videocap_mode_in <= 0;
  1247. videocap_pitch <= 720; // FIXME?
  1248. if (!z_reset)
  1249. zorro_state <= DECIDE_Z2_Z3;
  1250. // uncomment this to have native video capture
  1251. // directly on startup, before/without autoconfig.
  1252. // we don't do this by default because it messes
  1253. // up the timing sometimes.
  1254. //videocap_mode_in <= 1;
  1255. end
  1256. DECIDE_Z2_Z3: begin
  1257. `ifdef ZORRO2
  1258. if (z2addr_autoconfig) begin
  1259. //ZORRO3 <= 0;
  1260. zorro_state <= Z2_CONFIGURING;
  1261. end
  1262. `endif
  1263. `ifdef ZORRO3
  1264. if (z3addr_autoconfig) begin
  1265. //ZORRO3 <= 1;
  1266. zorro_state <= Z3_CONFIGURING;
  1267. end
  1268. `endif
  1269. end
  1270. `ifdef ZORRO3
  1271. Z3_AUTOCONF_READ_DLY: begin
  1272. // wait for data to be latched out
  1273. zorro_state <= Z3_AUTOCONF_READ_DLY2;
  1274. end
  1275. Z3_AUTOCONF_READ_DLY2: begin
  1276. // wait for data to be latched out
  1277. zorro_state <= Z3_DTACK;
  1278. end
  1279. Z3_AUTOCONF_READ: begin
  1280. dataout_z3 <= 1;
  1281. slaven <= 1;
  1282. zorro_state <= Z3_AUTOCONF_READ_DLY;
  1283. last_z3addr <= z3addr;
  1284. case (z3addr[15:0])
  1285. 'h0000: data_z3_hi16 <= 'b1000_1111_1111_1111; // zorro 3 (10), no pool link (0), autoboot ROM (1)
  1286. 'h0100: data_z3_hi16 <= 'b0100_1111_1111_1111; // next board unrelated (0), 256MB 1024MB fixme
  1287. 'h0004: data_z3_hi16 <= 'b1111_1111_1111_1111; // product number
  1288. 'h0104: data_z3_hi16 <= 'b1011_1111_1111_1111; // (4)
  1289. 'h0008: data_z3_hi16 <= 'b0000_1111_1111_1111; // flags inverted 0111 io,shutup,extension,reserved(1)
  1290. 'h0108: data_z3_hi16 <= 'b1111_1111_1111_1111; // inverted zero
  1291. 'h000c: data_z3_hi16 <= 'b1111_1111_1111_1111; // reserved?
  1292. 'h010c: data_z3_hi16 <= 'b1111_1111_1111_1111; //
  1293. 'h0010: data_z3_hi16 <= 'b1001_1111_1111_1111; // manufacturer high byte inverted
  1294. 'h0110: data_z3_hi16 <= 'b0010_1111_1111_1111; //
  1295. 'h0014: data_z3_hi16 <= 'b1001_1111_1111_1111; // manufacturer low byte
  1296. 'h0114: data_z3_hi16 <= 'b0001_1111_1111_1111;
  1297. 'h0018: data_z3_hi16 <= 'b1111_1111_1111_1111; // serial 01 01 01 01
  1298. 'h0118: data_z3_hi16 <= 'b1110_1111_1111_1111; //
  1299. 'h001c: data_z3_hi16 <= 'b1111_1111_1111_1111; //
  1300. 'h011c: data_z3_hi16 <= 'b1110_1111_1111_1111; //
  1301. 'h0020: data_z3_hi16 <= 'b1111_1111_1111_1111; //
  1302. 'h0120: data_z3_hi16 <= 'b1110_1111_1111_1111; //
  1303. 'h0024: data_z3_hi16 <= 'b1111_1111_1111_1111; //
  1304. 'h0124: data_z3_hi16 <= 'b1110_1111_1111_1111; //
  1305. /*'h0028: data_z3_hi16 <= 'b1111_1111_1111_1111; // autoboot rom vector (er_InitDiagVec)
  1306. 'h0128: data_z3_hi16 <= 'b1111_1111_1111_1111; // ff7f = ~0080
  1307. 'h002c: data_z3_hi16 <= 'b0111_1111_1111_1111;
  1308. 'h012c: data_z3_hi16 <= 'b1111_1111_1111_1111;*/
  1309. default: data_z3_hi16 <= 'b1111_1111_1111_1110; // FIXME
  1310. endcase
  1311. end
  1312. Z3_AUTOCONF_WRITE: begin
  1313. slaven <= 1;
  1314. if (z3_ds0||z3_ds1||z3_ds2||z3_ds3) begin
  1315. zorro_state <= Z3_DTACK;
  1316. casex (z3addr[15:0])
  1317. 'hXX44: begin
  1318. z3_ram_low[31:16] <= z3_din_high_s2;
  1319. z_confout <= 1;
  1320. z3_confdone <= 1;
  1321. end
  1322. 'hXX48: begin
  1323. end
  1324. 'hXX4c: begin
  1325. // shutup
  1326. z_confout <= 1;
  1327. z3_confdone <= 1;
  1328. end
  1329. endcase
  1330. end
  1331. end
  1332. Z3_CONFIGURING: begin
  1333. // FIXME why?
  1334. //data_z3_low16 <= 'hffff;
  1335. if (z_cfgin && z3addr_autoconfig) begin
  1336. if (zorro_read) begin
  1337. // autoconfig ROM
  1338. zorro_state <= Z3_AUTOCONF_READ;
  1339. end else begin
  1340. // write to autoconfig register
  1341. zorro_state <= Z3_AUTOCONF_WRITE;
  1342. end
  1343. end
  1344. dataout_z3 <= 0;
  1345. slaven <= 0;
  1346. dtack <= 0;
  1347. end
  1348. Z3_DTACK: begin
  1349. if (z3_fcs_state == 1) begin
  1350. dtack <= 0;
  1351. dataout_z3 <= 0;
  1352. slaven <= 0;
  1353. if (z3_confdone) begin
  1354. zorro_state <= CONFIGURED;
  1355. end else
  1356. zorro_state <= Z3_CONFIGURING;
  1357. end else
  1358. dtack <= 1;
  1359. end
  1360. `endif
  1361. CONFIGURED: begin
  1362. ram_high <= ram_low + `RAM_SIZE;
  1363. reg_low <= ram_low + 'h1000;
  1364. reg_high <= ram_low + 'h2000;
  1365. z3_ram_high <= z3_ram_low + `Z3_RAM_SIZE;
  1366. z3_reg_low <= z3_ram_low + 'h1000;
  1367. z3_reg_high <= z3_ram_low + 'h2000;
  1368. zorro_state <= CONFIGURED_CLEAR;
  1369. end
  1370. CONFIGURED_CLEAR: begin
  1371. // this is a fix for the "pixel swap" bug: if AXI HP is getting writes too early,
  1372. // it would sometimes (~10% of cold starts) get confused and swap pairs of writes.
  1373. `ifndef VARIANT_FW20
  1374. videocap_mode_in <= 1;
  1375. `endif
  1376. `ifdef ZORRO3
  1377. zorro_state <= Z3_IDLE;
  1378. `else
  1379. zorro_state <= Z2_IDLE;
  1380. `endif
  1381. end
  1382. // ---------------------------------------------------------------------------------
  1383. `ifdef ZORRO2
  1384. Z2_CONFIGURING: begin
  1385. z_ovr <= 0;
  1386. if (z2_addr_valid && z2addr_autoconfig && z_cfgin) begin
  1387. if (z2_read) begin
  1388. // read iospace 'he80000 (Autoconfig ROM)
  1389. dataout_enable <= 1;
  1390. dataout <= 1;
  1391. slaven <= 1;
  1392. case (z2_mapped_addr[7:0])
  1393. 8'h00: data_out <= 'b1101_1111_1111_1111; // zorro 2 (11), no pool (0) rom (1)
  1394. `ifdef VARIANT_2MB
  1395. 8'h02: data_out <= 'b0110_1111_1111_1111; // next board unrelated (0), 2mb (110)
  1396. `else
  1397. 8'h02: data_out <= 'b0111_1111_1111_1111; // next board unrelated (0), 4mb (111)
  1398. `endif
  1399. 8'h04: data_out <= 'b1111_1111_1111_1111; // product number
  1400. 8'h06: data_out <= 'b1100_1111_1111_1111; // (3)
  1401. 8'h08: data_out <= 'b0011_1111_1111_1111; // flags inverted 0011
  1402. 8'h0a: data_out <= 'b1110_1111_1111_1111; // inverted 0001 = OS sized
  1403. 8'h10: data_out <= 'b1001_1111_1111_1111; // manufacturer high byte inverted (02)
  1404. 8'h12: data_out <= 'b0010_1111_1111_1111; //
  1405. 8'h14: data_out <= 'b1001_1111_1111_1111; // manufacturer low byte (9a)
  1406. 8'h16: data_out <= 'b0001_1111_1111_1111;
  1407. 8'h18: data_out <= 'b1111_1111_1111_1111; // serial 01 01 01 01
  1408. 8'h1a: data_out <= 'b1110_1111_1111_1111; //
  1409. 8'h1c: data_out <= 'b1111_1111_1111_1111; //
  1410. 8'h1e: data_out <= 'b1110_1111_1111_1111; //
  1411. 8'h20: data_out <= 'b1111_1111_1111_1111; //
  1412. 8'h22: data_out <= 'b1110_1111_1111_1111; //
  1413. 8'h24: data_out <= 'b1111_1111_1111_1111; //
  1414. 8'h26: data_out <= 'b1110_1111_1111_1111; //
  1415. /*8'h28: data_out <= 'b1111_1111_1111_1111; // autoboot rom vector (er_InitDiagVec)
  1416. 8'h2a: data_out <= 'b1111_1111_1111_1111; // ff7f = ~0080
  1417. 8'h2c: data_out <= 'b0111_1111_1111_1111;
  1418. 8'h2e: data_out <= 'b1111_1111_1111_1111;*/
  1419. //'h000040: data <= 'b0000_0000_0000_0000; // interrupts (not inverted)
  1420. //'h000042: data <= 'b0000_0000_0000_0000; //
  1421. default: data_out <= 'b1111_1111_1111_1111;
  1422. endcase
  1423. end else begin
  1424. // write to autoconfig register
  1425. if (z2_datastrobe_synced) begin
  1426. case (z2_mapped_addr[7:0])
  1427. 8'h48: begin
  1428. ram_low[31:24] <= 8'h0;
  1429. ram_low[23:20] <= zdata_in_sync[15:12];
  1430. ram_low[15:0] <= 16'h0;
  1431. zorro_state <= Z2_PRE_CONFIGURED; // configured
  1432. end
  1433. 8'h4a: begin
  1434. ram_low[31:24] <= 8'h0;
  1435. ram_low[19:16] <= zdata_in_sync[15:12];
  1436. ram_low[15:0] <= 16'h0;
  1437. end
  1438. 8'h4c: begin
  1439. zorro_state <= Z2_PRE_CONFIGURED; // configured, shut up
  1440. end
  1441. endcase
  1442. end
  1443. end
  1444. end else begin
  1445. // no address match
  1446. dataout <= 0;
  1447. dataout_enable <= 0;
  1448. slaven <= 0;
  1449. end
  1450. end
  1451. Z2_PRE_CONFIGURED: begin
  1452. if (!z2_addr_valid) begin
  1453. z_confout<=1;
  1454. zorro_state <= CONFIGURED;
  1455. end
  1456. end
  1457. Z2_IDLE: begin
  1458. if (z2_addr_valid) begin
  1459. if (z2_write && z2addr_in_reg) begin
  1460. // write to register
  1461. dataout_enable <= 0;
  1462. dataout <= 0;
  1463. slaven <= 1;
  1464. z_ovr <= 1;
  1465. zaddr_regpart <= z2_mapped_addr;
  1466. zorro_state <= Z2_REGWRITE;
  1467. end else if (z2_read && z2addr_in_reg) begin
  1468. // read from registers
  1469. dataout_enable <= 1;
  1470. dataout <= 1;
  1471. data_out <= default_data; //'hffff;
  1472. slaven <= 1;
  1473. z_ovr <= 1;
  1474. zaddr_regpart <= z2_mapped_addr;
  1475. zorro_state <= Z2_REGREAD;
  1476. end else if (z2_read && z2addr_in_ram) begin
  1477. // read RAM
  1478. // request ram access from arbiter
  1479. last_addr <= z2_mapped_addr-ram_low; // differently done in z3
  1480. data_out <= default_data; //'hffff;
  1481. dataout_enable <= 1;
  1482. dataout <= 1;
  1483. slaven <= 1;
  1484. z_ovr <= 1;
  1485. zorro_state <= WAIT_READ3;
  1486. end else if (z2_write && z2addr_in_ram) begin
  1487. // write RAM
  1488. last_addr <= z2_mapped_addr-ram_low;
  1489. dataout_enable <= 0;
  1490. dataout <= 0;
  1491. datain_counter <= 0;
  1492. slaven <= 1;
  1493. z_ovr <= 1;
  1494. //count_writes <= count_writes + 1;
  1495. zorro_state <= WAIT_WRITE;
  1496. end else begin
  1497. dataout <= 0;
  1498. dataout_enable <= 0;
  1499. slaven <= 0;
  1500. end
  1501. end else begin
  1502. dataout <= 0;
  1503. dataout_enable <= 0;
  1504. slaven <= 0;
  1505. end
  1506. end
  1507. Z2_REGWRITE: begin
  1508. if (z2_datastrobe_synced) begin
  1509. regdata_in <= zdata_in_sync;
  1510. regwrite_addr <= zaddr_regpart;
  1511. zorro_state <= REGWRITE;
  1512. end
  1513. end
  1514. WAIT_READ3: begin
  1515. zorro_ram_read_addr <= last_addr;
  1516. zorro_ram_read_request <= 1;
  1517. zorro_state <= WAIT_READ2;
  1518. end
  1519. WAIT_READ2: begin
  1520. // FIXME there can be a race here where read_request is immediately cancelled
  1521. if (zorro_ram_read_flag) begin
  1522. zorro_ram_read_request <= 0;
  1523. data_out <= axi_reg1[15:0];
  1524. zorro_state <= WAIT_READ2B;
  1525. end
  1526. end
  1527. WAIT_READ2B: begin
  1528. // FIXME trying to fix the race using the same approach as in Z3
  1529. if (!zorro_ram_read_flag) begin
  1530. read_counter <= 0;
  1531. zorro_state <= WAIT_READ2C;
  1532. end
  1533. end
  1534. WAIT_READ2C: begin
  1535. //if (read_counter>7) // FIXME tune this
  1536. zorro_state <= WAIT_READ2D;
  1537. //read_counter <= read_counter + 1'b1;
  1538. end
  1539. WAIT_READ2D: begin
  1540. read_counter <= 0;
  1541. dtack <= 1;
  1542. zorro_state <= Z2_ENDCYCLE;
  1543. end
  1544. WAIT_WRITE: begin
  1545. if (z2_datastrobe_synced) begin
  1546. zorro_write_capture_bytes <= {~znUDS_sync[2],~znLDS_sync[2]}; // FIXME was 1
  1547. zorro_write_capture_data <= zdata_in_sync;
  1548. if (last_addr<'h10000)
  1549. zorro_state <= WAIT_WRITE2;
  1550. else
  1551. zorro_state <= WAIT_WRITE_DMA_Z2;
  1552. end
  1553. end
  1554. WAIT_WRITE2: begin
  1555. zorro_ram_write_addr <= last_addr;
  1556. zorro_ram_write_bytes <= {2'b0,zorro_write_capture_bytes};
  1557. zorro_ram_write_data <= {16'b0,zorro_write_capture_data};
  1558. zorro_ram_write_request <= 1;
  1559. zorro_state <= Z2_WRITE_FINALIZE;
  1560. end
  1561. WAIT_WRITE_DMA_Z2: begin
  1562. if (last_addr[1])
  1563. m00_axi_wstrb_z3 <= {zorro_write_capture_bytes[0],zorro_write_capture_bytes[1],2'b0};
  1564. else
  1565. m00_axi_wstrb_z3 <= {2'b0,zorro_write_capture_bytes[0],zorro_write_capture_bytes[1]};
  1566. m00_axi_awaddr_z3 <= (last_addr+`ARM_MEMORY_START)&'hfffffc;
  1567. m00_axi_wdata_z3 <= {zorro_write_capture_data[7:0],zorro_write_capture_data[15:8],zorro_write_capture_data[7:0],zorro_write_capture_data[15:8]};
  1568. m00_axi_awvalid_z3 <= 1;
  1569. if (m00_axi_awready) begin // TODO wready?
  1570. zorro_state <= WAIT_WRITE_DMA_Z2_FINALIZE;
  1571. end
  1572. end
  1573. WAIT_WRITE_DMA_Z2_FINALIZE: begin
  1574. m00_axi_awvalid_z3 <= 0;
  1575. m00_axi_wvalid_z3 <= 1;
  1576. if (m00_axi_wready) begin
  1577. dtack <= 1;
  1578. zorro_state <= Z2_ENDCYCLE;
  1579. end
  1580. end
  1581. Z2_WRITE_FINALIZE: begin
  1582. if (zorro_ram_write_flag) begin
  1583. dtack <= 1;
  1584. zorro_state <= Z2_ENDCYCLE;
  1585. zorro_ram_write_request <= 0;
  1586. end
  1587. end
  1588. Z2_ENDCYCLE: begin
  1589. m00_axi_wvalid_z3 <= 0;
  1590. z_ovr <= 0;
  1591. // FIXME
  1592. read_counter <= read_counter + 1'b1;
  1593. if (read_counter >= 10) begin
  1594. dtack <= 0;
  1595. end
  1596. if (!z2_addr_valid) begin
  1597. dtack <= 0;
  1598. slaven <= 0;
  1599. dataout_enable <= 0;
  1600. dataout <= 0;
  1601. zorro_state <= Z2_IDLE;
  1602. read_counter <= 0;
  1603. end
  1604. end
  1605. // 16bit reg read
  1606. Z2_REGREAD_POST: begin
  1607. if (zaddr_regpart[1]==1'b1)
  1608. data_out <= rr_data[15:0];
  1609. else
  1610. data_out <= rr_data[31:16];
  1611. dtack <= 1;
  1612. zorro_state <= Z2_ENDCYCLE;
  1613. end
  1614. // relaxing the data pipeline a bit
  1615. Z2_REGREAD: begin
  1616. regread_addr <= zaddr_regpart;
  1617. zorro_state <= REGREAD;
  1618. end
  1619. `endif
  1620. `ifdef ZORRO3
  1621. // =========================================================================
  1622. // ZORRO 3
  1623. // =========================================================================
  1624. Z3_REGWRITE_PRE: begin
  1625. if (z3_ds1) begin
  1626. regdata_in <= z3_din_low_s2;
  1627. z3addr_regpart <= (z3addr[15:0])|16'h2;
  1628. zorro_state <= Z3_REGWRITE;
  1629. end else if (z3_ds3) begin
  1630. regdata_in <= z3_din_high_s2;
  1631. z3addr_regpart <= z3addr[15:0];
  1632. zorro_state <= Z3_REGWRITE;
  1633. end
  1634. end
  1635. Z3_REGREAD_PRE: begin
  1636. z3addr_regpart <= z3addr[15:0]; //|16'h2;
  1637. zorro_state <= Z3_REGREAD;
  1638. dataout_z3 <= 1;
  1639. end
  1640. Z3_IDLE: begin
  1641. read_counter <= 0;
  1642. if (z3_fcs_state==0) begin
  1643. // falling edge of /FCS
  1644. if (zorro_write && z3addr_in_reg) begin
  1645. // FIXME doesn't support 32 bit access
  1646. // write to register
  1647. zorro_state <= Z3_REGWRITE_PRE;
  1648. slaven <= 1;
  1649. end else if (zorro_read && z3addr_in_reg) begin
  1650. // read registers
  1651. data_z3_hi16 <= default_data;
  1652. data_z3_low16 <= default_data;
  1653. zorro_state <= Z3_REGREAD_PRE;
  1654. slaven <= 1;
  1655. end else if (z3addr_in_ram && zorro_write) begin
  1656. // write to memory
  1657. slaven <= 1;
  1658. zorro_state <= Z3_WRITE_PRE;
  1659. end else if (z3addr_in_ram && zorro_read) begin
  1660. // read from memory
  1661. data_z3_hi16 <= default_data;
  1662. data_z3_low16 <= default_data;
  1663. slaven <= 1;
  1664. if (z3_mapped_addr<'h2000)
  1665. zorro_state <= Z3_READ_UPPER;
  1666. else
  1667. zorro_state <= WAIT_READ_DMA_Z3;
  1668. end else begin
  1669. // address not recognized
  1670. slaven <= 0;
  1671. end
  1672. end else begin
  1673. // not in a cycle
  1674. slaven <= 0;
  1675. end
  1676. end
  1677. Z3_REGWRITE: begin
  1678. regwrite_addr <= z3addr_regpart;
  1679. zorro_state <= REGWRITE;
  1680. dtack <= 1;
  1681. end
  1682. Z3_REGREAD: begin
  1683. regread_addr <= z3addr_regpart;
  1684. zorro_state <= REGREAD;
  1685. end
  1686. // 32bit reg read
  1687. Z3_REGREAD_POST: begin
  1688. data_z3_hi16 <= rr_data[31:16];
  1689. data_z3_low16 <= rr_data[15:0];
  1690. zorro_state <= Z3_ENDCYCLE;
  1691. dtack <= 1;
  1692. end
  1693. Z3_READ_UPPER: begin
  1694. zorro_state <= Z3_READ_DELAY1;
  1695. last_z3addr <= z3_mapped_addr;
  1696. zorro_ram_read_addr <= z3_mapped_addr;
  1697. zorro_ram_read_bytes <= 4'b1111;
  1698. zorro_ram_read_request <= 1;
  1699. dataout_z3 <= 1; // enable data output
  1700. // dummy read for debug
  1701. /*dtack <= 1;
  1702. data_z3_hi16 <= 'hffff;
  1703. data_z3_low16 <= 'hffff;
  1704. zorro_state <= Z3_ENDCYCLE;*/
  1705. end
  1706. Z3_READ_DELAY1: begin
  1707. data_z3_hi16 <= axi_reg1[31:16];
  1708. data_z3_low16 <= axi_reg1[15:0];
  1709. if (zorro_ram_read_flag) begin
  1710. zorro_ram_read_request <= 0; // acknowledge read request done
  1711. zorro_state <= Z3_READ_DELAY2; // CHECK DELAY
  1712. end
  1713. end
  1714. Z3_READ_DELAY2: begin
  1715. if (!zorro_ram_read_flag) begin
  1716. zorro_state <= Z3_ENDCYCLE;
  1717. dtack <= 1;
  1718. slaven <= 0;
  1719. end
  1720. end
  1721. Z3_WRITE_PRE: begin
  1722. if (z3_ds0||z3_ds1||z3_ds2||z3_ds3) begin
  1723. zorro_state <= Z3_WRITE_PRE2;
  1724. end
  1725. end
  1726. Z3_WRITE_PRE2: begin
  1727. // FIXME DMA temporarily disabled for FW2.0
  1728. `ifdef VARIANT_FW20
  1729. zorro_state <= Z3_WRITE_UPPER;
  1730. `else
  1731. if (z3_mapped_addr<'h2000)
  1732. zorro_state <= Z3_WRITE_UPPER;
  1733. else
  1734. zorro_state <= WAIT_WRITE_DMA_Z3;
  1735. `endif
  1736. end
  1737. Z3_WRITE_UPPER: begin
  1738. last_z3addr <= z3_mapped_addr;
  1739. zorro_ram_write_addr <= z3_mapped_addr;
  1740. zorro_ram_write_bytes <= {z3_ds3,z3_ds2,z3_ds1,z3_ds0};
  1741. zorro_ram_write_data <= {z3_din_high_s2,z3_din_low_s2};
  1742. zorro_ram_write_request <= 1;
  1743. zorro_state <= Z3_WRITE_FINALIZE;
  1744. end
  1745. Z3_WRITE_FINALIZE: begin
  1746. if (zorro_ram_write_flag) begin
  1747. zorro_ram_write_request <= 0; // acknowledge write request done
  1748. zorro_state <= Z3_ENDCYCLE;
  1749. dtack <= 1;
  1750. slaven <= 0;
  1751. end
  1752. end
  1753. WAIT_READ_DMA_Z3: begin
  1754. if ( (z3_mapped_addr>='hA000)&&(z3_mapped_addr<'h10000) )
  1755. m00_axi_araddr <= (`USB_BLOCK_STORAGE_ADDRESS - 32'hA000) + z3_mapped_addr + {usbb[22:0],9'h0}; // 9'h0 is USB_BLOCK_SIZE = 512
  1756. else
  1757. if ( (z3_mapped_addr>='h8000)&&(z3_mapped_addr<'hA000) )
  1758. m00_axi_araddr <= (`TX_FRAME_ADDRESS - 32'h8000) + z3_mapped_addr;
  1759. else
  1760. if ( (z3_mapped_addr>='h2000)&&(z3_mapped_addr<'h8000) ) begin
  1761. m00_axi_araddr <= (`RX_BACKLOG_ADDRESS - 32'h2000) + z3_mapped_addr + {frfb[20:0],11'h0}; // 11'h0 is FRAME_SIZE = 2048
  1762. clear_interrupt<=1;
  1763. end else
  1764. m00_axi_araddr <= `ARM_MEMORY_START + (z3_mapped_addr/*&32'hfffffffc*/); // max 256MB
  1765. m00_axi_arvalid <= 1;
  1766. // m00_axi_rready <= 1;
  1767. if (m00_axi_arready) begin
  1768. zorro_state <= WAIT_READ_DMA_Z3B;
  1769. end
  1770. end
  1771. WAIT_READ_DMA_Z3B: begin
  1772. m00_axi_arvalid <= 0;
  1773. // m00_axi_rready <= 1;
  1774. if (m00_axi_rvalid) begin
  1775. zorro_state <= Z3_ENDCYCLE;
  1776. data_z3_hi16 <= {m00_axi_rdata[7:0], m00_axi_rdata[15:8]};
  1777. data_z3_low16 <= {m00_axi_rdata[23:16], m00_axi_rdata[31:24]};
  1778. dataout_z3 <= 1; // enable data output
  1779. dtack <= 1;
  1780. end
  1781. end
  1782. WAIT_WRITE_DMA_Z3: begin
  1783. m00_axi_wstrb_z3 <= {z3_ds0, z3_ds1, z3_ds2, z3_ds3};
  1784. if ( (z3_mapped_addr>='hA000)&&(z3_mapped_addr<'h10000) )
  1785. m00_axi_awaddr_z3 <= (`USB_BLOCK_STORAGE_ADDRESS - 32'hA000) + z3_mapped_addr + {usbb[22:0],9'h0}; // 9'h0 is USB_BLOCK_SIZE = 512
  1786. else
  1787. if ( (z3_mapped_addr>='h8000)&&(z3_mapped_addr<'hA000) )
  1788. m00_axi_awaddr_z3 <= (`TX_FRAME_ADDRESS - 32'h8000) + z3_mapped_addr;
  1789. else
  1790. if ( (z3_mapped_addr>='h2000)&&(z3_mapped_addr<'h8000) ) // this is marked in main.c as "FIXME remove"
  1791. m00_axi_awaddr_z3 <= (`RX_FRAME_ADDRESS - 32'h2000) + z3_mapped_addr;
  1792. else
  1793. m00_axi_awaddr_z3 <= `ARM_MEMORY_START + (z3_mapped_addr/*&32'hfffffffc*/); // max 256MB
  1794. m00_axi_wdata_z3 <= {z3_din_low_s2[7:0], z3_din_low_s2[15:8], z3_din_high_s2[7:0], z3_din_high_s2[15:8]};
  1795. m00_axi_awvalid_z3 <= 1;
  1796. if (m00_axi_awready) begin
  1797. zorro_state <= WAIT_WRITE_DMA_Z3B;
  1798. end
  1799. end
  1800. WAIT_WRITE_DMA_Z3B: begin
  1801. dtack <= 1;
  1802. m00_axi_awvalid_z3 <= 0;
  1803. m00_axi_wvalid_z3 <= 1;
  1804. if (m00_axi_wready) begin
  1805. zorro_state <= WAIT_WRITE_DMA_Z3C;
  1806. end
  1807. end
  1808. // not sure if this extra state is needed actually
  1809. WAIT_WRITE_DMA_Z3C: begin
  1810. m00_axi_wvalid_z3 <= 0;
  1811. zorro_state <= Z3_ENDCYCLE;
  1812. end
  1813. Z3_ENDCYCLE: begin
  1814. dtack <= 1;
  1815. // we're timing out or own dtack here. because of a zorro
  1816. // bug / subtlety, dtack can be sampled incorrectly to "hang over"
  1817. // into the next amiga zorro cycle.
  1818. // this is because we have a long rise time on our DTACK
  1819. // output/1k pullup.
  1820. read_counter <= read_counter + 1'b1;
  1821. if (read_counter >= dtack_timeout) begin
  1822. dtack <= 0;
  1823. end
  1824. if (z3_fcs_state==1) begin
  1825. dtack <= 0;
  1826. slaven <= 0;
  1827. dataout_z3 <= 0;
  1828. zorro_state <= Z3_IDLE;
  1829. end
  1830. end
  1831. `endif
  1832. // FIXME why is there no dataout time on REGREAD? (see memory reads)
  1833. // now fixed for Z3, still pending for Z2
  1834. REGREAD: begin
  1835. // TODO split up into z3/z2
  1836. `ifdef ZORRO3
  1837. zorro_state <= Z3_REGREAD_POST;
  1838. `else
  1839. zorro_state <= Z2_REGREAD_POST;
  1840. `endif
  1841. case (regread_addr&'hff)
  1842. /*'h00: begin
  1843. rr_data <= video_control_data;
  1844. end
  1845. 'h04: begin
  1846. rr_data <= video_control_op;
  1847. end*/
  1848. 'h00: begin
  1849. // this flag is read by Amiga software to check if all writes are done
  1850. rr_data <= video_control_vblank << 16; //zorro_ram_write_request;
  1851. end
  1852. default: begin
  1853. rr_data[31:16] <= REVISION;
  1854. rr_data[15:0] <= REVISION;
  1855. end
  1856. endcase
  1857. end
  1858. REGWRITE: begin
  1859. `ifdef ZORRO3
  1860. zorro_state <= Z3_ENDCYCLE;
  1861. `else
  1862. dtack <= 1;
  1863. zorro_state <= Z2_ENDCYCLE;
  1864. `endif
  1865. case (regwrite_addr&'hff)
  1866. 'h00: video_control_data_zorro[31:16] <= regdata_in[15:0];
  1867. 'h02: video_control_data_zorro[15:0] <= regdata_in[15:0];
  1868. 'h04: video_control_op_zorro[7:0] <= regdata_in[7:0]; // FIXME
  1869. 'h06: videocap_mode_in <= regdata_in[0];
  1870. //'h20: if (regdata_in[5:0]>0) dtack_timeout <= regdata_in[5:0];
  1871. //'h14: zorro_interrupt <= regdata_in[0];
  1872. //'h10: E7M_PSINCDEC <= regdata_in[0];
  1873. //'h12: E7M_PSEN <= regdata_in[0];
  1874. endcase
  1875. end
  1876. endcase
  1877. // PSEN reset
  1878. //if (E7M_PSEN==1'b1) E7M_PSEN <= 1'b0;
  1879. // ARM video control
  1880. if (axi_reg2[31]==1'b1) begin
  1881. video_control_data_axi <= axi_reg3[31:0];
  1882. video_control_op_axi <= axi_reg2[7:0];
  1883. video_control_axi <= 1;
  1884. end else
  1885. video_control_axi <= 0;
  1886. if (axi_reg2[30]==1'b1) begin
  1887. zorro_interrupt <= axi_reg2[0];
  1888. end
  1889. else if (clear_interrupt==1) begin
  1890. zorro_interrupt<=0;
  1891. clear_interrupt<=0;
  1892. end
  1893. // read / write request acknowledged by ARM
  1894. zorro_ram_read_flag <= axi_reg0[30];
  1895. zorro_ram_write_flag <= axi_reg0[31];
  1896. frfb <= axi_reg4;
  1897. usbb <= axi_reg5;
  1898. axi_reg0 <= slv_reg0;
  1899. axi_reg1 <= slv_reg1;
  1900. axi_reg2 <= slv_reg2;
  1901. axi_reg3 <= slv_reg3;
  1902. axi_reg4 <= slv_reg4;
  1903. axi_reg5 <= slv_reg5;
  1904. if (video_control_axi) begin
  1905. video_control_data <= video_control_data_axi;
  1906. video_control_op <= video_control_op_axi;
  1907. end else begin
  1908. video_control_data <= video_control_data_zorro;
  1909. video_control_op <= video_control_op_zorro;
  1910. end
  1911. video_control_data_out <= video_control_data;
  1912. video_control_op_out <= video_control_op;
  1913. video_control_vblank <= video_control_vblank_in;
  1914. video_control_interlace_out <= video_control_interlace;
  1915. // snoop the screen width for correct capture pitch
  1916. if (video_control_op == 2) begin
  1917. // OP_DIMENSIONS = 2
  1918. videocap_pitch_snoop <= video_control_data[11:0];
  1919. end
  1920. videocap_pitch <= videocap_pitch_snoop;
  1921. out_reg0 <= ZORRO3 ? last_z3addr : last_addr;
  1922. out_reg1 <= zorro_ram_write_data;
  1923. out_reg2 <= last_z3addr;
  1924. //out_reg3 <= {zorro_ram_write_request, zorro_ram_read_request, zorro_ram_write_bytes, ZORRO3,
  1925. // video_control_interlace, videocap_mode, 15'b0, zorro_state};
  1926. // `-- 24 `-- 23 `-- 22 `-- 7:0
  1927. out_reg3 <= {zorro_ram_write_request, zorro_ram_read_request, zorro_ram_write_bytes, ZORRO3,
  1928. video_control_interlace, videocap_mode, videocap_ntsc, video_control_vblank, 13'b0, zorro_state};
  1929. end
  1930. assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
  1931. always @(*)
  1932. begin
  1933. // Address decoding for reading registers
  1934. case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
  1935. 3'h0 : reg_data_out <= out_reg0;
  1936. 3'h1 : reg_data_out <= out_reg1;
  1937. 3'h2 : reg_data_out <= out_reg2;
  1938. 3'h3 : reg_data_out <= out_reg3;
  1939. default : reg_data_out <= 'h0;
  1940. endcase
  1941. end
  1942. endmodule