Firmware for MNT ZZ9000 graphics and ARM coprocessor card for Amiga computers.
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

mntzorro.v 66KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998
  1. `timescale 1 ns / 1 ps
  2. /*
  3. * MNT ZZ9000 Amiga Graphics and Coprocessor Card Firmware
  4. * Zorro 2/3 AXI4-Lite Interface, 24-bit Video Capture (AXI DMA)
  5. *
  6. * Copyright (C) 2019, Lukas F. Hartmann <lukas@mntre.com>
  7. * MNT Research GmbH, Berlin
  8. * https://mntre.com
  9. *
  10. * More Info: https://mntre.com/zz9000
  11. *
  12. * SPDX-License-Identifier: GPL-3.0-or-later
  13. * GNU General Public License v3.0 or later
  14. *
  15. * https://spdx.org/licenses/GPL-3.0-or-later.html
  16. *
  17. */
  18. // ZORRO2/3 switch
  19. //`define ZORRO2
  20. `define ZORRO3
  21. //`define VARIANT_ZZ9500
  22. `define C_S_AXI_DATA_WIDTH 32
  23. `define C_S_AXI_ADDR_WIDTH 4
  24. `define RAM_SIZE 32'h400000 // 4MB for Zorro 2
  25. `define REG_SIZE 32'h01000
  26. `define AUTOCONF_LOW 24'he80000
  27. `define AUTOCONF_HIGH 24'he80080
  28. `define Z3_RAM_SIZE 32'h10000000 // 256MB for Zorro 3
  29. `define ARM_MEMORY_START 32'h001f0000
  30. `define VIDEOCAP_ADDR 32'h01000000 // ARM_MEMORY_START+0xe0_0000
  31. `define C_M00_AXI_TARGET_SLAVE_BASE_ADDR 32'h10000000
  32. `define C_M00_AXI_ID_WIDTH 1
  33. `define C_M00_AXI_ADDR_WIDTH 32
  34. `define C_M00_AXI_DATA_WIDTH 32
  35. `define C_M00_AXI_AWUSER_WIDTH 0
  36. `define C_M00_AXI_ARUSER_WIDTH 0
  37. `define C_M00_AXI_WUSER_WIDTH 0
  38. `define C_M00_AXI_RUSER_WIDTH 0
  39. `define C_M00_AXI_BUSER_WIDTH 0
  40. module MNTZorro_v0_1_S00_AXI
  41. (
  42. inout wire [22:0] ZORRO_ADDR,
  43. inout wire [15:0] ZORRO_DATA,
  44. output wire ZORRO_INT6,
  45. output wire ZORRO_DATADIR,
  46. output wire ZORRO_ADDRDIR,
  47. output wire ZORRO_ADDRDIR2,
  48. output wire ZORRO_NBRN,
  49. input wire ZORRO_NBGN,
  50. input wire ZORRO_READ,
  51. //input wire ZORRO_NMTCR,
  52. input wire ZORRO_NUDS,
  53. input wire ZORRO_NLDS,
  54. input wire ZORRO_NDS1,
  55. input wire ZORRO_NDS0,
  56. input wire ZORRO_NCCS,
  57. input wire ZORRO_NFCS,
  58. input wire ZORRO_DOE,
  59. input wire ZORRO_NIORST,
  60. input wire ZORRO_NCFGIN,
  61. input wire ZORRO_E7M,
  62. input wire ZORRO_C28D,
  63. input wire VCAP_VSYNC,
  64. input wire VCAP_HSYNC,
  65. input wire VCAP_G0,
  66. input wire VCAP_G1,
  67. input wire VCAP_G2,
  68. input wire VCAP_G3,
  69. input wire VCAP_G4,
  70. input wire VCAP_G5,
  71. input wire VCAP_G6,
  72. input wire VCAP_G7,
  73. input wire VCAP_B7,
  74. input wire VCAP_B6,
  75. input wire VCAP_B5,
  76. input wire VCAP_B4,
  77. input wire VCAP_B3,
  78. input wire VCAP_B2,
  79. input wire VCAP_B1,
  80. input wire VCAP_B0,
  81. input wire VCAP_R7,
  82. input wire VCAP_R6,
  83. input wire VCAP_R5,
  84. input wire VCAP_R4,
  85. input wire VCAP_R3,
  86. input wire VCAP_R2,
  87. input wire VCAP_R1,
  88. input wire VCAP_R0,
  89. output wire ZORRO_NCFGOUT,
  90. output wire ZORRO_NSLAVE,
  91. output wire ZORRO_NCINH,
  92. output wire ZORRO_NDTACK,
  93. // HP master interface to write to PS memory directly
  94. input wire m00_axi_aclk,
  95. input wire m00_axi_aresetn,
  96. // write address channel
  97. input wire m00_axi_awready,
  98. //output reg [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_awid,
  99. output wire [`C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr,
  100. output reg [7:0] m00_axi_awlen,
  101. output reg [2:0] m00_axi_awsize,
  102. output reg [1:0] m00_axi_awburst,
  103. output reg m00_axi_awlock,
  104. output reg [3:0] m00_axi_awcache,
  105. output reg [2:0] m00_axi_awprot,
  106. output reg [3:0] m00_axi_awqos,
  107. output wire m00_axi_awvalid,
  108. // write channel
  109. input wire m00_axi_wready,
  110. //output reg [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_wid,
  111. output wire [`C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata,
  112. output wire [`C_M00_AXI_DATA_WIDTH/8-1 : 0] m00_axi_wstrb,
  113. output reg m00_axi_wlast,
  114. output wire m00_axi_wvalid,
  115. // buffered write response channel
  116. //input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_bid,
  117. input wire [1 : 0] m00_axi_bresp,
  118. input wire m00_axi_bvalid,
  119. output reg m00_axi_bready,
  120. // read address channel
  121. /*input wire m00_axi_arready,
  122. output reg [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_arid,
  123. output reg [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
  124. output reg [7 : 0] m00_axi_arlen,
  125. output reg [2 : 0] m00_axi_arsize,
  126. output reg [1 : 0] m00_axi_arburst,
  127. output reg m00_axi_arlock,
  128. output reg [3 : 0] m00_axi_arcache,
  129. output reg [2 : 0] m00_axi_arprot,
  130. output reg [3 : 0] m00_axi_arqos,
  131. output reg m00_axi_arvalid,
  132. output reg m00_axi_rready,
  133. input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_rid,
  134. input wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
  135. input wire [1 : 0] m00_axi_rresp,
  136. input wire m00_axi_rlast,
  137. input wire m00_axi_rvalid,*/
  138. // HP master interface 2 to write to PS memory directly (for videocap)
  139. input wire m01_axi_aclk,
  140. input wire m01_axi_aresetn,
  141. // write address channel
  142. input wire m01_axi_awready,
  143. output wire [`C_M00_AXI_ADDR_WIDTH-1 : 0] m01_axi_awaddr,
  144. output reg [7:0] m01_axi_awlen,
  145. output reg [2:0] m01_axi_awsize,
  146. output reg [1:0] m01_axi_awburst,
  147. output reg m01_axi_awlock,
  148. output reg [3:0] m01_axi_awcache,
  149. output reg [2:0] m01_axi_awprot,
  150. output reg [3:0] m01_axi_awqos,
  151. output wire m01_axi_awvalid,
  152. // write channel
  153. input wire m01_axi_wready,
  154. output wire [`C_M00_AXI_DATA_WIDTH-1 : 0] m01_axi_wdata,
  155. output wire [`C_M00_AXI_DATA_WIDTH/8-1 : 0] m01_axi_wstrb,
  156. output reg m01_axi_wlast,
  157. output wire m01_axi_wvalid,
  158. // buffered write response channel
  159. input wire [1 : 0] m01_axi_bresp,
  160. input wire m01_axi_bvalid,
  161. output reg m01_axi_bready,
  162. // video_formatter control interface
  163. output reg [31:0] video_control_data,
  164. output reg [7:0] video_control_op,
  165. output reg video_control_interlace,
  166. input wire video_control_vblank,
  167. // Xilinx AXI4-Lite implementation starts here ==============================
  168. // Global Clock Signal
  169. input wire S_AXI_ACLK,
  170. // Global Reset Signal. This Signal is Active LOW
  171. input wire S_AXI_ARESETN,
  172. // Write address (issued by master, acceped by Slave)
  173. input wire [`C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
  174. // Write channel Protection type. This signal indicates the
  175. // privilege and security level of the transaction, and whether
  176. // the transaction is a data access or an instruction access.
  177. input wire [2 : 0] S_AXI_AWPROT,
  178. // Write address valid. This signal indicates that the master signaling
  179. // valid write address and control information.
  180. input wire S_AXI_AWVALID,
  181. // Write address ready. This signal indicates that the slave is ready
  182. // to accept an address and associated control signals.
  183. output wire S_AXI_AWREADY,
  184. // Write data (issued by master, acceped by Slave)
  185. input wire [`C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
  186. // Write strobes. This signal indicates which byte lanes hold
  187. // valid data. There is one write strobe bit for each eight
  188. // bits of the write data bus.
  189. input wire [(`C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
  190. // Write valid. This signal indicates that valid write
  191. // data and strobes are available.
  192. input wire S_AXI_WVALID,
  193. // Write ready. This signal indicates that the slave
  194. // can accept the write data.
  195. output wire S_AXI_WREADY,
  196. // Write response. This signal indicates the status
  197. // of the write transaction.
  198. output wire [1 : 0] S_AXI_BRESP,
  199. // Write response valid. This signal indicates that the channel
  200. // is signaling a valid write response.
  201. output wire S_AXI_BVALID,
  202. // Response ready. This signal indicates that the master
  203. // can accept a write response.
  204. input wire S_AXI_BREADY,
  205. // Read address (issued by master, acceped by Slave)
  206. input wire [`C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
  207. // Protection type. This signal indicates the privilege
  208. // and security level of the transaction, and whether the
  209. // transaction is a data access or an instruction access.
  210. input wire [2 : 0] S_AXI_ARPROT,
  211. // Read address valid. This signal indicates that the channel
  212. // is signaling valid read address and control information.
  213. input wire S_AXI_ARVALID,
  214. // Read address ready. This signal indicates that the slave is
  215. // ready to accept an address and associated control signals.
  216. output wire S_AXI_ARREADY,
  217. // Read data (issued by slave)
  218. output wire [`C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
  219. // Read response. This signal indicates the status of the
  220. // read transfer.
  221. output wire [1 : 0] S_AXI_RRESP,
  222. // Read valid. This signal indicates that the channel is
  223. // signaling the required read data.
  224. output wire S_AXI_RVALID,
  225. // Read ready. This signal indicates that the master can
  226. // accept the read data and response information.
  227. input wire S_AXI_RREADY
  228. );
  229. // AXI4LITE signals
  230. reg [`C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
  231. reg axi_awready;
  232. reg axi_wready;
  233. reg [1 : 0] axi_bresp;
  234. reg axi_bvalid;
  235. reg [`C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
  236. reg axi_arready;
  237. reg [`C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
  238. reg [1 : 0] axi_rresp;
  239. reg axi_rvalid;
  240. // Example-specific design signals
  241. // local localparam for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
  242. // ADDR_LSB is used for addressing 32/64 bit registers/memories
  243. // ADDR_LSB = 2 for 32 bits (n downto 2)
  244. // ADDR_LSB = 3 for 64 bits (n downto 3)
  245. localparam integer ADDR_LSB = (`C_S_AXI_DATA_WIDTH/32) + 1;
  246. localparam integer OPT_MEM_ADDR_BITS = 1;
  247. //----------------------------------------------
  248. //-- Signals for user logic register space example
  249. //------------------------------------------------
  250. //-- Number of Slave Registers 4
  251. reg [`C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
  252. reg [`C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
  253. reg [`C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
  254. reg [`C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
  255. wire slv_reg_rden;
  256. wire slv_reg_wren;
  257. reg [`C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
  258. integer byte_index;
  259. reg aw_en;
  260. reg [`C_S_AXI_DATA_WIDTH-1:0] out_reg0;
  261. reg [`C_S_AXI_DATA_WIDTH-1:0] out_reg1;
  262. reg [`C_S_AXI_DATA_WIDTH-1:0] out_reg2;
  263. reg [`C_S_AXI_DATA_WIDTH-1:0] out_reg3;
  264. // I/O Connections assignments
  265. assign S_AXI_AWREADY = axi_awready;
  266. assign S_AXI_WREADY = axi_wready;
  267. assign S_AXI_BRESP = axi_bresp;
  268. assign S_AXI_BVALID = axi_bvalid;
  269. assign S_AXI_ARREADY = axi_arready;
  270. assign S_AXI_RDATA = axi_rdata;
  271. assign S_AXI_RRESP = axi_rresp;
  272. assign S_AXI_RVALID = axi_rvalid;
  273. // Implement axi_awready generation
  274. // axi_awready is asserted for one S_AXI_ACLK clock cycle when both
  275. // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
  276. // de-asserted when reset is low.
  277. always @( posedge S_AXI_ACLK )
  278. begin
  279. if ( S_AXI_ARESETN == 1'b0 )
  280. begin
  281. axi_awready <= 1'b0;
  282. aw_en <= 1'b1;
  283. end
  284. else
  285. begin
  286. if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
  287. begin
  288. // slave is ready to accept write address when
  289. // there is a valid write address and write data
  290. // on the write address and data bus. This design
  291. // expects no outstanding transactions.
  292. axi_awready <= 1'b1;
  293. aw_en <= 1'b0;
  294. end
  295. else if (S_AXI_BREADY && axi_bvalid)
  296. begin
  297. aw_en <= 1'b1;
  298. axi_awready <= 1'b0;
  299. end
  300. else
  301. begin
  302. axi_awready <= 1'b0;
  303. end
  304. end
  305. end
  306. // Implement axi_awaddr latching
  307. // This process is used to latch the address when both
  308. // S_AXI_AWVALID and S_AXI_WVALID are valid.
  309. always @( posedge S_AXI_ACLK )
  310. begin
  311. if ( S_AXI_ARESETN == 1'b0 )
  312. begin
  313. axi_awaddr <= 0;
  314. end
  315. else
  316. begin
  317. if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
  318. begin
  319. // Write Address latching
  320. axi_awaddr <= S_AXI_AWADDR;
  321. end
  322. end
  323. end
  324. // Implement axi_wready generation
  325. // axi_wready is asserted for one S_AXI_ACLK clock cycle when both
  326. // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
  327. // de-asserted when reset is low.
  328. always @( posedge S_AXI_ACLK )
  329. begin
  330. if ( S_AXI_ARESETN == 1'b0 )
  331. begin
  332. axi_wready <= 1'b0;
  333. end
  334. else
  335. begin
  336. if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
  337. begin
  338. // slave is ready to accept write data when
  339. // there is a valid write address and write data
  340. // on the write address and data bus. This design
  341. // expects no outstanding transactions.
  342. axi_wready <= 1'b1;
  343. end
  344. else
  345. begin
  346. axi_wready <= 1'b0;
  347. end
  348. end
  349. end
  350. // Implement memory mapped register select and write logic generation
  351. // The write data is accepted and written to memory mapped registers when
  352. // axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
  353. // select byte enables of slave registers while writing.
  354. // These registers are cleared when reset (active low) is applied.
  355. // Slave register write enable is asserted when valid address and data are available
  356. // and the slave is ready to accept the write address and write data.
  357. assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
  358. always @( posedge S_AXI_ACLK )
  359. begin
  360. if ( S_AXI_ARESETN == 1'b0 )
  361. begin
  362. slv_reg0 <= 0;
  363. slv_reg1 <= 0;
  364. slv_reg2 <= 0;
  365. slv_reg3 <= 0;
  366. end
  367. else begin
  368. if (slv_reg_wren)
  369. begin
  370. case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
  371. 2'h0:
  372. for ( byte_index = 0; byte_index <= (`C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
  373. if ( S_AXI_WSTRB[byte_index] == 1 ) begin
  374. // Respective byte enables are asserted as per write strobes
  375. // Slave register 0
  376. slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
  377. end
  378. 2'h1:
  379. for ( byte_index = 0; byte_index <= (`C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
  380. if ( S_AXI_WSTRB[byte_index] == 1 ) begin
  381. // Respective byte enables are asserted as per write strobes
  382. // Slave register 1
  383. slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
  384. end
  385. 2'h2:
  386. for ( byte_index = 0; byte_index <= (`C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
  387. if ( S_AXI_WSTRB[byte_index] == 1 ) begin
  388. // Respective byte enables are asserted as per write strobes
  389. // Slave register 2
  390. slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
  391. end
  392. 2'h3:
  393. for ( byte_index = 0; byte_index <= (`C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
  394. if ( S_AXI_WSTRB[byte_index] == 1 ) begin
  395. // Respective byte enables are asserted as per write strobes
  396. // Slave register 3
  397. slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
  398. end
  399. default : begin
  400. slv_reg0 <= slv_reg0;
  401. slv_reg1 <= slv_reg1;
  402. slv_reg2 <= slv_reg2;
  403. slv_reg3 <= slv_reg3;
  404. end
  405. endcase
  406. end
  407. end
  408. end
  409. // Implement write response logic generation
  410. // The write response and response valid signals are asserted by the slave
  411. // when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
  412. // This marks the acceptance of address and indicates the status of
  413. // write transaction.
  414. always @( posedge S_AXI_ACLK )
  415. begin
  416. if ( S_AXI_ARESETN == 1'b0 )
  417. begin
  418. axi_bvalid <= 0;
  419. axi_bresp <= 2'b0;
  420. end
  421. else
  422. begin
  423. if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
  424. begin
  425. // indicates a valid write response is available
  426. axi_bvalid <= 1'b1;
  427. axi_bresp <= 2'b0; // 'OKAY' response
  428. end // work error responses in future
  429. else
  430. begin
  431. if (S_AXI_BREADY && axi_bvalid)
  432. //check if bready is asserted while bvalid is high)
  433. //(there is a possibility that bready is always asserted high)
  434. begin
  435. axi_bvalid <= 1'b0;
  436. end
  437. end
  438. end
  439. end
  440. // Implement axi_arready generation
  441. // axi_arready is asserted for one S_AXI_ACLK clock cycle when
  442. // S_AXI_ARVALID is asserted. axi_awready is
  443. // de-asserted when reset (active low) is asserted.
  444. // The read address is also latched when S_AXI_ARVALID is
  445. // asserted. axi_araddr is reset to zero on reset assertion.
  446. always @( posedge S_AXI_ACLK )
  447. begin
  448. if ( S_AXI_ARESETN == 1'b0 )
  449. begin
  450. axi_arready <= 1'b0;
  451. axi_araddr <= 32'b0;
  452. end
  453. else
  454. begin
  455. if (~axi_arready && S_AXI_ARVALID)
  456. begin
  457. // indicates that the slave has acceped the valid read address
  458. axi_arready <= 1'b1;
  459. // Read address latching
  460. axi_araddr <= S_AXI_ARADDR;
  461. end
  462. else
  463. begin
  464. axi_arready <= 1'b0;
  465. end
  466. end
  467. end
  468. // Implement axi_arvalid generation
  469. // axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
  470. // S_AXI_ARVALID and axi_arready are asserted. The slave registers
  471. // data are available on the axi_rdata bus at this instance. The
  472. // assertion of axi_rvalid marks the validity of read data on the
  473. // bus and axi_rresp indicates the status of read transaction.axi_rvalid
  474. // is deasserted on reset (active low). axi_rresp and axi_rdata are
  475. // cleared to zero on reset (active low).
  476. always @( posedge S_AXI_ACLK )
  477. begin
  478. if ( S_AXI_ARESETN == 1'b0 )
  479. begin
  480. axi_rvalid <= 0;
  481. axi_rresp <= 0;
  482. end
  483. else
  484. begin
  485. if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
  486. begin
  487. // Valid read data is available at the read data bus
  488. axi_rvalid <= 1'b1;
  489. axi_rresp <= 2'b0; // 'OKAY' response
  490. end
  491. else if (axi_rvalid && S_AXI_RREADY)
  492. begin
  493. // Read data is accepted by the master
  494. axi_rvalid <= 1'b0;
  495. end
  496. end
  497. end
  498. // Output register or memory read data
  499. always @( posedge S_AXI_ACLK )
  500. begin
  501. if ( S_AXI_ARESETN == 1'b0 )
  502. begin
  503. axi_rdata <= 0;
  504. end
  505. else
  506. begin
  507. // When there is a valid read address (S_AXI_ARVALID) with
  508. // acceptance of read address by the slave (axi_arready),
  509. // output the read dada
  510. if (slv_reg_rden)
  511. begin
  512. axi_rdata <= reg_data_out; // register read data
  513. end
  514. end
  515. end
  516. // end of AXI-Lite interface ==================================================
  517. (* mark_debug = "true" *) reg [4:0] znAS_sync = 3'b11111;
  518. (* mark_debug = "true" *) reg [2:0] znUDS_sync = 3'b000;
  519. (* mark_debug = "true" *) reg [2:0] znLDS_sync = 3'b000;
  520. (* mark_debug = "true" *) reg [2:0] zREAD_sync = 3'b000;
  521. (* mark_debug = "true" *) reg [2:0] znFCS_sync = 3'b111;
  522. (* mark_debug = "true" *) reg [2:0] znDS1_sync = 3'b000;
  523. (* mark_debug = "true" *) reg [2:0] znDS0_sync = 3'b000;
  524. reg [1:0] znRST_sync = 2'b11;
  525. (* mark_debug = "true" *) reg [1:0] zDOE_sync = 2'b00;
  526. (* mark_debug = "true" *) reg [4:0] zE7M_sync = 5'b00000;
  527. reg [2:0] znCFGIN_sync = 3'b000;
  528. (* mark_debug = "true" *) reg [23:0] zaddr; // zorro 2 address
  529. (* mark_debug = "true" *) reg [23:0] zaddr_sync;
  530. (* mark_debug = "true" *) reg [23:0] zaddr_sync2;
  531. (* mark_debug = "true" *) reg [15:0] zdata_in_sync;
  532. (* mark_debug = "true" *) reg [15:0] zdata_in_sync2;
  533. (* mark_debug = "true" *) reg z2_addr_valid = 0;
  534. (* mark_debug = "true" *) reg [23:0] z2_mapped_addr;
  535. (* mark_debug = "true" *) reg z2_read = 0;
  536. (* mark_debug = "true" *) reg z2_write = 0;
  537. (* mark_debug = "true" *) reg z2_datastrobe_synced = 0;
  538. (* mark_debug = "true" *) reg z2addr_in_ram = 0;
  539. (* mark_debug = "true" *) reg z2addr_in_reg = 0;
  540. (* mark_debug = "true" *) reg z2addr_autoconfig = 0;
  541. (* mark_debug = "true" *) reg [31:0] ram_low = 32'h600000;
  542. (* mark_debug = "true" *) reg [31:0] ram_high = 32'ha00000;
  543. reg [31:0] reg_low = 32'h601000;
  544. reg [31:0] reg_high = 32'h602000;
  545. (* mark_debug = "true" *) reg z2_uds = 0;
  546. (* mark_debug = "true" *) reg z2_lds = 0;
  547. reg [31:0] z3_ram_low = 32'h50000000;
  548. reg [31:0] z3_ram_high = 32'h50000000 + `Z3_RAM_SIZE -4;
  549. reg [31:0] z3_reg_low = 32'h50001000;
  550. reg [31:0] z3_reg_high = 32'h50002000;
  551. reg [15:0] data_z3_hi16;
  552. reg [15:0] data_z3_low16;
  553. (* mark_debug = "true" *) reg [15:0] data_z3_hi16_latched;
  554. (* mark_debug = "true" *) reg [15:0] data_z3_low16_latched;
  555. reg [15:0] data_in_z3_low16;
  556. (* mark_debug = "true" *) reg [15:0] z3_din_high_s2;
  557. (* mark_debug = "true" *) reg [15:0] z3_din_low_s2;
  558. (* mark_debug = "true" *) reg [31:0] z3addr;
  559. (* mark_debug = "true" *) reg [31:0] last_z3addr;
  560. (* mark_debug = "true" *) reg [31:0] z3addr2;
  561. reg [31:0] z3addr3;
  562. (* mark_debug = "true" *) reg [31:0] z3_mapped_addr;
  563. (* mark_debug = "true" *) reg [31:0] z3_read_addr;
  564. (* mark_debug = "true" *) reg [15:0] z3_read_data;
  565. reg z3_din_latch = 0;
  566. (* mark_debug = "true" *) reg z3_fcs_state = 1;
  567. (* mark_debug = "true" *) reg z3_end_cycle = 0;
  568. (* mark_debug = "true" *) reg z3addr_in_ram = 0;
  569. (* mark_debug = "true" *) reg z3addr_in_reg = 0;
  570. (* mark_debug = "true" *) reg z3addr_autoconfig = 0;
  571. `ifdef ZORRO3
  572. reg ZORRO3 = 1;
  573. `else
  574. reg ZORRO3 = 0;
  575. `endif
  576. (* mark_debug = "true" *) reg dataout = 0;
  577. (* mark_debug = "true" *) reg dataout_z3 = 0;
  578. (* mark_debug = "true" *) reg dataout_enable = 0;
  579. (* mark_debug = "true" *) reg slaven = 0;
  580. (* mark_debug = "true" *) reg dtack = 0;
  581. reg dtack_latched = 0;
  582. reg z_reset = 0;
  583. reg z_cfgin = 0;
  584. reg z_cfgin_lo = 0;
  585. reg z3_confdone = 0;
  586. reg zorro_read = 0;
  587. reg zorro_write = 0;
  588. reg zorro_interrupt = 0;
  589. assign ZORRO_INT6 = zorro_interrupt;
  590. reg [15:0] data_in;
  591. reg [31:0] rr_data;
  592. reg [15:0] data_out;
  593. reg [15:0] regdata_in;
  594. // ram arbiter
  595. (* mark_debug = "true" *) reg zorro_ram_read_request = 0;
  596. (* mark_debug = "true" *) reg zorro_ram_write_request = 0;
  597. reg [31:0] zorro_ram_read_addr;
  598. reg [3:0] zorro_ram_read_bytes;
  599. reg [31:0] zorro_ram_write_addr;
  600. reg [31:0] zorro_ram_write_data;
  601. reg [3:0] zorro_ram_write_bytes;
  602. reg [15:0] default_data = 'hffff; // causes read/write glitches on A2000 (data bus interference) when 0
  603. reg [1:0] zorro_write_capture_bytes = 0;
  604. reg [15:0] zorro_write_capture_data = 0;
  605. // z3 strobes
  606. reg z3_ds3=0;
  607. reg z3_ds2=0;
  608. reg z3_ds1=0;
  609. reg z3_ds0=0;
  610. // level shifter direction pins
  611. assign ZORRO_DATADIR = ZORRO_DOE & (dataout_enable | dataout_z3); // d2-d9 d10-15, d0-d1
  612. assign ZORRO_ADDRDIR = ZORRO_DOE & (dataout_z3); // a16-a23 <- input a8-a15 <- input
  613. assign ZORRO_ADDRDIR2 = 0; //ZORRO_DOE & (dataout_z3_latched);
  614. assign ZORRO_NBRN = 1; // TODO busmastering
  615. // data/addr out signals are gated by master's DOE signal
  616. wire ZORRO_DATA_T = ~(ZORRO_DOE & (dataout_enable | dataout_z3));
  617. wire ZORRO_ADDR_T = ~(ZORRO_DOE & dataout_z3);
  618. reg z_ovr = 0;
  619. assign ZORRO_NCINH = z_ovr?1'b1:1'b0; // inverse
  620. // "slave" signals are gated by master's FCS signal
  621. assign ZORRO_NSLAVE = (ZORRO_DOE & slaven)?1'b0:1'b1; // cannot gate by FCS for Z2
  622. assign ZORRO_NDTACK = (ZORRO_DOE & dtack) ?1'b1:1'b0; // inverse, pull-down transistor on output
  623. wire [22:0] z3_addr_out = {data_z3_low16_latched, 7'bZZZ_ZZZZ}; // FIXME this creates tri-cell warning?
  624. //wire [22:0] z3_addr_out = {data_z3_low16_latched, 7'b111_1111}; // FIXME this creates tri-cell warning?
  625. wire [15:0] ZORRO_DATA_IN;
  626. wire [22:0] ZORRO_ADDR_IN;
  627. genvar i;
  628. generate
  629. for (i=0; i < 16; i=i+1) begin : ZORRO_DATABUS
  630. IOBUF u_iobuf_dq
  631. (
  632. .I (ZORRO3 ? data_z3_hi16_latched[i] : data_out[i]),
  633. .T (ZORRO_DATA_T),
  634. .IO (ZORRO_DATA[i]),
  635. .O (ZORRO_DATA_IN[i])
  636. );
  637. end
  638. endgenerate
  639. generate
  640. for (i=0; i < 23; i=i+1) begin : ZORRO_ADDRBUS
  641. IOBUF u_iobuf_dq
  642. (
  643. .I (z3_addr_out[i]),
  644. .T (ZORRO_ADDR_T),
  645. .IO (ZORRO_ADDR[i]),
  646. .O (ZORRO_ADDR_IN[i])
  647. );
  648. end
  649. endgenerate
  650. // autoconf output signal
  651. reg z_confout = 0;
  652. assign ZORRO_NCFGOUT = ZORRO_NCFGIN?1'b1:(~z_confout);
  653. reg [7:0] video_debug_reg;
  654. // -- synchronizers ------------------------------------------
  655. always @(posedge S_AXI_ACLK) begin
  656. znUDS_sync <= {znUDS_sync[1:0],ZORRO_NUDS};
  657. znLDS_sync <= {znLDS_sync[1:0],ZORRO_NLDS};
  658. znAS_sync <= {znAS_sync[3:0],ZORRO_NCCS};
  659. zREAD_sync <= {zREAD_sync[1:0],ZORRO_READ};
  660. znDS1_sync <= {znDS1_sync[1:0],ZORRO_NDS1};
  661. znDS0_sync <= {znDS0_sync[1:0],ZORRO_NDS0};
  662. znFCS_sync <= {znFCS_sync[1:0],ZORRO_NFCS};
  663. znCFGIN_sync<= {znCFGIN_sync[1:0],ZORRO_NCFGIN};
  664. zDOE_sync <= {zDOE_sync[0],ZORRO_DOE};
  665. znRST_sync <= {znRST_sync[0],ZORRO_NIORST};
  666. // Z2 ------------------------------------------------
  667. `ifndef ZORRO3
  668. // READ and nAS can happen dangerously close to each other. so we delay
  669. // the recognition of a valid Z2 cycle 2 clocks more than the other signals.
  670. z2_addr_valid <= (znAS_sync[4]==0 && znAS_sync[3]==0);
  671. zaddr <= ZORRO_ADDR_IN[22:0];
  672. zaddr_sync <= zaddr;
  673. zaddr_sync2 <= zaddr_sync;
  674. z2_mapped_addr <= {zaddr_sync2[22:0],1'b0};
  675. z2_read <= (zREAD_sync[2] == 1'b1); // FIXME was 0
  676. z2_write <= (zREAD_sync[2] == 1'b0); // FIXME was 0
  677. z2_datastrobe_synced <= ((znUDS_sync[2]==0 && znUDS_sync[1]==0) || (znLDS_sync[2]==0 && znLDS_sync[1]==0));
  678. z2_uds <= (znUDS_sync[2]==0 && znUDS_sync[1]==0);
  679. z2_lds <= (znLDS_sync[2]==0 && znLDS_sync[1]==0);
  680. z2addr_in_ram <= (z2_mapped_addr>=ram_low && z2_mapped_addr<ram_high);
  681. z2addr_in_reg <= (z2_mapped_addr>=reg_low && z2_mapped_addr<reg_high);
  682. // FIXME was 1
  683. if (znAS_sync[4]==0 && z2_mapped_addr>=`AUTOCONF_LOW && z2_mapped_addr<`AUTOCONF_HIGH)
  684. z2addr_autoconfig <= 1'b1;
  685. else
  686. z2addr_autoconfig <= 1'b0;
  687. `endif
  688. // Z3 ------------------------------------------------
  689. `ifdef ZORRO3
  690. z3addr2 <= {ZORRO_DATA_IN[15:8],ZORRO_ADDR_IN[22:1],2'b00};
  691. // sample z3addr on falling edge of /FCS
  692. // A4000 needs [0] here, [1] worked for A3000
  693. case (znFCS_sync[2:1])
  694. 2'b01: begin
  695. z3_fcs_state <= 1;
  696. z3addr <= 0;
  697. end
  698. 2'b10: begin
  699. // CHECK: if responding too quickly, this causes crashes
  700. z3_fcs_state <= 0;
  701. z3addr <= z3addr2;
  702. end
  703. endcase
  704. z3addr_in_ram <= (z3addr >= z3_ram_low) && (z3addr < z3_ram_high);
  705. z3addr_in_reg <= (z3addr >= z3_reg_low) && (z3addr < z3_reg_high);
  706. z3addr_autoconfig <= (z3addr[31:16]=='hff00);
  707. z3_mapped_addr <= (z3addr-z3_ram_low);
  708. data_in_z3_low16 <= ZORRO_ADDR_IN[22:7]; //zA[22:7]; // FIXME why sample this twice?
  709. if (znUDS_sync[1]==0 || znLDS_sync[1]==0 || znDS1_sync[1]==0 || znDS0_sync[1]==0)
  710. z3_din_latch <= 1;
  711. else
  712. z3_din_latch <= 0;
  713. // pipelined for better timing
  714. if (z3_din_latch) begin
  715. z3_din_high_s2 <= zdata_in_sync; //zD;
  716. z3_din_low_s2 <= data_in_z3_low16; //zA[22:7];
  717. end
  718. // pipelined for better timing
  719. data_z3_hi16_latched <= data_z3_hi16;
  720. data_z3_low16_latched <= data_z3_low16;
  721. `endif
  722. // FIXME shared by z2/z3 with high load, split up?
  723. zdata_in_sync2 <= ZORRO_DATA_IN;
  724. zdata_in_sync <= zdata_in_sync2;
  725. zorro_read <= zREAD_sync[2]; // FIXME was 0
  726. zorro_write <= ~zREAD_sync[2]; // FIXME was 0
  727. //dtack_latched <= dtack;
  728. z_reset <= (znRST_sync==2'b00);
  729. z_cfgin <= (znCFGIN_sync==3'b000);
  730. z_cfgin_lo <= (znCFGIN_sync==3'b111);
  731. //video_debug_reg <= video_debug;
  732. end // always @ (posedge S_AXI_ACLK)
  733. reg [15:0] REVISION = 'h7a09; // z9
  734. // main FSM
  735. localparam RESET = 0;
  736. localparam Z2_CONFIGURING = 1;
  737. localparam Z2_IDLE = 2;
  738. localparam WAIT_WRITE = 3;
  739. localparam WAIT_WRITE2 = 4;
  740. localparam Z2_WRITE_FINALIZE = 5;
  741. localparam WAIT_READ = 6;
  742. localparam WAIT_READ2 = 7;
  743. localparam WAIT_READ3 = 8;
  744. localparam CONFIGURED = 9;
  745. localparam CONFIGURED_CLEAR = 10;
  746. localparam DECIDE_Z2_Z3 = 11;
  747. localparam Z3_IDLE = 12;
  748. localparam Z3_WRITE_UPPER = 13;
  749. localparam Z3_WRITE_LOWER = 14;
  750. localparam Z3_READ_UPPER = 15;
  751. localparam Z3_READ_LOWER = 16;
  752. localparam Z3_READ_DELAY = 17;
  753. localparam Z3_READ_DELAY1 = 18;
  754. localparam Z3_READ_DELAY2 = 19;
  755. localparam Z3_WRITE_PRE = 20;
  756. localparam Z3_WRITE_FINALIZE = 21;
  757. localparam Z3_ENDCYCLE = 22;
  758. localparam Z3_DTACK = 23;
  759. localparam Z3_CONFIGURING = 24;
  760. localparam Z2_REGWRITE = 25;
  761. localparam REGWRITE = 26;
  762. localparam REGREAD = 27;
  763. localparam Z2_REGREAD_POST = 28;
  764. localparam Z3_REGREAD_POST = 29;
  765. localparam Z3_REGWRITE = 30;
  766. localparam Z2_REGREAD = 31;
  767. localparam Z3_REGREAD = 32;
  768. localparam Z2_PRE_CONFIGURED = 34;
  769. localparam Z2_ENDCYCLE = 35;
  770. localparam WAIT_WRITE_DMA_Z2 = 36;
  771. localparam WAIT_WRITE_DMA_Z2_FINALIZE = 37;
  772. localparam RESET_DVID = 39;
  773. localparam COLD = 40;
  774. localparam WAIT_READ2B = 41; // delay states
  775. localparam WAIT_READ2C = 42;
  776. localparam WAIT_READ2D = 54;
  777. localparam WAIT_WRITE_DMA_Z3 = 43;
  778. localparam WAIT_WRITE_DMA_Z3_FINALIZE = 44;
  779. localparam Z3_AUTOCONF_READ = 45;
  780. localparam Z3_AUTOCONF_WRITE = 46;
  781. localparam Z3_AUTOCONF_READ_DLY = 47;
  782. localparam Z3_AUTOCONF_READ_DLY2 = 48;
  783. localparam Z3_REGWRITE_PRE = 49;
  784. localparam Z3_REGREAD_PRE = 50;
  785. localparam Z3_WRITE_PRE2 = 51;
  786. localparam WAIT_WRITE_DMA_Z3B = 52;
  787. localparam WAIT_WRITE_DMA_Z3C = 53;
  788. (* mark_debug = "true" *) reg [7:0] zorro_state = COLD;
  789. reg zorro_idle = 0;
  790. (* mark_debug = "true" *) reg [7:0] read_counter = 0; // used by Z3
  791. reg [7:0] dataout_time = 'h02;
  792. reg [7:0] datain_time = 'h10;
  793. reg [7:0] datain_counter = 0;
  794. reg [23:0] last_addr = 0;
  795. reg [23:0] last_read_addr = 0;
  796. reg [15:0] last_data = 0;
  797. reg [15:0] last_read_data = 0;
  798. reg [15:0] zaddr_regpart = 0;
  799. reg [15:0] z3addr_regpart = 0;
  800. reg [15:0] regread_addr = 0;
  801. reg [15:0] regwrite_addr = 0;
  802. reg [31:0] axi_reg0 = 0;
  803. reg [31:0] axi_reg1 = 0;
  804. reg [31:0] axi_reg2 = 0;
  805. reg [31:0] axi_reg3 = 0;
  806. reg [31:0] video_control_data_zorro = 0;
  807. reg [7:0] video_control_op_zorro = 0;
  808. reg [31:0] video_control_data_axi = 0;
  809. reg [7:0] video_control_op_axi = 0;
  810. reg video_control_axi = 0;
  811. reg zorro_ram_read_flag = 0;
  812. reg zorro_ram_write_flag = 0;
  813. reg videocap_mode = 0;
  814. reg videocap_mode_in = 0;
  815. reg [6:0] videocap_hs = 0;
  816. reg [6:0] videocap_vs = 0;
  817. reg [2:0] videocap_state = 0;
  818. reg [23:0] videocap_rgbin = 0;
  819. reg [23:0] videocap_rgbin2 = 0;
  820. reg [9:0] videocap_x = 0;
  821. reg [9:0] videocap_x2 = 0;
  822. reg [9:0] videocap_y = 0;
  823. reg [9:0] videocap_y2 = 0;
  824. reg [9:0] videocap_y2_sync = 0;
  825. reg [9:0] videocap_ymax = 0;
  826. reg [9:0] videocap_ymax2 = 0;
  827. reg [9:0] videocap_ymax_sync = 0;
  828. reg [9:0] videocap_y3 = 0;
  829. reg [9:0] videocap_voffset = 'h1a;
  830. reg [9:0] videocap_prex = 'h5e; // 3f
  831. reg [9:0] videocap_prex_sync = 'h5e;
  832. reg [9:0] videocap_height = 'h200;
  833. parameter VCAPW = 799;
  834. reg [31:0] videocap_buf [0:VCAPW];
  835. reg videocap_lace_field=0;
  836. reg videocap_interlace=0;
  837. reg videocap_ntsc=0;
  838. reg [9:0] videocap_voffset2=0;
  839. reg E7M_PSEN = 0;
  840. reg E7M_PSINCDEC = 0;
  841. wire clkfbout_zz9000_ps_clk_wiz_1_0;
  842. wire e7m_shifted;
  843. wire e7m_shifted180;
  844. // video capture clock adjustment
  845. MMCME2_ADV #(
  846. .BANDWIDTH("OPTIMIZED"),
  847. .CLKFBOUT_MULT_F(32.000000),
  848. .CLKFBOUT_PHASE(0.000000),
  849. .CLKFBOUT_USE_FINE_PS("TRUE"),
  850. .CLKIN1_PERIOD(35.000000),
  851. .CLKIN2_PERIOD(0.000000),
  852. .CLKOUT0_DIVIDE_F(16.000000),
  853. .CLKOUT0_DUTY_CYCLE(0.500000),
  854. `ifdef ZORRO3
  855. .CLKOUT0_PHASE(0.000000),
  856. `elsif VARIANT_ZZ9500
  857. .CLKOUT0_PHASE(90.000000),
  858. `else
  859. .CLKOUT0_PHASE(315.000000),
  860. `endif
  861. .CLKOUT0_USE_FINE_PS("TRUE"),
  862. .CLKOUT1_DIVIDE(32),
  863. .CLKOUT1_DUTY_CYCLE(0.500000),
  864. `ifdef ZORRO3
  865. .CLKOUT1_PHASE(0.000000),
  866. `elsif VARIANT_ZZ9500
  867. .CLKOUT1_PHASE(270.000000),
  868. `else
  869. .CLKOUT1_PHASE(135.000000),
  870. `endif
  871. .CLKOUT1_USE_FINE_PS("TRUE"),
  872. .COMPENSATION("ZHOLD"),
  873. .DIVCLK_DIVIDE(1),
  874. .IS_CLKINSEL_INVERTED(1'b0),
  875. .IS_PSEN_INVERTED(1'b0),
  876. .IS_PSINCDEC_INVERTED(1'b0),
  877. .IS_PWRDWN_INVERTED(1'b0),
  878. .IS_RST_INVERTED(1'b0),
  879. .REF_JITTER1(0.001000),
  880. .REF_JITTER2(0.001000),
  881. .SS_EN("FALSE"),
  882. .SS_MODE("CENTER_HIGH"),
  883. .SS_MOD_PERIOD(10000),
  884. .STARTUP_WAIT("FALSE"))
  885. mmcm_adv_inst
  886. (.CLKFBIN(clkfbout_zz9000_ps_clk_wiz_1_0),
  887. .CLKFBOUT(clkfbout_zz9000_ps_clk_wiz_1_0),
  888. //.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
  889. //.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
  890. .CLKIN1(ZORRO_E7M),
  891. .CLKIN2(1'b0),
  892. .CLKINSEL(1'b1),
  893. //.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
  894. .CLKOUT0(e7m_shifted),
  895. //.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
  896. .CLKOUT1(e7m_shifted180),
  897. //.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
  898. .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
  899. .DCLK(1'b0),
  900. .DEN(1'b0),
  901. .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
  902. //.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
  903. //.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
  904. .DWE(1'b0),
  905. //.LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED),
  906. .PSCLK(S_AXI_ACLK),
  907. //.PSDONE(psdone),
  908. .PSEN(E7M_PSEN),
  909. .PSINCDEC(E7M_PSINCDEC),
  910. .PWRDWN(1'b0),
  911. .RST(1'b0));
  912. always @(posedge e7m_shifted) begin
  913. videocap_vs <= {videocap_vs[5:0], VCAP_VSYNC};
  914. `ifdef VARIANT_ZZ9500
  915. videocap_hs <= {videocap_hs[5:0], VCAP_B4}; // FIXME
  916. `else
  917. videocap_hs <= {videocap_hs[5:0], VCAP_HSYNC};
  918. `endif
  919. videocap_prex_sync <= videocap_prex;
  920. `ifdef VARIANT_ZZ9500
  921. videocap_rgbin <= {VCAP_R3,VCAP_R2,VCAP_R1,VCAP_R0,VCAP_R3,VCAP_R2,VCAP_R1,VCAP_R0,
  922. VCAP_G3,VCAP_G2,VCAP_G1,VCAP_G0,VCAP_G3,VCAP_G2,VCAP_G1,VCAP_G0,
  923. VCAP_B3,VCAP_B2,VCAP_B1,VCAP_B0,VCAP_B3,VCAP_B2,VCAP_B1,VCAP_B0};
  924. `elsif ZORRO2
  925. videocap_rgbin <= {VCAP_R7,VCAP_R6,VCAP_R5,VCAP_R4,VCAP_R7,VCAP_R6,VCAP_R5,VCAP_R4,
  926. VCAP_G7,VCAP_G6,VCAP_G5,VCAP_G4,VCAP_G7,VCAP_G6,VCAP_G5,VCAP_G4,
  927. VCAP_B7,VCAP_B6,VCAP_B5,VCAP_B4,VCAP_B7,VCAP_B6,VCAP_B5,VCAP_B4};
  928. `else
  929. videocap_rgbin <= {VCAP_R7,VCAP_R6,VCAP_R5,VCAP_R4,VCAP_R3,VCAP_R2,VCAP_R1,VCAP_R0,
  930. VCAP_G7,VCAP_G6,VCAP_G5,VCAP_G4,VCAP_G3,VCAP_G2,VCAP_G1,VCAP_G0,
  931. VCAP_B7,VCAP_B6,VCAP_B5,VCAP_B4,VCAP_B3,VCAP_B2,VCAP_B1,VCAP_B0};
  932. `endif
  933. if (videocap_vs[6:1]=='b111000) begin
  934. if (videocap_ymax[0]!=videocap_ymax2[0])
  935. videocap_interlace <= 1;
  936. else
  937. videocap_interlace <= 0;
  938. if (videocap_ymax>='h138)
  939. videocap_ntsc <= 0;
  940. else
  941. videocap_ntsc <= 1;
  942. videocap_lace_field <= videocap_ymax[0];
  943. if (videocap_interlace) begin
  944. videocap_y2 <= videocap_lace_field;
  945. videocap_voffset2 <= videocap_voffset<<1;
  946. end else begin
  947. videocap_y2 <= 0;
  948. videocap_voffset2 <= videocap_voffset;
  949. end
  950. videocap_ymax <= videocap_y3;
  951. videocap_ymax2 <= videocap_ymax;
  952. videocap_y3 <= 0;
  953. end else if (videocap_hs[6:1]=='b000111) begin
  954. videocap_x <= 0;
  955. if (videocap_interlace)
  956. videocap_y2 <= videocap_y2 + 2'b10;
  957. else
  958. videocap_y2 <= videocap_y2 + 1'b1;
  959. videocap_y3 <= videocap_y3 + 1'b1;
  960. end else if (videocap_x<(VCAPW+videocap_prex_sync)) begin
  961. videocap_x <= videocap_x + 1'b1;
  962. if (videocap_prex_sync<=videocap_x)
  963. videocap_buf[videocap_x-videocap_prex_sync] <= videocap_rgbin;
  964. end
  965. end
  966. reg [11:0] videocap_save_x=0;
  967. reg [11:0] videocap_save_x2=0;
  968. reg [11:0] videocap_save_x3=0;
  969. reg [11:0] videocap_yoffset=0;
  970. reg [11:0] videocap_xoffset=0;
  971. reg [11:0] videocap_pitch=720;
  972. reg [9:0] videocap_save_line_done=1;
  973. reg [11:0] videocap_save_y=0;
  974. reg [31:0] videocap_save_y2=0;
  975. reg [31:0] videocap_save_addr=0;
  976. reg [3:0] videocap_save_state=3; // FIXME
  977. reg videocap_mode_sync;
  978. reg [31:0] m01_axi_awaddr_out;
  979. reg [31:0] m01_axi_wdata_out;
  980. reg m01_axi_awvalid_out = 0;
  981. reg m01_axi_wvalid_out = 0;
  982. (* mark_debug = "true" *) reg [31:0] m00_axi_awaddr_z3;
  983. (* mark_debug = "true" *) reg [31:0] m00_axi_wdata_z3;
  984. (* mark_debug = "true" *) reg m00_axi_awvalid_z3 = 0;
  985. (* mark_debug = "true" *) reg m00_axi_wvalid_z3 = 0;
  986. (* mark_debug = "true" *) reg [3:0] m00_axi_wstrb_z3;
  987. reg z3_axi_write = 0;
  988. assign m00_axi_awaddr = m00_axi_awaddr_z3;
  989. assign m00_axi_awvalid = m00_axi_awvalid_z3;
  990. assign m00_axi_wdata = m00_axi_wdata_z3;
  991. assign m00_axi_wstrb = m00_axi_wstrb_z3;
  992. assign m00_axi_wvalid = m00_axi_wvalid_z3;
  993. assign m01_axi_awaddr = m01_axi_awaddr_out;
  994. assign m01_axi_awvalid = m01_axi_awvalid_out;
  995. assign m01_axi_wdata = m01_axi_wdata_out;
  996. assign m01_axi_wstrb = 4'b1111;
  997. assign m01_axi_wvalid = m01_axi_wvalid_out;
  998. // FIXME i think this process can be dissolved
  999. // AXI DMA arbiter
  1000. always @(posedge S_AXI_ACLK) begin
  1001. m00_axi_awlen <= 'h0; // 1 burst (1 write)
  1002. m00_axi_awsize <= 'h2; // 2^2 == 4 bytes
  1003. m00_axi_awburst <= 'h0; // FIXED (non incrementing)
  1004. m00_axi_awcache <= 'h3;
  1005. m00_axi_awlock <= 'h0;
  1006. m00_axi_awprot <= 'h0;
  1007. m00_axi_awqos <= 'h0;
  1008. m00_axi_wlast <= 'h1;
  1009. m00_axi_bready <= 'h1;
  1010. // FIXME this could use bursts
  1011. m01_axi_awlen <= 'h0; // 1 burst (1 write)
  1012. m01_axi_awsize <= 'h2; //'h2; // 2^2 == 4 bytes
  1013. m01_axi_awburst <= 'h0; // FIXED (non incrementing)
  1014. m01_axi_awcache <= 'h0;
  1015. m01_axi_awlock <= 'h0;
  1016. m01_axi_awprot <= 'h0;
  1017. m01_axi_awqos <= 'h0;
  1018. m01_axi_wlast <= 'h1;
  1019. m01_axi_bready <= 'h1;
  1020. end
  1021. reg [9:0] videocap_x_sync;
  1022. reg [9:0] vc_saving_line;
  1023. always @(posedge S_AXI_ACLK) begin
  1024. // VIDEOCAP
  1025. // pass interlace mode to video control block
  1026. video_control_interlace <= videocap_interlace;
  1027. videocap_x_sync <= videocap_x;
  1028. videocap_mode_sync <= videocap_mode;
  1029. videocap_y2_sync <= videocap_y2-videocap_voffset2;
  1030. videocap_save_x2 <= videocap_save_x;
  1031. if (m01_axi_aresetn == 0) begin
  1032. videocap_save_state <= 3;
  1033. m01_axi_wvalid_out <= 0;
  1034. m01_axi_awvalid_out <= 0;
  1035. end else begin
  1036. // we shift left by 2 bits to scale from 1 pixel to 4 bytes
  1037. m01_axi_awaddr_out <= `VIDEOCAP_ADDR+((vc_saving_line*videocap_pitch+videocap_save_x)<<2);
  1038. m01_axi_wdata_out <= videocap_buf[videocap_save_x];
  1039. if (videocap_save_line_done!=videocap_y2_sync && videocap_x_sync > 0) begin
  1040. vc_saving_line <= videocap_y2_sync;
  1041. end
  1042. if (videocap_save_state == 0) begin
  1043. // initial state
  1044. if (m01_axi_awready) begin
  1045. videocap_save_state <= 2;
  1046. end
  1047. end else if (videocap_save_state == 1) begin
  1048. m01_axi_awvalid_out <= 0;
  1049. m01_axi_wvalid_out <= 1;
  1050. if (m01_axi_wready) begin
  1051. if (videocap_save_x >= videocap_pitch) begin
  1052. videocap_save_line_done <= vc_saving_line;
  1053. videocap_save_x <= 0;
  1054. end else if (videocap_save_line_done != vc_saving_line)
  1055. videocap_save_x <= videocap_save_x + 1'b1;
  1056. videocap_save_state <= 2;
  1057. end
  1058. end else if (videocap_save_state == 2) begin
  1059. m01_axi_awvalid_out <= 1;
  1060. m01_axi_wvalid_out <= 0;
  1061. if (m01_axi_awready) begin
  1062. if (videocap_mode_sync)
  1063. videocap_save_state <= 1;
  1064. else
  1065. videocap_save_state <= 3;
  1066. end
  1067. end else if (videocap_save_state == 3) begin
  1068. // videocap is disabled, lets wait here
  1069. if (videocap_mode_sync)
  1070. videocap_save_state <= 0;
  1071. m01_axi_wvalid_out <= 0;
  1072. m01_axi_awvalid_out <= 0;
  1073. end
  1074. end
  1075. end
  1076. // -- main zorro fsm ---------------------------------------------
  1077. always @(posedge S_AXI_ACLK) begin
  1078. zorro_idle <= ((zorro_state==Z2_IDLE)||(zorro_state==Z3_IDLE));
  1079. videocap_mode <= videocap_mode_in;
  1080. if (/*z_cfgin_lo ||*/ z_reset) begin
  1081. zorro_state <= RESET;
  1082. end else
  1083. case (zorro_state)
  1084. COLD: begin
  1085. zorro_state <= RESET;
  1086. end
  1087. RESET: begin
  1088. dataout_enable <= 0;
  1089. dataout <= 0;
  1090. dataout_z3 <= 0;
  1091. slaven <= 0;
  1092. z_ovr <= 0;
  1093. z_confout <= 0;
  1094. z3_confdone <= 0;
  1095. zorro_ram_read_request <= 0;
  1096. zorro_ram_write_request <= 0;
  1097. zorro_interrupt <= 0;
  1098. video_control_data_zorro <= 0;
  1099. video_control_op_zorro <= 0;
  1100. video_control_data_axi <= 0;
  1101. video_control_op_axi <= 0;
  1102. if (!z_reset)
  1103. zorro_state <= DECIDE_Z2_Z3;
  1104. //count_writes <= 0;
  1105. //videocap_mode_in <= 0;
  1106. //last_z3addr <= 0;
  1107. // RESET video controller
  1108. //video_control_op <= 11;
  1109. end
  1110. DECIDE_Z2_Z3: begin
  1111. //video_control_op <= 0;
  1112. `ifdef ZORRO2
  1113. if (z2addr_autoconfig) begin
  1114. //ZORRO3 <= 0;
  1115. zorro_state <= Z2_CONFIGURING;
  1116. end
  1117. `endif
  1118. `ifdef ZORRO3
  1119. if (z3addr_autoconfig) begin
  1120. //ZORRO3 <= 1;
  1121. zorro_state <= Z3_CONFIGURING;
  1122. end
  1123. `endif
  1124. end
  1125. `ifdef ZORRO3
  1126. Z3_AUTOCONF_READ_DLY: begin
  1127. // wait for data to be latched out
  1128. zorro_state <= Z3_AUTOCONF_READ_DLY2;
  1129. end
  1130. Z3_AUTOCONF_READ_DLY2: begin
  1131. // wait for data to be latched out
  1132. zorro_state <= Z3_DTACK;
  1133. end
  1134. Z3_AUTOCONF_READ: begin
  1135. dataout_z3 <= 1;
  1136. slaven <= 1;
  1137. zorro_state <= Z3_AUTOCONF_READ_DLY;
  1138. last_z3addr <= z3addr;
  1139. case (z3addr[15:0])
  1140. 'h0000: data_z3_hi16 <= 'b1000_1111_1111_1111; // zorro 3 (10), no pool link (0), autoboot ROM (1)
  1141. 'h0100: data_z3_hi16 <= 'b0100_1111_1111_1111; // next board unrelated (0), 256MB
  1142. 'h0004: data_z3_hi16 <= 'b1111_1111_1111_1111; // product number
  1143. 'h0104: data_z3_hi16 <= 'b1011_1111_1111_1111; // (4)
  1144. 'h0008: data_z3_hi16 <= 'b0000_1111_1111_1111; // flags inverted 0111 io,shutup,extension,reserved(1)
  1145. 'h0108: data_z3_hi16 <= 'b1111_1111_1111_1111; // inverted zero
  1146. 'h000c: data_z3_hi16 <= 'b1111_1111_1111_1111; // reserved?
  1147. 'h010c: data_z3_hi16 <= 'b1111_1111_1111_1111; //
  1148. 'h0010: data_z3_hi16 <= 'b1001_1111_1111_1111; // manufacturer high byte inverted
  1149. 'h0110: data_z3_hi16 <= 'b0010_1111_1111_1111; //
  1150. 'h0014: data_z3_hi16 <= 'b1001_1111_1111_1111; // manufacturer low byte
  1151. 'h0114: data_z3_hi16 <= 'b0001_1111_1111_1111;
  1152. 'h0018: data_z3_hi16 <= 'b1111_1111_1111_1111; // serial 01 01 01 01
  1153. 'h0118: data_z3_hi16 <= 'b1110_1111_1111_1111; //
  1154. 'h001c: data_z3_hi16 <= 'b1111_1111_1111_1111; //
  1155. 'h011c: data_z3_hi16 <= 'b1110_1111_1111_1111; //
  1156. 'h0020: data_z3_hi16 <= 'b1111_1111_1111_1111; //
  1157. 'h0120: data_z3_hi16 <= 'b1110_1111_1111_1111; //
  1158. 'h0024: data_z3_hi16 <= 'b1111_1111_1111_1111; //
  1159. 'h0124: data_z3_hi16 <= 'b1110_1111_1111_1111; //
  1160. /*'h0028: data_z3_hi16 <= 'b1111_1111_1111_1111; // autoboot rom vector (er_InitDiagVec)
  1161. 'h0128: data_z3_hi16 <= 'b1111_1111_1111_1111; // ff7f = ~0080
  1162. 'h002c: data_z3_hi16 <= 'b0111_1111_1111_1111;
  1163. 'h012c: data_z3_hi16 <= 'b1111_1111_1111_1111;*/
  1164. default: data_z3_hi16 <= 'b1111_1111_1111_1110; // FIXME
  1165. endcase
  1166. end
  1167. Z3_AUTOCONF_WRITE: begin
  1168. slaven <= 1;
  1169. // was [2] for A3000
  1170. if (z3_din_latch) begin
  1171. zorro_state <= Z3_DTACK;
  1172. casex (z3addr[15:0])
  1173. 'hXX44: begin
  1174. z3_ram_low[31:16] <= zdata_in_sync;
  1175. z_confout <= 1;
  1176. z3_confdone <= 1;
  1177. end
  1178. 'hXX48: begin
  1179. end
  1180. 'hXX4c: begin
  1181. // shutup
  1182. z_confout <= 1;
  1183. z3_confdone <= 1;
  1184. end
  1185. endcase
  1186. end
  1187. end
  1188. Z3_CONFIGURING: begin
  1189. // FIXME why?
  1190. //data_z3_low16 <= 'hffff;
  1191. // was [2] for A3000
  1192. if (z_cfgin && z3addr_autoconfig) begin
  1193. if (zorro_read) begin
  1194. // autoconfig ROM
  1195. zorro_state <= Z3_AUTOCONF_READ;
  1196. end else begin
  1197. // write to autoconfig register
  1198. zorro_state <= Z3_AUTOCONF_WRITE;
  1199. end
  1200. end
  1201. dataout_z3 <= 0;
  1202. slaven <= 0;
  1203. dtack <= 0;
  1204. end
  1205. Z3_DTACK: begin
  1206. if (z3_fcs_state == 1) begin
  1207. dtack <= 0;
  1208. dataout_z3 <= 0;
  1209. slaven <= 0;
  1210. if (z3_confdone) begin
  1211. zorro_state <= CONFIGURED;
  1212. end else
  1213. zorro_state <= Z3_CONFIGURING;
  1214. end else
  1215. dtack <= 1;
  1216. end
  1217. `endif
  1218. CONFIGURED: begin
  1219. ram_high <= ram_low + `RAM_SIZE;
  1220. reg_low <= ram_low + 'h1000;
  1221. reg_high <= ram_low + 'h2000;
  1222. z3_ram_high <= z3_ram_low + `Z3_RAM_SIZE;
  1223. z3_reg_low <= z3_ram_low + 'h1000;
  1224. z3_reg_high <= z3_ram_low + 'h2000;
  1225. zorro_state <= CONFIGURED_CLEAR;
  1226. end
  1227. CONFIGURED_CLEAR: begin
  1228. // this is a fix for the "pixel swap" bug: if AXI HP is getting writes too early,
  1229. // it would sometimes (~10% of cold starts) get confused and swap pairs of writes.
  1230. videocap_mode_in <= 1;
  1231. `ifdef ZORRO3
  1232. zorro_state <= Z3_IDLE;
  1233. `else
  1234. zorro_state <= Z2_IDLE;
  1235. `endif
  1236. end
  1237. // ---------------------------------------------------------------------------------
  1238. `ifdef ZORRO2
  1239. Z2_CONFIGURING: begin
  1240. z_ovr <= 0;
  1241. if (z2_addr_valid && z2addr_autoconfig && z_cfgin) begin
  1242. if (z2_read) begin
  1243. // read iospace 'he80000 (Autoconfig ROM)
  1244. dataout_enable <= 1;
  1245. dataout <= 1;
  1246. slaven <= 1;
  1247. case (z2_mapped_addr[7:0])
  1248. 8'h00: data_out <= 'b1101_1111_1111_1111; // zorro 2 (11), no pool (0) rom (1)
  1249. 8'h02: data_out <= 'b0111_1111_1111_1111; // next board unrelated (0), 4mb (110 for 2mb)
  1250. 8'h04: data_out <= 'b1111_1111_1111_1111; // product number
  1251. 8'h06: data_out <= 'b1100_1111_1111_1111; // (3)
  1252. 8'h08: data_out <= 'b0011_1111_1111_1111; // flags inverted 0011
  1253. 8'h0a: data_out <= 'b1110_1111_1111_1111; // inverted 0001 = OS sized
  1254. 8'h10: data_out <= 'b1001_1111_1111_1111; // manufacturer high byte inverted (02)
  1255. 8'h12: data_out <= 'b0010_1111_1111_1111; //
  1256. 8'h14: data_out <= 'b1001_1111_1111_1111; // manufacturer low byte (9a)
  1257. 8'h16: data_out <= 'b0001_1111_1111_1111;
  1258. 8'h18: data_out <= 'b1111_1111_1111_1111; // serial 01 01 01 01
  1259. 8'h1a: data_out <= 'b1110_1111_1111_1111; //
  1260. 8'h1c: data_out <= 'b1111_1111_1111_1111; //
  1261. 8'h1e: data_out <= 'b1110_1111_1111_1111; //
  1262. 8'h20: data_out <= 'b1111_1111_1111_1111; //
  1263. 8'h22: data_out <= 'b1110_1111_1111_1111; //
  1264. 8'h24: data_out <= 'b1111_1111_1111_1111; //
  1265. 8'h26: data_out <= 'b1110_1111_1111_1111; //
  1266. /*8'h28: data_out <= 'b1111_1111_1111_1111; // autoboot rom vector (er_InitDiagVec)
  1267. 8'h2a: data_out <= 'b1111_1111_1111_1111; // ff7f = ~0080
  1268. 8'h2c: data_out <= 'b0111_1111_1111_1111;
  1269. 8'h2e: data_out <= 'b1111_1111_1111_1111;*/
  1270. //'h000040: data <= 'b0000_0000_0000_0000; // interrupts (not inverted)
  1271. //'h000042: data <= 'b0000_0000_0000_0000; //
  1272. default: data_out <= 'b1111_1111_1111_1111;
  1273. endcase
  1274. end else begin
  1275. // write to autoconfig register
  1276. if (z2_datastrobe_synced) begin
  1277. case (z2_mapped_addr[7:0])
  1278. 8'h48: begin
  1279. ram_low[31:24] <= 8'h0;
  1280. ram_low[23:20] <= zdata_in_sync[15:12];
  1281. ram_low[15:0] <= 16'h0;
  1282. zorro_state <= Z2_PRE_CONFIGURED; // configured
  1283. end
  1284. 8'h4a: begin
  1285. ram_low[31:24] <= 8'h0;
  1286. ram_low[19:16] <= zdata_in_sync[15:12];
  1287. ram_low[15:0] <= 16'h0;
  1288. end
  1289. 8'h4c: begin
  1290. zorro_state <= Z2_PRE_CONFIGURED; // configured, shut up
  1291. end
  1292. endcase
  1293. end
  1294. end
  1295. end else begin
  1296. // no address match
  1297. dataout <= 0;
  1298. dataout_enable <= 0;
  1299. slaven <= 0;
  1300. end
  1301. end
  1302. Z2_PRE_CONFIGURED: begin
  1303. if (!z2_addr_valid) begin
  1304. z_confout<=1;
  1305. zorro_state <= CONFIGURED;
  1306. end
  1307. end
  1308. Z2_IDLE: begin
  1309. if (z2_addr_valid) begin
  1310. if (z2_write && z2addr_in_reg) begin
  1311. // write to register
  1312. dataout_enable <= 0;
  1313. dataout <= 0;
  1314. slaven <= 1;
  1315. z_ovr <= 1;
  1316. zaddr_regpart <= z2_mapped_addr;
  1317. zorro_state <= Z2_REGWRITE;
  1318. end else if (z2_read && z2addr_in_reg) begin
  1319. // read from registers
  1320. dataout_enable <= 1;
  1321. dataout <= 1;
  1322. data_out <= default_data; //'hffff;
  1323. slaven <= 1;
  1324. z_ovr <= 1;
  1325. zaddr_regpart <= z2_mapped_addr;
  1326. zorro_state <= Z2_REGREAD;
  1327. end else if (z2_read && z2addr_in_ram) begin
  1328. // read RAM
  1329. // request ram access from arbiter
  1330. last_addr <= z2_mapped_addr-ram_low; // differently done in z3
  1331. data_out <= default_data; //'hffff;
  1332. dataout_enable <= 1;
  1333. dataout <= 1;
  1334. slaven <= 1;
  1335. z_ovr <= 1;
  1336. zorro_state <= WAIT_READ3;
  1337. end else if (z2_write && z2addr_in_ram) begin
  1338. // write RAM
  1339. last_addr <= z2_mapped_addr-ram_low;
  1340. dataout_enable <= 0;
  1341. dataout <= 0;
  1342. datain_counter <= 0;
  1343. slaven <= 1;
  1344. z_ovr <= 1;
  1345. //count_writes <= count_writes + 1;
  1346. zorro_state <= WAIT_WRITE;
  1347. end else begin
  1348. dataout <= 0;
  1349. dataout_enable <= 0;
  1350. slaven <= 0;
  1351. end
  1352. end else begin
  1353. dataout <= 0;
  1354. dataout_enable <= 0;
  1355. slaven <= 0;
  1356. end
  1357. end
  1358. Z2_REGWRITE: begin
  1359. if (z2_datastrobe_synced) begin
  1360. regdata_in <= zdata_in_sync;
  1361. regwrite_addr <= zaddr_regpart;
  1362. zorro_state <= REGWRITE;
  1363. end
  1364. end
  1365. WAIT_READ3: begin
  1366. zorro_ram_read_addr <= last_addr;
  1367. zorro_ram_read_request <= 1;
  1368. zorro_state <= WAIT_READ2;
  1369. end
  1370. WAIT_READ2: begin
  1371. // FIXME there can be a race here where read_request is immediately cancelled
  1372. if (zorro_ram_read_flag) begin
  1373. zorro_ram_read_request <= 0;
  1374. data_out <= axi_reg1[15:0];
  1375. zorro_state <= WAIT_READ2B;
  1376. end
  1377. end
  1378. WAIT_READ2B: begin
  1379. // FIXME trying to fix the race using the same approach as in Z3
  1380. if (!zorro_ram_read_flag) begin
  1381. read_counter <= 0;
  1382. zorro_state <= WAIT_READ2C;
  1383. end
  1384. end
  1385. WAIT_READ2C: begin
  1386. //if (read_counter>7) // FIXME tune this
  1387. zorro_state <= WAIT_READ2D;
  1388. //read_counter <= read_counter + 1'b1;
  1389. end
  1390. WAIT_READ2D: begin
  1391. read_counter <= 0;
  1392. dtack <= 1;
  1393. zorro_state <= Z2_ENDCYCLE;
  1394. end
  1395. WAIT_WRITE: begin
  1396. if (z2_datastrobe_synced) begin
  1397. zorro_write_capture_bytes <= {~znUDS_sync[2],~znLDS_sync[2]}; // FIXME was 1
  1398. zorro_write_capture_data <= zdata_in_sync;
  1399. if (last_addr<'h10000 || videocap_mode)
  1400. zorro_state <= WAIT_WRITE2;
  1401. else
  1402. zorro_state <= WAIT_WRITE_DMA_Z2;
  1403. end
  1404. end
  1405. WAIT_WRITE2: begin
  1406. zorro_ram_write_addr <= last_addr;
  1407. zorro_ram_write_bytes <= {2'b0,zorro_write_capture_bytes};
  1408. zorro_ram_write_data <= {16'b0,zorro_write_capture_data};
  1409. zorro_ram_write_request <= 1;
  1410. zorro_state <= Z2_WRITE_FINALIZE;
  1411. end
  1412. WAIT_WRITE_DMA_Z2: begin
  1413. if (last_addr[1])
  1414. m00_axi_wstrb_z3 <= {zorro_write_capture_bytes[0],zorro_write_capture_bytes[1],2'b0};
  1415. else
  1416. m00_axi_wstrb_z3 <= {2'b0,zorro_write_capture_bytes[0],zorro_write_capture_bytes[1]};
  1417. m00_axi_awaddr_z3 <= (last_addr+`ARM_MEMORY_START)&'hfffffc;
  1418. m00_axi_wdata_z3 <= {zorro_write_capture_data[7:0],zorro_write_capture_data[15:8],zorro_write_capture_data[7:0],zorro_write_capture_data[15:8]};
  1419. m00_axi_awvalid_z3 <= 1;
  1420. if (m00_axi_awready) begin // TODO wready?
  1421. zorro_state <= WAIT_WRITE_DMA_Z2_FINALIZE;
  1422. end
  1423. end
  1424. WAIT_WRITE_DMA_Z2_FINALIZE: begin
  1425. m00_axi_awvalid_z3 <= 0;
  1426. m00_axi_wvalid_z3 <= 1;
  1427. if (m00_axi_wready) begin
  1428. dtack <= 1;
  1429. zorro_state <= Z2_ENDCYCLE;
  1430. end
  1431. end
  1432. Z2_WRITE_FINALIZE: begin
  1433. if (zorro_ram_write_flag) begin
  1434. dtack <= 1;
  1435. zorro_state <= Z2_ENDCYCLE;
  1436. zorro_ram_write_request <= 0;
  1437. end
  1438. end
  1439. Z2_ENDCYCLE: begin
  1440. m00_axi_wvalid_z3 <= 0;
  1441. z_ovr <= 0;
  1442. read_counter <= read_counter + 1'b1;
  1443. if (read_counter >= 10) begin
  1444. dtack <= 0;
  1445. end
  1446. if (!z2_addr_valid) begin
  1447. dtack <= 0;
  1448. slaven <= 0;
  1449. dataout_enable <= 0;
  1450. dataout <= 0;
  1451. zorro_state <= Z2_IDLE;
  1452. read_counter <= 0;
  1453. end
  1454. end
  1455. // 16bit reg read
  1456. Z2_REGREAD_POST: begin
  1457. if (zaddr_regpart[1]==1'b1)
  1458. data_out <= rr_data[15:0];
  1459. else
  1460. data_out <= rr_data[31:16];
  1461. dtack <= 1;
  1462. zorro_state <= Z2_ENDCYCLE;
  1463. end
  1464. // relaxing the data pipeline a bit
  1465. Z2_REGREAD: begin
  1466. regread_addr <= zaddr_regpart;
  1467. zorro_state <= REGREAD;
  1468. end
  1469. `endif
  1470. `ifdef ZORRO3
  1471. // =========================================================================
  1472. // ZORRO 3
  1473. // =========================================================================
  1474. // questionable direct access
  1475. Z3_REGWRITE_PRE: begin
  1476. if (znDS1_sync[2]==0) begin
  1477. regdata_in <= data_in_z3_low16;
  1478. z3addr_regpart <= (z3addr[15:0])|16'h2;
  1479. zorro_state <= Z3_REGWRITE;
  1480. end else if (znUDS_sync[2]==0) begin
  1481. regdata_in <= zdata_in_sync;
  1482. z3addr_regpart <= z3addr[15:0];
  1483. zorro_state <= Z3_REGWRITE;
  1484. end
  1485. end
  1486. Z3_REGREAD_PRE: begin
  1487. z3addr_regpart <= z3addr[15:0]; //|16'h2;
  1488. //if (z3_din_latch) begin
  1489. zorro_state <= Z3_REGREAD;
  1490. //end
  1491. dataout_z3 <= 1;
  1492. end
  1493. Z3_IDLE: begin
  1494. read_counter <= 0;
  1495. if (z3_fcs_state==0) begin
  1496. // falling edge of /FCS
  1497. if (zorro_write && z3addr_in_reg) begin
  1498. // FIXME doesn't support 32 bit access
  1499. // write to register
  1500. zorro_state <= Z3_REGWRITE_PRE;
  1501. slaven <= 1;
  1502. end else if (zorro_read && z3addr_in_reg) begin
  1503. // read registers
  1504. data_z3_hi16 <= default_data;
  1505. data_z3_low16 <= default_data;
  1506. zorro_state <= Z3_REGREAD_PRE;
  1507. slaven <= 1;
  1508. end else if (z3addr_in_ram && zorro_write) begin
  1509. // write to memory
  1510. //read_counter <= 0;
  1511. slaven <= 1;
  1512. zorro_state <= Z3_WRITE_PRE;
  1513. end else if (z3addr_in_ram && zorro_read) begin
  1514. // read from memory
  1515. data_z3_hi16 <= default_data;
  1516. data_z3_low16 <= default_data;
  1517. slaven <= 1;
  1518. zorro_state <= Z3_READ_UPPER;
  1519. end else begin
  1520. // address not recognized
  1521. slaven <= 0;
  1522. end
  1523. end else begin
  1524. // not in a cycle
  1525. slaven <= 0;
  1526. end
  1527. end
  1528. Z3_REGWRITE: begin
  1529. regwrite_addr <= z3addr_regpart;
  1530. zorro_state <= REGWRITE;
  1531. dtack <= 1;
  1532. end
  1533. Z3_REGREAD: begin
  1534. regread_addr <= z3addr_regpart;
  1535. zorro_state <= REGREAD;
  1536. end
  1537. // 32bit reg read
  1538. Z3_REGREAD_POST: begin
  1539. data_z3_hi16 <= rr_data[31:16];
  1540. data_z3_low16 <= rr_data[15:0];
  1541. zorro_state <= Z3_ENDCYCLE;
  1542. dtack <= 1;
  1543. end
  1544. Z3_READ_UPPER: begin
  1545. zorro_state <= Z3_READ_DELAY1;
  1546. last_z3addr <= z3_mapped_addr;
  1547. zorro_ram_read_addr <= z3_mapped_addr;
  1548. zorro_ram_read_bytes <= 4'b1111;
  1549. zorro_ram_read_request <= 1;
  1550. dataout_z3 <= 1; // enable data output
  1551. // dummy read
  1552. /*dtack <= 1;
  1553. data_z3_hi16 <= 'hffff;
  1554. data_z3_low16 <= 'hffff;
  1555. zorro_state <= Z3_ENDCYCLE;*/
  1556. end
  1557. Z3_READ_DELAY1: begin
  1558. data_z3_hi16 <= axi_reg1[31:16];
  1559. data_z3_low16 <= axi_reg1[15:0];
  1560. //read_counter <= 0;
  1561. if (zorro_ram_read_flag) begin
  1562. zorro_ram_read_request <= 0; // acknowledge read request done
  1563. zorro_state <= Z3_READ_DELAY2; // CHECK DELAY
  1564. end
  1565. end
  1566. Z3_READ_DELAY2: begin
  1567. if (!zorro_ram_read_flag) begin
  1568. zorro_state <= Z3_ENDCYCLE;
  1569. dtack <= 1;
  1570. slaven <= 0;
  1571. end
  1572. end
  1573. Z3_WRITE_PRE: begin
  1574. // FIXME was [2] for A3000
  1575. z3_ds0 <= ~znDS0_sync[1];
  1576. z3_ds1 <= ~znDS1_sync[1];
  1577. z3_ds2 <= ~znLDS_sync[1];
  1578. z3_ds3 <= ~znUDS_sync[1];
  1579. if (~znDS0_sync[1]||~znDS1_sync[1]||~znLDS_sync[1]||~znUDS_sync[1]) begin
  1580. zorro_state <= Z3_WRITE_PRE2;
  1581. end
  1582. end
  1583. Z3_WRITE_PRE2: begin
  1584. // 1 more time for good measure
  1585. z3_ds0 <= ~znDS0_sync[1];
  1586. z3_ds1 <= ~znDS1_sync[1];
  1587. z3_ds2 <= ~znLDS_sync[1];
  1588. z3_ds3 <= ~znUDS_sync[1];
  1589. if (z3_mapped_addr<'h10000 || videocap_mode)
  1590. zorro_state <= Z3_WRITE_UPPER;
  1591. else
  1592. zorro_state <= WAIT_WRITE_DMA_Z3;
  1593. end
  1594. Z3_WRITE_UPPER: begin
  1595. last_z3addr <= z3_mapped_addr;
  1596. zorro_ram_write_addr <= z3_mapped_addr;
  1597. zorro_ram_write_bytes <= {z3_ds3,z3_ds2,z3_ds1,z3_ds0};
  1598. zorro_ram_write_data <= {z3_din_high_s2,z3_din_low_s2};
  1599. zorro_ram_write_request <= 1;
  1600. zorro_state <= Z3_WRITE_FINALIZE;
  1601. end
  1602. Z3_WRITE_FINALIZE: begin
  1603. if (zorro_ram_write_flag) begin
  1604. zorro_ram_write_request <= 0; // acknowledge write request done
  1605. zorro_state <= Z3_ENDCYCLE;
  1606. dtack <= 1;
  1607. slaven <= 0;
  1608. end
  1609. end
  1610. WAIT_WRITE_DMA_Z3: begin
  1611. //z3_axi_write <= 1;
  1612. m00_axi_wstrb_z3 <= {z3_ds0, z3_ds1, z3_ds2, z3_ds3};
  1613. m00_axi_awaddr_z3 <= `ARM_MEMORY_START + (z3_mapped_addr/*&32'hfffffffc*/); // max 256MB
  1614. m00_axi_wdata_z3 <= {z3_din_low_s2[7:0], z3_din_low_s2[15:8], z3_din_high_s2[7:0], z3_din_high_s2[15:8]};
  1615. m00_axi_awvalid_z3 <= 1;
  1616. if (m00_axi_awready) begin
  1617. zorro_state <= WAIT_WRITE_DMA_Z3B;
  1618. end
  1619. end
  1620. WAIT_WRITE_DMA_Z3B: begin
  1621. m00_axi_awvalid_z3 <= 0;
  1622. m00_axi_wvalid_z3 <= 1;
  1623. if (m00_axi_wready) begin
  1624. zorro_state <= WAIT_WRITE_DMA_Z3C;
  1625. end
  1626. end
  1627. // not sure if this extra state is needed actually
  1628. WAIT_WRITE_DMA_Z3C: begin
  1629. m00_axi_wvalid_z3 <= 0;
  1630. zorro_state <= Z3_ENDCYCLE;
  1631. end
  1632. Z3_ENDCYCLE: begin
  1633. //z3_axi_write <= 0;
  1634. dtack <= 1;
  1635. slaven <= 0;
  1636. // we're timing out or own dtack here. because of a zorro
  1637. // bug / subtlety, dtack can be sampled incorrectly to "hang over"
  1638. // into the next amiga zorro cycle.
  1639. // TODO: find the optimal value or make it user adjustable (the 10)
  1640. read_counter <= read_counter + 1'b1;
  1641. if (read_counter >= 10) begin
  1642. dtack <= 0;
  1643. end
  1644. if (z3_fcs_state==1) begin
  1645. dtack <= 0;
  1646. slaven <= 0;
  1647. dataout_z3 <= 0;
  1648. zorro_state <= Z3_IDLE;
  1649. end
  1650. end
  1651. `endif
  1652. // FIXME why is there no dataout time on REGREAD? (see memory reads)
  1653. // now fixed for Z3, still pending for Z2
  1654. REGREAD: begin
  1655. // TODO split up into z3/z2
  1656. `ifdef ZORRO3
  1657. zorro_state <= Z3_REGREAD_POST;
  1658. `else
  1659. zorro_state <= Z2_REGREAD_POST;
  1660. `endif
  1661. case (regread_addr&'hff)
  1662. /*'h00: begin
  1663. rr_data <= video_control_data;
  1664. end
  1665. 'h04: begin
  1666. rr_data <= video_control_op;
  1667. end*/
  1668. 'h00: begin
  1669. // this flag is read by Amiga software to check if all writes are done
  1670. rr_data <= 0; //zorro_ram_write_request;
  1671. end
  1672. default: begin
  1673. rr_data[31:16] <= REVISION;
  1674. rr_data[15:0] <= REVISION;
  1675. end
  1676. endcase
  1677. end
  1678. REGWRITE: begin
  1679. `ifdef ZORRO3
  1680. zorro_state <= Z3_ENDCYCLE;
  1681. `else
  1682. dtack <= 1;
  1683. zorro_state <= Z2_ENDCYCLE;
  1684. `endif
  1685. case (regwrite_addr&'hff)
  1686. 'h00: video_control_data_zorro[31:16] <= regdata_in[15:0];
  1687. 'h02: video_control_data_zorro[15:0] <= regdata_in[15:0];
  1688. 'h04: video_control_op_zorro[7:0] <= regdata_in[7:0]; // FIXME
  1689. 'h06: videocap_mode_in <= regdata_in[0];
  1690. //'h14: zorro_interrupt <= regdata_in[0];
  1691. //'h08: videocap_prex <= regdata_in;
  1692. //'h0a: videocap_voffset <= regdata_in;
  1693. //'h10: E7M_PSINCDEC <= regdata_in[0];
  1694. //'h12: E7M_PSEN <= regdata_in[0];
  1695. endcase
  1696. end
  1697. endcase
  1698. // PSEN reset
  1699. if (E7M_PSEN==1'b1) E7M_PSEN <= 1'b0;
  1700. // ARM video control
  1701. if (axi_reg2[31]==1'b1) begin
  1702. video_control_data_axi <= axi_reg3[31:0];
  1703. video_control_op_axi <= axi_reg2[7:0];
  1704. video_control_axi <= 1;
  1705. end else
  1706. video_control_axi <= 0;
  1707. if (axi_reg2[30]==1'b1) begin
  1708. zorro_interrupt <= axi_reg2[0];
  1709. end
  1710. // read / write request acknowledged by ARM
  1711. zorro_ram_read_flag <= axi_reg0[30];
  1712. zorro_ram_write_flag <= axi_reg0[31];
  1713. axi_reg0 <= slv_reg0;
  1714. axi_reg1 <= slv_reg1;
  1715. axi_reg2 <= slv_reg2;
  1716. axi_reg3 <= slv_reg3;
  1717. if (video_control_axi) begin
  1718. video_control_data <= video_control_data_axi;
  1719. video_control_op <= video_control_op_axi;
  1720. end else begin
  1721. video_control_data <= video_control_data_zorro;
  1722. video_control_op <= video_control_op_zorro;
  1723. end
  1724. // snoop the screen width for correct capture pitch
  1725. if (video_control_op_axi == 2) begin
  1726. // OP_DIMENSIONS = 2
  1727. videocap_pitch <= video_control_data_axi[11:0];
  1728. end
  1729. videocap_ymax_sync <= videocap_ymax;
  1730. out_reg0 <= ZORRO3 ? last_z3addr : last_addr;
  1731. out_reg1 <= zorro_ram_write_data;
  1732. out_reg2 <= last_z3addr;
  1733. //out_reg3 <= {zorro_ram_write_request, zorro_ram_read_request, zorro_ram_write_bytes, ZORRO3,
  1734. // video_control_interlace, videocap_mode, 15'b0, zorro_state};
  1735. // `-- 24 `-- 23 `-- 22 `-- 7:0
  1736. out_reg3 <= {zorro_ram_write_request, zorro_ram_read_request, zorro_ram_write_bytes, ZORRO3,
  1737. video_control_interlace, videocap_mode, videocap_ntsc, video_control_vblank, 13'b0, zorro_state};
  1738. end
  1739. assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
  1740. always @(*)
  1741. begin
  1742. // Address decoding for reading registers
  1743. case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
  1744. 2'h0 : reg_data_out <= out_reg0;
  1745. 2'h1 : reg_data_out <= out_reg1;
  1746. 2'h2 : reg_data_out <= out_reg2;
  1747. 2'h3 : reg_data_out <= out_reg3;
  1748. default : reg_data_out <= 'h0;
  1749. endcase
  1750. end
  1751. endmodule