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update zz9000_project.tcl for recreating block design

release-170
mntmn 3 weeks ago
parent
commit
d510d9d07b
Signed by: mntmn <lukas@mntre.com> GPG Key ID: 376511EB67AD7BAF
2 changed files with 263 additions and 1260 deletions
  1. +263
    -227
      zz9000_project.tcl
  2. +0
    -1033
      zz9000_ps.tcl

+ 263
- 227
zz9000_project.tcl View File

@@ -3,7 +3,7 @@
#
# zz9000_project.tcl: Tcl script for re-creating project 'ZZ9000_proto'
#
# Generated by Vivado on Sun Jan 05 20:23:52 CET 2020
# Generated by Vivado on Wed Sep 02 13:20:36 CEST 2020
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -255,11 +255,11 @@ proc cr_bd_zz9000_ps { parentCell } {
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:axi_dwidth_converter:2.1\
xilinx.com:ip:axi_protocol_converter:2.1\
xilinx.com:ip:axi_register_slice:2.1\
xilinx.com:ip:clk_wiz:6.0\
xilinx.com:ip:proc_sys_reset:5.0\
xilinx.com:ip:processing_system7:5.5\
xilinx.com:ip:xadc_wiz:3.3\
xilinx.com:ip:xlslice:1.0\
xilinx.com:ip:axi_vdma:6.3\
xilinx.com:ip:axis_data_fifo:2.0\
@@ -349,7 +349,7 @@ proc create_hier_cell_video { parentCell nameHier } {
current_bd_instance $hier_obj

# Create interface pins
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_MM2S
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_MM2S1
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_LITE

# Create pins
@@ -370,7 +370,7 @@ proc create_hier_cell_video { parentCell nameHier } {
# Create instance: axi_vdma_0, and set properties
set axi_vdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.3 axi_vdma_0 ]
set_property -dict [ list \
CONFIG.c_include_mm2s_dre {0} \
CONFIG.c_include_mm2s_dre {1} \
CONFIG.c_include_s2mm {0} \
CONFIG.c_m_axi_mm2s_data_width {32} \
CONFIG.c_mm2s_genlock_mode {0} \
@@ -384,6 +384,7 @@ proc create_hier_cell_video { parentCell nameHier } {
set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
set_property -dict [ list \
CONFIG.FIFO_DEPTH {32} \
CONFIG.FIFO_MEMORY_TYPE {auto} \
] $axis_data_fifo_0

# Create instance: video_formatter_0, and set properties
@@ -398,10 +399,10 @@ proc create_hier_cell_video { parentCell nameHier } {
}
# Create interface connections
connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins M_AXI_MM2S1] [get_bd_intf_pins axi_vdma_0/M_AXI_MM2S]
connect_bd_intf_net -intf_net axi_vdma_0_M_AXIS_MM2S [get_bd_intf_pins axi_vdma_0/M_AXIS_MM2S] [get_bd_intf_pins axis_data_fifo_0/S_AXIS]
connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axis_data_fifo_0/M_AXIS] [get_bd_intf_pins video_formatter_0/m_axis_vid]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins S_AXI_LITE] [get_bd_intf_pins axi_vdma_0/S_AXI_LITE]
connect_bd_intf_net -intf_net video_subsystem_M_AXI_MM2S [get_bd_intf_pins M_AXI_MM2S] [get_bd_intf_pins axi_vdma_0/M_AXI_MM2S]

# Create port connections
connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_data [get_bd_pins control_data] [get_bd_pins video_formatter_0/control_data]
@@ -525,35 +526,35 @@ proc create_hier_cell_video { parentCell nameHier } {
# Create instance: axi_dwidth_converter_0, and set properties
set axi_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_0 ]

# Create instance: axi_mem_intercon, and set properties
set axi_mem_intercon [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon ]
# Create instance: axi_interconnect_0, and set properties
set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
set_property -dict [ list \
CONFIG.NUM_MI {1} \
] $axi_mem_intercon
CONFIG.S00_HAS_REGSLICE {3} \
] $axi_interconnect_0

# Create instance: axi_protocol_convert_0, and set properties
set axi_protocol_convert_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_converter:2.1 axi_protocol_convert_0 ]

# Create instance: axi_protocol_convert_1, and set properties
set axi_protocol_convert_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_converter:2.1 axi_protocol_convert_1 ]
# Create instance: axi_interconnect_1, and set properties
set axi_interconnect_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_1 ]
set_property -dict [ list \
CONFIG.TRANSLATION_MODE {2} \
] $axi_protocol_convert_1

# Create instance: axi_protocol_convert_2, and set properties
set axi_protocol_convert_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_converter:2.1 axi_protocol_convert_2 ]
CONFIG.NUM_MI {1} \
CONFIG.S00_HAS_REGSLICE {4} \
] $axi_interconnect_1

# Create instance: axi_register_slice_0, and set properties
set axi_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 ]
# Create instance: axi_interconnect_2, and set properties
set axi_interconnect_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_2 ]
set_property -dict [ list \
CONFIG.NUM_MI {1} \
CONFIG.S00_HAS_REGSLICE {3} \
] $axi_interconnect_2

# Create instance: axi_register_slice_1, and set properties
set axi_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_1 ]

# Create instance: axi_register_slice_2, and set properties
set axi_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_2 ]
# Create instance: axi_register_slice_3, and set properties
set axi_register_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_3 ]
set_property -dict [ list \
CONFIG.PROTOCOL {AXI3} \
CONFIG.REG_AR {7} \
CONFIG.REG_AW {7} \
CONFIG.REG_B {7} \
] $axi_register_slice_1

# Create instance: clk_wiz_0, and set properties
set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
@@ -617,6 +618,9 @@ proc create_hier_cell_video { parentCell nameHier } {
CONFIG.PCW_CLK1_FREQ {25000000} \
CONFIG.PCW_CLK2_FREQ {10000000} \
CONFIG.PCW_CLK3_FREQ {10000000} \
CONFIG.PCW_CORE0_FIQ_INTR {0} \
CONFIG.PCW_CORE0_IRQ_INTR {0} \
CONFIG.PCW_CORE1_IRQ_INTR {0} \
CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
@@ -660,7 +664,7 @@ proc create_hier_cell_video { parentCell nameHier } {
CONFIG.PCW_EN_GPIO {1} \
CONFIG.PCW_EN_I2C0 {1} \
CONFIG.PCW_EN_RST0_PORT {1} \
CONFIG.PCW_EN_RST1_PORT {0} \
CONFIG.PCW_EN_RST1_PORT {1} \
CONFIG.PCW_EN_SDIO0 {1} \
CONFIG.PCW_EN_TTC0 {0} \
CONFIG.PCW_EN_UART1 {1} \
@@ -675,7 +679,7 @@ proc create_hier_cell_video { parentCell nameHier } {
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_FCLK_CLK0_BUF {FALSE} \
CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \
CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \
CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {25} \
@@ -699,6 +703,7 @@ proc create_hier_cell_video { parentCell nameHier } {
CONFIG.PCW_I2C_RESET_SELECT {<Select>} \
CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
CONFIG.PCW_IRQ_F2P_INTR {1} \
CONFIG.PCW_MIO_0_DIRECTION {inout} \
CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_0_PULLUP {enabled} \
@@ -917,7 +922,7 @@ proc create_hier_cell_video { parentCell nameHier } {
CONFIG.PCW_MIO_9_SLEW {slow} \
CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO#GPIO#UART 1#UART 1#I2C 0#I2C 0#Enet 0#Enet 0} \
CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#gpio[1]#gpio[2]#gpio[3]#gpio[4]#gpio[5]#gpio[6]#gpio[7]#gpio[8]#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#gpio[46]#gpio[47]#tx#rx#scl#sda#mdc#mdio} \
CONFIG.PCW_P2F_ENET0_INTR {1} \
CONFIG.PCW_P2F_ENET0_INTR {0} \
CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {1} \
@@ -991,7 +996,7 @@ proc create_hier_cell_video { parentCell nameHier } {
CONFIG.PCW_USB_RESET_ENABLE {0} \
CONFIG.PCW_USE_AXI_NONSECURE {0} \
CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {1} \
CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \
CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
CONFIG.PCW_USE_M_AXI_GP0 {1} \
CONFIG.PCW_USE_M_AXI_GP1 {1} \
CONFIG.PCW_USE_S_AXI_ACP {1} \
@@ -1010,9 +1015,9 @@ proc create_hier_cell_video { parentCell nameHier } {
CONFIG.M00_HAS_REGSLICE {3} \
CONFIG.M01_HAS_DATA_FIFO {0} \
CONFIG.M01_HAS_REGSLICE {3} \
CONFIG.NUM_MI {2} \
CONFIG.S00_HAS_DATA_FIFO {1} \
CONFIG.S00_HAS_REGSLICE {4} \
CONFIG.NUM_MI {3} \
CONFIG.S00_HAS_DATA_FIFO {0} \
CONFIG.S00_HAS_REGSLICE {3} \
] $ps7_0_axi_periph

# Create instance: rst_ps7_0_25M, and set properties
@@ -1025,6 +1030,39 @@ proc create_hier_cell_video { parentCell nameHier } {
# Create instance: video
create_hier_cell_video [current_bd_instance .] video

# Create instance: xadc_wiz_0, and set properties
set xadc_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.3 xadc_wiz_0 ]
set_property -dict [ list \
CONFIG.AVERAGE_ENABLE_TEMPERATURE {true} \
CONFIG.AVERAGE_ENABLE_VBRAM {true} \
CONFIG.AVERAGE_ENABLE_VCCAUX {true} \
CONFIG.AVERAGE_ENABLE_VCCDDRO {true} \
CONFIG.AVERAGE_ENABLE_VCCINT {true} \
CONFIG.AVERAGE_ENABLE_VCCPAUX {true} \
CONFIG.AVERAGE_ENABLE_VCCPINT {true} \
CONFIG.CHANNEL_ENABLE_TEMPERATURE {true} \
CONFIG.CHANNEL_ENABLE_VBRAM {true} \
CONFIG.CHANNEL_ENABLE_VCCAUX {true} \
CONFIG.CHANNEL_ENABLE_VCCDDRO {true} \
CONFIG.CHANNEL_ENABLE_VCCINT {true} \
CONFIG.CHANNEL_ENABLE_VCCPAUX {true} \
CONFIG.CHANNEL_ENABLE_VCCPINT {true} \
CONFIG.CHANNEL_ENABLE_VP_VN {false} \
CONFIG.ENABLE_VCCDDRO_ALARM {false} \
CONFIG.ENABLE_VCCPAUX_ALARM {false} \
CONFIG.ENABLE_VCCPINT_ALARM {false} \
CONFIG.EXTERNAL_MUX_CHANNEL {VP_VN} \
CONFIG.SEQUENCER_MODE {Off} \
CONFIG.SINGLE_CHANNEL_SELECTION {TEMPERATURE} \
CONFIG.TEMPERATURE_ALARM_OT_TRIGGER {80} \
CONFIG.TEMPERATURE_ALARM_TRIGGER {85.0} \
CONFIG.TIMING_MODE {Continuous} \
CONFIG.USER_TEMP_ALARM {false} \
CONFIG.VCCAUX_ALARM {false} \
CONFIG.VCCINT_ALARM {false} \
CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} \
] $xadc_wiz_0

# Create instance: xlslice_0, and set properties
set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ]
set_property -dict [ list \
@@ -1053,27 +1091,23 @@ proc create_hier_cell_video { parentCell nameHier } {
] $xlslice_2

# Create interface connections
connect_bd_intf_net -intf_net MNTZorro_v0_1_S00_AXI_0_m00_axi [get_bd_intf_pins MNTZorro_v0_1_S00_AXI_0/m00_axi] [get_bd_intf_pins axi_protocol_convert_2/S_AXI]
connect_bd_intf_net -intf_net MNTZorro_v0_1_S00_AXI_0_m01_axi [get_bd_intf_pins MNTZorro_v0_1_S00_AXI_0/m01_axi] [get_bd_intf_pins axi_mem_intercon/S00_AXI]
connect_bd_intf_net -intf_net axi_dwidth_converter_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/M_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_ACP]
connect_bd_intf_net -intf_net axi_mem_intercon_M00_AXI [get_bd_intf_pins axi_mem_intercon/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP1]
connect_bd_intf_net -intf_net axi_protocol_convert_0_M_AXI [get_bd_intf_pins MNTZorro_v0_1_S00_AXI_0/S_AXI] [get_bd_intf_pins axi_protocol_convert_0/M_AXI]
connect_bd_intf_net -intf_net axi_protocol_convert_1_M_AXI [get_bd_intf_pins axi_protocol_convert_1/M_AXI] [get_bd_intf_pins axi_register_slice_1/S_AXI]
connect_bd_intf_net -intf_net axi_protocol_convert_2_M_AXI [get_bd_intf_pins axi_protocol_convert_2/M_AXI] [get_bd_intf_pins axi_register_slice_3/S_AXI]
connect_bd_intf_net -intf_net axi_register_slice_0_M_AXI [get_bd_intf_pins axi_register_slice_0/M_AXI] [get_bd_intf_pins axi_register_slice_2/S_AXI]
connect_bd_intf_net -intf_net axi_register_slice_1_M_AXI [get_bd_intf_pins axi_register_slice_1/M_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0]
connect_bd_intf_net -intf_net axi_register_slice_2_M_AXI [get_bd_intf_pins axi_protocol_convert_1/S_AXI] [get_bd_intf_pins axi_register_slice_2/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_3_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/S_AXI] [get_bd_intf_pins axi_register_slice_3/M_AXI]
connect_bd_intf_net -intf_net MNTZorro_v0_1_S00_AXI_0_m00_axi [get_bd_intf_pins MNTZorro_v0_1_S00_AXI_0/m00_axi] [get_bd_intf_pins axi_dwidth_converter_0/S_AXI]
connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
connect_bd_intf_net -intf_net S00_AXI_2 [get_bd_intf_pins processing_system7_0/M_AXI_GP1] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
connect_bd_intf_net -intf_net S00_AXI_3 [get_bd_intf_pins axi_interconnect_1/S00_AXI] [get_bd_intf_pins video/M_AXI_MM2S1]
connect_bd_intf_net -intf_net S00_AXI_4 [get_bd_intf_pins MNTZorro_v0_1_S00_AXI_0/m01_axi] [get_bd_intf_pins axi_interconnect_2/S00_AXI]
connect_bd_intf_net -intf_net axi_dwidth_converter_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/M_AXI] [get_bd_intf_pins axi_register_slice_1/S_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins MNTZorro_v0_1_S00_AXI_0/S_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
connect_bd_intf_net -intf_net axi_interconnect_1_M00_AXI [get_bd_intf_pins axi_interconnect_1/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0]
connect_bd_intf_net -intf_net axi_interconnect_2_M00_AXI [get_bd_intf_pins axi_interconnect_2/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP1]
connect_bd_intf_net -intf_net axi_register_slice_1_M_AXI [get_bd_intf_pins axi_register_slice_1/M_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_ACP]
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins axi_protocol_convert_0/S_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP1 [get_bd_intf_pins processing_system7_0/M_AXI_GP1] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins clk_wiz_0/s_axi_lite] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] [get_bd_intf_pins video/S_AXI_LITE]
connect_bd_intf_net -intf_net video_subsystem_M_AXI_MM2S [get_bd_intf_pins axi_register_slice_0/S_AXI] [get_bd_intf_pins video/M_AXI_MM2S]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M02_AXI [get_bd_intf_pins ps7_0_axi_periph/M02_AXI] [get_bd_intf_pins xadc_wiz_0/s_axi_lite]

# Create port connections
connect_bd_net -net M00_ARESETN_1 [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_25M/interconnect_aresetn]
connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_ADDRDIR [get_bd_ports ZORRO_ADDRDIR] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_ADDRDIR]
connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_ADDRDIR2 [get_bd_ports ZORRO_ADDRDIR2] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_ADDRDIR2]
connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_DATADIR [get_bd_ports ZORRO_DATADIR] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_DATADIR]
@@ -1083,11 +1117,13 @@ proc create_hier_cell_video { parentCell nameHier } {
connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_NCINH [get_bd_ports ZORRO_NCINH] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NCINH]
connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_NDTACK [get_bd_ports ZORRO_NDTACK] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NDTACK]
connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_ZORRO_NSLAVE [get_bd_ports ZORRO_NSLAVE] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NSLAVE]
connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_data [get_bd_pins MNTZorro_v0_1_S00_AXI_0/video_control_data] [get_bd_pins video/control_data]
connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_interlace [get_bd_pins MNTZorro_v0_1_S00_AXI_0/video_control_interlace] [get_bd_pins video/control_interlace]
connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_op [get_bd_pins MNTZorro_v0_1_S00_AXI_0/video_control_op] [get_bd_pins video/control_op]
connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_arm_interrupt [get_bd_pins MNTZorro_v0_1_S00_AXI_0/arm_interrupt] [get_bd_pins processing_system7_0/IRQ_F2P]
connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_data [get_bd_pins MNTZorro_v0_1_S00_AXI_0/video_control_data_out] [get_bd_pins video/control_data]
connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_interlace [get_bd_pins MNTZorro_v0_1_S00_AXI_0/video_control_interlace_out] [get_bd_pins video/control_interlace]
connect_bd_net -net MNTZorro_v0_1_S00_AXI_0_video_control_op [get_bd_pins MNTZorro_v0_1_S00_AXI_0/video_control_op_out] [get_bd_pins video/control_op]
connect_bd_net -net Net [get_bd_ports ZORRO_ADDR] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_ADDR]
connect_bd_net -net Net1 [get_bd_ports ZORRO_DATA] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_DATA]
connect_bd_net -net S00_ACLK_1 [get_bd_pins clk_wiz_0/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK1] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_25M/slowest_sync_clk] [get_bd_pins video/s_axi_lite_aclk] [get_bd_pins xadc_wiz_0/s_axi_aclk]
connect_bd_net -net VCAP_B0_0_1 [get_bd_ports VCAP_B0] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B0]
connect_bd_net -net VCAP_B1_0_1 [get_bd_ports VCAP_B1] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B1]
connect_bd_net -net VCAP_B2_0_1 [get_bd_ports VCAP_B2] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/VCAP_B2]
@@ -1128,13 +1164,13 @@ proc create_hier_cell_video { parentCell nameHier } {
connect_bd_net -net ZORRO_NUDS_1 [get_bd_ports ZORRO_NUDS] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NUDS]
connect_bd_net -net ZORRO_READ_1 [get_bd_ports ZORRO_READ] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_READ]
connect_bd_net -net clk_1 [get_bd_ports VGA_PCLK] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins video/VGA_PCLK]
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins MNTZorro_v0_1_S00_AXI_0/S_AXI_ARESETN] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/m00_axi_aresetn] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/m01_axi_aresetn] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn] [get_bd_pins axi_mem_intercon/ARESETN] [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins axi_protocol_convert_0/aresetn] [get_bd_pins axi_protocol_convert_1/aresetn] [get_bd_pins axi_protocol_convert_2/aresetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins axi_register_slice_1/aresetn] [get_bd_pins axi_register_slice_2/aresetn] [get_bd_pins axi_register_slice_3/aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins video/aresetn]
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins MNTZorro_v0_1_S00_AXI_0/S_AXI_ACLK] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/m00_axi_aclk] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/m01_axi_aclk] [get_bd_pins axi_dwidth_converter_0/s_axi_aclk] [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axi_protocol_convert_0/aclk] [get_bd_pins axi_protocol_convert_1/aclk] [get_bd_pins axi_protocol_convert_2/aclk] [get_bd_pins axi_register_slice_0/aclk] [get_bd_pins axi_register_slice_1/aclk] [get_bd_pins axi_register_slice_2/aclk] [get_bd_pins axi_register_slice_3/aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_ACP_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins video/m_axi_mm2s_aclk]
connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_pins clk_wiz_0/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK1] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_25M/slowest_sync_clk] [get_bd_pins video/s_axi_lite_aclk]
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_25M/ext_reset_in]
connect_bd_net -net rst_ps7_0_25M_peripheral_aresetn [get_bd_pins clk_wiz_0/s_axi_aresetn] [get_bd_pins rst_ps7_0_25M/peripheral_aresetn] [get_bd_pins video/axi_resetn]
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins MNTZorro_v0_1_S00_AXI_0/S_AXI_ARESETN] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/m00_axi_aresetn] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/m01_axi_aresetn] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_1/ARESETN] [get_bd_pins axi_interconnect_1/M00_ARESETN] [get_bd_pins axi_interconnect_1/S00_ARESETN] [get_bd_pins axi_interconnect_2/ARESETN] [get_bd_pins axi_interconnect_2/M00_ARESETN] [get_bd_pins axi_interconnect_2/S00_ARESETN] [get_bd_pins axi_register_slice_1/aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins video/aresetn]
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins MNTZorro_v0_1_S00_AXI_0/S_AXI_ACLK] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/m00_axi_aclk] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/m01_axi_aclk] [get_bd_pins axi_dwidth_converter_0/s_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_1/ACLK] [get_bd_pins axi_interconnect_1/M00_ACLK] [get_bd_pins axi_interconnect_1/S00_ACLK] [get_bd_pins axi_interconnect_2/ACLK] [get_bd_pins axi_interconnect_2/M00_ACLK] [get_bd_pins axi_interconnect_2/S00_ACLK] [get_bd_pins axi_register_slice_1/aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_ACP_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins video/m_axi_mm2s_aclk]
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N]
connect_bd_net -net processing_system7_0_FCLK_RESET1_N [get_bd_pins processing_system7_0/FCLK_RESET1_N] [get_bd_pins rst_ps7_0_25M/ext_reset_in]
connect_bd_net -net rst_ps7_0_25M_peripheral_aresetn [get_bd_pins clk_wiz_0/s_axi_aresetn] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_25M/peripheral_aresetn] [get_bd_pins video/axi_resetn] [get_bd_pins xadc_wiz_0/s_axi_aresetn]
connect_bd_net -net v_axi4s_vid_out_0_vid_data [get_bd_pins video/dvi_rgb] [get_bd_pins xlslice_0/Din] [get_bd_pins xlslice_1/Din] [get_bd_pins xlslice_2/Din]
connect_bd_net -net video_control_vblank [get_bd_pins MNTZorro_v0_1_S00_AXI_0/video_control_vblank] [get_bd_pins video/control_vblank]
connect_bd_net -net video_control_vblank [get_bd_pins MNTZorro_v0_1_S00_AXI_0/video_control_vblank_in] [get_bd_pins video/control_vblank]
connect_bd_net -net video_subsystem_VGA_DE [get_bd_ports VGA_DE] [get_bd_pins video/VGA_DE]
connect_bd_net -net video_subsystem_VGA_HS [get_bd_ports VGA_HS] [get_bd_pins video/VGA_HS]
connect_bd_net -net video_subsystem_VGA_VS [get_bd_ports VGA_VS] [get_bd_pins video/VGA_VS]
@@ -1151,6 +1187,7 @@ proc create_hier_cell_video { parentCell nameHier } {
create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs MNTZorro_v0_1_S00_AXI_0/S_AXI/reg0] SEG_MNTZorro_v0_1_S00_AXI_0_reg0
create_bd_addr_seg -range 0x00010000 -offset 0x83000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs video/axi_vdma_0/S_AXI_LITE/Reg] SEG_axi_vdma_0_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x83C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs clk_wiz_0/s_axi_lite/Reg] SEG_clk_wiz_0_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x83C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs xadc_wiz_0/s_axi_lite/Reg] SEG_xadc_wiz_0_Reg
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces video/axi_vdma_0/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM

# Perform GUI Layout
@@ -1158,171 +1195,166 @@ proc create_hier_cell_video { parentCell nameHier } {
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 6.8.11 2018-08-07 bk=1.4403 VDI=40 GEI=35 GUI=JA:9.0 TLS
# -string -flagsOSRD
preplace port ZORRO_C28D -pg 1 -y 1520 -defaultsOSRD
preplace port VCAP_B7 -pg 1 -y 1740 -defaultsOSRD
preplace port VCAP_R6 -pg 1 -y 1920 -defaultsOSRD
preplace port ZORRO_NIORST -pg 1 -y 1460 -defaultsOSRD
preplace port ZORRO_NDS1 -pg 1 -y 1360 -defaultsOSRD
preplace port ZORRO_NLDS -pg 1 -y 1340 -defaultsOSRD
preplace port DDR -pg 1 -y 600 -defaultsOSRD
preplace port VCAP_R7 -pg 1 -y 1900 -defaultsOSRD
preplace port ZORRO_DATADIR -pg 1 -y 1660 -defaultsOSRD
preplace port ZORRO_NCFGIN -pg 1 -y 1480 -defaultsOSRD
preplace port ZORRO_DOE -pg 1 -y 1440 -defaultsOSRD
preplace port VGA_PCLK -pg 1 -y 80 -defaultsOSRD
preplace port ZORRO_NBRN -pg 1 -y 1720 -defaultsOSRD
preplace port VCAP_G0 -pg 1 -y 1580 -defaultsOSRD
preplace port VGA_VS -pg 1 -y 270 -defaultsOSRD
preplace port VCAP_G1 -pg 1 -y 1600 -defaultsOSRD
preplace port ZORRO_READ -pg 1 -y 1300 -defaultsOSRD
preplace port ZORRO_NCFGOUT -pg 1 -y 1740 -defaultsOSRD
preplace port VCAP_B0 -pg 1 -y 1880 -defaultsOSRD
preplace port VCAP_G2 -pg 1 -y 1620 -defaultsOSRD
preplace port ZORRO_NFCS -pg 1 -y 1420 -defaultsOSRD
preplace port ZORRO_ADDRDIR -pg 1 -y 1680 -defaultsOSRD
preplace port ZORRO_INT6 -pg 1 -y 1640 -defaultsOSRD
preplace port VCAP_R0 -pg 1 -y 2040 -defaultsOSRD
preplace port VCAP_B1 -pg 1 -y 1860 -defaultsOSRD
preplace port VCAP_G3 -pg 1 -y 1640 -defaultsOSRD
preplace port ZORRO_NUDS -pg 1 -y 1320 -defaultsOSRD
preplace port VGA_DE -pg 1 -y 290 -defaultsOSRD
preplace port VCAP_R1 -pg 1 -y 2020 -defaultsOSRD
preplace port VCAP_G4 -pg 1 -y 1660 -defaultsOSRD
preplace port VCAP_B2 -pg 1 -y 1840 -defaultsOSRD
preplace port ZORRO_NDTACK -pg 1 -y 1800 -defaultsOSRD
preplace port FIXED_IO -pg 1 -y 620 -defaultsOSRD
preplace port VCAP_R2 -pg 1 -y 2000 -defaultsOSRD
preplace port VCAP_G5 -pg 1 -y 1680 -defaultsOSRD
preplace port VCAP_VSYNC -pg 1 -y 1540 -defaultsOSRD
preplace port VCAP_B3 -pg 1 -y 1820 -defaultsOSRD
preplace port ZORRO_NCINH -pg 1 -y 1780 -defaultsOSRD
preplace port ZORRO_ADDRDIR2 -pg 1 -y 1700 -defaultsOSRD
preplace port VCAP_R3 -pg 1 -y 1980 -defaultsOSRD
preplace port VCAP_B4 -pg 1 -y 1800 -defaultsOSRD
preplace port VCAP_G6 -pg 1 -y 1700 -defaultsOSRD
preplace port VCAP_R4 -pg 1 -y 1960 -defaultsOSRD
preplace port VCAP_B5 -pg 1 -y 1780 -defaultsOSRD
preplace port VCAP_G7 -pg 1 -y 1720 -defaultsOSRD
preplace port ZORRO_E7M -pg 1 -y 1500 -defaultsOSRD
preplace port ZORRO_NSLAVE -pg 1 -y 1760 -defaultsOSRD
preplace port VGA_HS -pg 1 -y 250 -defaultsOSRD
preplace port ZORRO_NBGN -pg 1 -y 1280 -defaultsOSRD
preplace port VCAP_R5 -pg 1 -y 1940 -defaultsOSRD
preplace port VCAP_B6 -pg 1 -y 1760 -defaultsOSRD
preplace port VCAP_HSYNC -pg 1 -y 1560 -defaultsOSRD
preplace port ZORRO_NCCS -pg 1 -y 1400 -defaultsOSRD
preplace port ZORRO_NDS0 -pg 1 -y 1380 -defaultsOSRD
preplace portBus VGA_B -pg 1 -y 540 -defaultsOSRD
preplace portBus ZORRO_ADDR -pg 1 -y 1600 -defaultsOSRD
preplace portBus VGA_R -pg 1 -y 340 -defaultsOSRD
preplace portBus ZORRO_DATA -pg 1 -y 1620 -defaultsOSRD
preplace portBus VGA_G -pg 1 -y 440 -defaultsOSRD
preplace inst rst_ps7_0_25M -pg 1 -lvl 4 -y 370 -defaultsOSRD
preplace inst xlslice_0 -pg 1 -lvl 7 -y 340 -defaultsOSRD
preplace inst xlslice_1 -pg 1 -lvl 7 -y 440 -defaultsOSRD
preplace inst xlslice_2 -pg 1 -lvl 7 -y 540 -defaultsOSRD
preplace inst axi_dwidth_converter_0 -pg 1 -lvl 5 -y 760 -defaultsOSRD
preplace inst axi_register_slice_0 -pg 1 -lvl 2 -y 390 -defaultsOSRD
preplace inst proc_sys_reset_0 -pg 1 -lvl 1 -y 580 -defaultsOSRD
preplace inst axi_register_slice_1 -pg 1 -lvl 5 -y 600 -defaultsOSRD
preplace inst axi_register_slice_2 -pg 1 -lvl 3 -y 560 -defaultsOSRD
preplace inst axi_protocol_convert_0 -pg 1 -lvl 5 -y 1090 -defaultsOSRD
preplace inst axi_register_slice_3 -pg 1 -lvl 4 -y 740 -defaultsOSRD
preplace inst axi_protocol_convert_1 -pg 1 -lvl 4 -y 580 -defaultsOSRD
preplace inst MNTZorro_v0_1_S00_AXI_0 -pg 1 -lvl 6 -y 1944 -defaultsOSRD
preplace inst axi_protocol_convert_2 -pg 1 -lvl 3 -y 730 -defaultsOSRD
preplace inst ps7_0_axi_periph -pg 1 -lvl 5 -y 230 -defaultsOSRD
preplace inst video -pg 1 -lvl 6 -y 322 -defaultsOSRD
preplace inst clk_wiz_0 -pg 1 -lvl 6 -y 90 -defaultsOSRD
preplace inst axi_mem_intercon -pg 1 -lvl 7 -y 1154 -defaultsOSRD
preplace inst processing_system7_0 -pg 1 -lvl 6 -y 884 -defaultsOSRD
preplace netloc xlslice_2_Dout 1 7 1 NJ
preplace netloc axi_protocol_convert_1_M_AXI 1 4 1 N
preplace netloc VCAP_R4_0_1 1 0 6 NJ 1960 NJ 1960 NJ 1960 NJ 1960 NJ 1960 1790J
preplace netloc VCAP_B2_0_1 1 0 6 NJ 1840 NJ 1840 NJ 1840 NJ 1840 NJ 1840 1850J
preplace netloc processing_system7_0_FIXED_IO 1 6 2 2850J 620 NJ
preplace netloc VCAP_VSYNC_0_1 1 0 6 NJ 1540 NJ 1540 NJ 1540 NJ 1540 NJ 1540 2020J
preplace netloc VCAP_B0_0_1 1 0 6 NJ 1880 NJ 1880 NJ 1880 NJ 1880 NJ 1880 1830J
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NCINH 1 6 2 2850J 1780 NJ
preplace netloc rst_ps7_0_25M_peripheral_aresetn 1 4 2 NJ 410 1980
preplace netloc VCAP_G6_0_1 1 0 6 NJ 1700 NJ 1700 NJ 1700 NJ 1700 NJ 1700 1920J
preplace netloc VCAP_R2_0_1 1 0 6 NJ 2000 NJ 2000 NJ 2000 NJ 2000 NJ 2000 1770J
preplace netloc VCAP_G5_0_1 1 0 6 NJ 1680 NJ 1680 NJ 1680 NJ 1680 NJ 1680 1930J
preplace netloc video_subsystem_VGA_HS 1 6 2 2720J 250 NJ
preplace netloc video_subsystem_M_AXI_MM2S 1 1 6 390 90 NJ 90 NJ 90 NJ 90 2180J 180 2710
preplace netloc axi_dwidth_converter_0_M_AXI 1 5 1 2120
preplace netloc VCAP_R5_0_1 1 0 6 NJ 1940 NJ 1940 NJ 1940 NJ 1940 NJ 1940 1800J
preplace netloc VCAP_G3_0_1 1 0 6 NJ 1640 NJ 1640 NJ 1640 NJ 1640 NJ 1640 1950J
preplace netloc VCAP_R1_0_1 1 0 6 NJ 2020 NJ 2020 NJ 2020 NJ 2020 NJ 2020 1760J
preplace netloc ZORRO_NIORST_1 1 0 6 NJ 1460 NJ 1460 NJ 1460 NJ 1460 NJ 1460 2060J
preplace netloc axi_register_slice_2_M_AXI 1 3 1 N
preplace netloc VCAP_B3_0_1 1 0 6 NJ 1820 NJ 1820 NJ 1820 NJ 1820 NJ 1820 1860J
preplace netloc ZORRO_NDS0_1 1 0 6 NJ 1380 NJ 1380 NJ 1380 NJ 1380 NJ 1380 2100J
preplace netloc ZORRO_NDS1_1 1 0 6 NJ 1360 NJ 1360 NJ 1360 NJ 1360 NJ 1360 2110J
preplace netloc video_subsystem_VGA_DE 1 6 2 2840J 280 3650J
preplace netloc VCAP_G7_0_1 1 0 6 NJ 1720 NJ 1720 NJ 1720 NJ 1720 NJ 1720 1910J
preplace netloc VCAP_HSYNC_0_1 1 0 6 NJ 1560 NJ 1560 NJ 1560 NJ 1560 NJ 1560 2010J
preplace netloc processing_system7_0_DDR 1 6 2 2840J 600 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_m00_axi 1 2 5 690 2464 NJ 2464 NJ 2464 NJ 2464 2670
preplace netloc VCAP_R3_0_1 1 0 6 NJ 1980 NJ 1980 NJ 1980 NJ 1980 NJ 1980 1780J
preplace netloc VCAP_R0_0_1 1 0 6 NJ 2040 NJ 2040 NJ 2040 NJ 2040 NJ 2040 1750J
preplace netloc ZORRO_NLDS_1 1 0 6 NJ 1340 NJ 1340 NJ 1340 NJ 1340 NJ 1340 2120J
preplace netloc axi_protocol_convert_0_M_AXI 1 5 1 2160
preplace netloc VCAP_B4_0_1 1 0 6 NJ 1800 NJ 1800 NJ 1800 NJ 1800 NJ 1800 1870J
preplace netloc ZORRO_C28D_0_1 1 0 6 NJ 1520 NJ 1520 NJ 1520 NJ 1520 NJ 1520 2030J
preplace netloc ps7_0_axi_periph_M00_AXI 1 5 1 1970
preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 7 30 480 NJ 480 650J 460 1010 472 NJ 472 NJ 472 2700
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_INT6 1 6 2 2780J 1640 NJ
preplace netloc xlslice_1_Dout 1 7 1 NJ
preplace netloc ps7_0_axi_periph_M01_AXI 1 5 1 2180
preplace netloc VCAP_G1_0_1 1 0 6 NJ 1600 NJ 1600 NJ 1600 NJ 1600 NJ 1600 1970J
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NDTACK 1 6 2 2860J 1800 NJ
preplace netloc VCAP_B5_0_1 1 0 6 NJ 1780 NJ 1780 NJ 1780 NJ 1780 NJ 1780 1880J
preplace netloc VCAP_G2_0_1 1 0 6 NJ 1620 NJ 1620 NJ 1620 NJ 1620 NJ 1620 1960J
preplace netloc video_control_vblank 1 5 2 2170 502 2710
preplace netloc xlslice_0_Dout 1 7 1 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_ADDRDIR2 1 6 2 2810J 1700 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NSLAVE 1 6 2 2840J 1760 NJ
preplace netloc ZORRO_DOE_1 1 0 6 NJ 1440 NJ 1440 NJ 1440 NJ 1440 NJ 1440 2070J
preplace netloc axi_protocol_convert_2_M_AXI 1 3 1 1010
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_DATADIR 1 6 2 2790J 1660 NJ
preplace netloc axi_register_slice_1_M_AXI 1 5 1 2130
preplace netloc Net 1 6 2 2760J 1600 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NBRN 1 6 2 2820J 1720 NJ
preplace netloc Net1 1 6 2 2770J 1620 NJ
preplace netloc processing_system7_0_FCLK_CLK0 1 0 7 20 470 390 470 670 470 1000 500 1380 500 1990 1044 2840
preplace netloc processing_system7_0_FCLK_CLK1 1 3 4 1010 270 1380 80 2140 1034 2670
preplace netloc VCAP_R7_0_1 1 0 6 NJ 1900 NJ 1900 NJ 1900 NJ 1900 NJ 1900 1820J
preplace netloc VCAP_B6_0_1 1 0 6 NJ 1760 NJ 1760 NJ 1760 NJ 1760 NJ 1760 1890J
preplace netloc axi_register_slice_0_M_AXI 1 2 1 660
preplace netloc v_axi4s_vid_out_0_vid_data 1 6 1 2850
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_ADDRDIR 1 6 2 2800J 1680 NJ
preplace netloc VCAP_G0_0_1 1 0 6 NJ 1580 NJ 1580 NJ 1580 NJ 1580 NJ 1580 1980J
preplace netloc VCAP_R6_0_1 1 0 6 NJ 1920 NJ 1920 NJ 1920 NJ 1920 NJ 1920 1810J
preplace netloc proc_sys_reset_1_peripheral_aresetn 1 1 6 400 490 680 480 990 660 1390 680 2000 1134 2850
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NCFGOUT 1 6 2 2830J 1740 NJ
preplace netloc M00_ARESETN_1 1 4 1 1390
preplace netloc ZORRO_NCFGIN_1 1 0 6 NJ 1480 NJ 1480 NJ 1480 NJ 1480 NJ 1480 2050J
preplace netloc ZORRO_NCCS_1 1 0 6 NJ 1400 NJ 1400 NJ 1400 NJ 1400 NJ 1400 2090J
preplace netloc VCAP_B7_0_1 1 0 6 NJ 1740 NJ 1740 NJ 1740 NJ 1740 NJ 1740 1900J
preplace netloc ZORRO_NBGN_0_1 1 0 6 NJ 1280 NJ 1280 NJ 1280 NJ 1280 NJ 1280 2150J
preplace netloc processing_system7_0_M_AXI_GP0 1 4 3 1410 1170 NJ 1170 2690
preplace netloc processing_system7_0_M_AXI_GP1 1 4 3 1400 1180 NJ 1180 2680
preplace netloc ZORRO_E7M_1 1 0 6 NJ 1500 NJ 1500 NJ 1500 NJ 1500 NJ 1500 2040J
preplace netloc axi_mem_intercon_M00_AXI 1 5 3 2180 734 NJ 734 3650
preplace netloc MNTZorro_v0_1_S00_AXI_0_m01_axi 1 6 1 2750
preplace netloc ZORRO_READ_1 1 0 6 NJ 1300 NJ 1300 NJ 1300 NJ 1300 NJ 1300 2140J
preplace netloc video_subsystem_VGA_VS 1 6 2 2740J 270 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_video_control_op 1 5 2 2160 492 2720
preplace netloc axi_register_slice_3_M_AXI 1 4 1 N
preplace netloc VCAP_B1_0_1 1 0 6 NJ 1860 NJ 1860 NJ 1860 NJ 1860 NJ 1860 1840J
preplace netloc MNTZorro_v0_1_S00_AXI_0_video_control_interlace 1 5 2 2180 462 2740
preplace netloc clk_1 1 5 3 2170 452 2730 80 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_video_control_data 1 5 2 2150 482 2730
preplace netloc ZORRO_NUDS_1 1 0 6 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ 1320 2130J
preplace netloc ZORRO_NFCS_1 1 0 6 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 2080J
preplace netloc VCAP_G4_0_1 1 0 6 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 1940J
levelinfo -pg 1 0 210 530 840 1200 1580 2450 3500 3670 -top 0 -bot 3270
preplace port ZORRO_C28D -pg 1 -y 1550 -defaultsOSRD
preplace port VCAP_B7 -pg 1 -y 1770 -defaultsOSRD
preplace port VCAP_R6 -pg 1 -y 1950 -defaultsOSRD
preplace port ZORRO_NIORST -pg 1 -y 1490 -defaultsOSRD
preplace port ZORRO_NDS1 -pg 1 -y 1390 -defaultsOSRD
preplace port ZORRO_NLDS -pg 1 -y 1370 -defaultsOSRD
preplace port DDR -pg 1 -y 410 -defaultsOSRD
preplace port VCAP_R7 -pg 1 -y 1930 -defaultsOSRD
preplace port ZORRO_DATADIR -pg 1 -y 1890 -defaultsOSRD
preplace port ZORRO_NCFGIN -pg 1 -y 1510 -defaultsOSRD
preplace port ZORRO_DOE -pg 1 -y 1470 -defaultsOSRD
preplace port VGA_PCLK -pg 1 -y 770 -defaultsOSRD
preplace port ZORRO_NBRN -pg 1 -y 1950 -defaultsOSRD
preplace port VCAP_G0 -pg 1 -y 1610 -defaultsOSRD
preplace port VGA_VS -pg 1 -y 1110 -defaultsOSRD
preplace port VCAP_G1 -pg 1 -y 1630 -defaultsOSRD
preplace port ZORRO_READ -pg 1 -y 1330 -defaultsOSRD
preplace port ZORRO_NCFGOUT -pg 1 -y 1970 -defaultsOSRD
preplace port VCAP_B0 -pg 1 -y 1910 -defaultsOSRD
preplace port VCAP_G2 -pg 1 -y 1650 -defaultsOSRD
preplace port ZORRO_NFCS -pg 1 -y 1450 -defaultsOSRD
preplace port ZORRO_ADDRDIR -pg 1 -y 1910 -defaultsOSRD
preplace port ZORRO_INT6 -pg 1 -y 1870 -defaultsOSRD
preplace port VCAP_R0 -pg 1 -y 2070 -defaultsOSRD
preplace port VCAP_B1 -pg 1 -y 1890 -defaultsOSRD
preplace port VCAP_G3 -pg 1 -y 1670 -defaultsOSRD
preplace port ZORRO_NUDS -pg 1 -y 1350 -defaultsOSRD
preplace port VGA_DE -pg 1 -y 1130 -defaultsOSRD
preplace port VCAP_R1 -pg 1 -y 2050 -defaultsOSRD
preplace port VCAP_G4 -pg 1 -y 1690 -defaultsOSRD
preplace port VCAP_B2 -pg 1 -y 1870 -defaultsOSRD
preplace port ZORRO_NDTACK -pg 1 -y 2030 -defaultsOSRD
preplace port FIXED_IO -pg 1 -y 430 -defaultsOSRD
preplace port VCAP_R2 -pg 1 -y 2030 -defaultsOSRD
preplace port VCAP_G5 -pg 1 -y 1710 -defaultsOSRD
preplace port VCAP_VSYNC -pg 1 -y 1570 -defaultsOSRD
preplace port VCAP_B3 -pg 1 -y 1850 -defaultsOSRD
preplace port ZORRO_NCINH -pg 1 -y 2010 -defaultsOSRD
preplace port ZORRO_ADDRDIR2 -pg 1 -y 1930 -defaultsOSRD
preplace port VCAP_R3 -pg 1 -y 2010 -defaultsOSRD
preplace port VCAP_B4 -pg 1 -y 1830 -defaultsOSRD
preplace port VCAP_G6 -pg 1 -y 1730 -defaultsOSRD
preplace port VCAP_R4 -pg 1 -y 1990 -defaultsOSRD
preplace port VCAP_B5 -pg 1 -y 1810 -defaultsOSRD
preplace port VCAP_G7 -pg 1 -y 1750 -defaultsOSRD
preplace port ZORRO_E7M -pg 1 -y 1530 -defaultsOSRD
preplace port ZORRO_NSLAVE -pg 1 -y 1990 -defaultsOSRD
preplace port VGA_HS -pg 1 -y 1090 -defaultsOSRD
preplace port ZORRO_NBGN -pg 1 -y 1310 -defaultsOSRD
preplace port VCAP_R5 -pg 1 -y 1970 -defaultsOSRD
preplace port VCAP_B6 -pg 1 -y 1790 -defaultsOSRD
preplace port VCAP_HSYNC -pg 1 -y 1590 -defaultsOSRD
preplace port ZORRO_NCCS -pg 1 -y 1430 -defaultsOSRD
preplace port ZORRO_NDS0 -pg 1 -y 1410 -defaultsOSRD
preplace portBus VGA_B -pg 1 -y 1390 -defaultsOSRD
preplace portBus ZORRO_ADDR -pg 1 -y 1830 -defaultsOSRD
preplace portBus VGA_R -pg 1 -y 1290 -defaultsOSRD
preplace portBus ZORRO_DATA -pg 1 -y 1850 -defaultsOSRD
preplace portBus VGA_G -pg 1 -y 1190 -defaultsOSRD
preplace inst rst_ps7_0_25M -pg 1 -lvl 2 -y 540 -defaultsOSRD
preplace inst xlslice_0 -pg 1 -lvl 5 -y 1290 -defaultsOSRD
preplace inst xlslice_1 -pg 1 -lvl 5 -y 1190 -defaultsOSRD
preplace inst xadc_wiz_0 -pg 1 -lvl 5 -y 200 -defaultsOSRD
preplace inst xlslice_2 -pg 1 -lvl 5 -y 1390 -defaultsOSRD
preplace inst axi_dwidth_converter_0 -pg 1 -lvl 2 -y 330 -defaultsOSRD
preplace inst proc_sys_reset_0 -pg 1 -lvl 1 -y 330 -defaultsOSRD
preplace inst axi_register_slice_1 -pg 1 -lvl 3 -y 370 -defaultsOSRD
preplace inst MNTZorro_v0_1_S00_AXI_0 -pg 1 -lvl 4 -y 1750 -defaultsOSRD
preplace inst axi_interconnect_0 -pg 1 -lvl 3 -y 1090 -defaultsOSRD
preplace inst ps7_0_axi_periph -pg 1 -lvl 3 -y 150 -defaultsOSRD
preplace inst axi_interconnect_1 -pg 1 -lvl 3 -y 570 -defaultsOSRD
preplace inst video -pg 1 -lvl 4 -y 1120 -defaultsOSRD
preplace inst clk_wiz_0 -pg 1 -lvl 4 -y 780 -defaultsOSRD
preplace inst axi_interconnect_2 -pg 1 -lvl 3 -y 820 -defaultsOSRD
preplace inst processing_system7_0 -pg 1 -lvl 4 -y 490 -defaultsOSRD
preplace netloc S00_AXI_2 1 2 3 800 -10 NJ -10 1740
preplace netloc xlslice_2_Dout 1 5 1 NJ
preplace netloc S00_AXI_3 1 2 3 810 690 NJ 690 1740
preplace netloc VCAP_R4_0_1 1 0 4 NJ 1990 NJ 1990 NJ 1990 NJ
preplace netloc S00_AXI_4 1 2 3 810 940 NJ 940 1730
preplace netloc MNTZorro_v0_1_S00_AXI_0_arm_interrupt 1 3 2 1250 870 1750
preplace netloc VCAP_B2_0_1 1 0 4 NJ 1870 NJ 1870 NJ 1870 NJ
preplace netloc processing_system7_0_FIXED_IO 1 4 2 NJ 430 NJ
preplace netloc VCAP_VSYNC_0_1 1 0 4 NJ 1570 NJ 1570 NJ 1570 NJ
preplace netloc VCAP_B0_0_1 1 0 4 NJ 1910 NJ 1910 NJ 1910 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NCINH 1 4 2 NJ 1830 2150J
preplace netloc rst_ps7_0_25M_peripheral_aresetn 1 2 3 780 -20 1200 230 N
preplace netloc ps7_0_axi_periph_M02_AXI 1 3 2 NJ 170 N
preplace netloc VCAP_G6_0_1 1 0 4 NJ 1730 NJ 1730 NJ 1730 NJ
preplace netloc VCAP_R2_0_1 1 0 4 NJ 2030 NJ 2030 NJ 2030 NJ
preplace netloc VCAP_G5_0_1 1 0 4 NJ 1710 NJ 1710 NJ 1710 NJ
preplace netloc video_subsystem_VGA_HS 1 4 2 NJ 1090 NJ
preplace netloc axi_dwidth_converter_0_M_AXI 1 2 1 790
preplace netloc VCAP_R5_0_1 1 0 4 NJ 1970 NJ 1970 NJ 1970 NJ
preplace netloc VCAP_G3_0_1 1 0 4 NJ 1670 NJ 1670 NJ 1670 NJ
preplace netloc VCAP_R1_0_1 1 0 4 NJ 2050 NJ 2050 NJ 2050 NJ
preplace netloc ZORRO_NIORST_1 1 0 4 NJ 1490 NJ 1490 NJ 1490 NJ
preplace netloc VCAP_B3_0_1 1 0 4 NJ 1850 NJ 1850 NJ 1850 NJ
preplace netloc ZORRO_NDS0_1 1 0 4 NJ 1410 NJ 1410 NJ 1410 NJ
preplace netloc ZORRO_NDS1_1 1 0 4 NJ 1390 NJ 1390 NJ 1390 NJ
preplace netloc video_subsystem_VGA_DE 1 4 2 NJ 1130 NJ
preplace netloc VCAP_G7_0_1 1 0 4 NJ 1750 NJ 1750 NJ 1750 NJ
preplace netloc processing_system7_0_FCLK_RESET1_N 1 1 4 390 700 NJ 700 1180J 670 1730
preplace netloc VCAP_HSYNC_0_1 1 0 4 NJ 1590 NJ 1590 NJ 1590 NJ
preplace netloc processing_system7_0_DDR 1 4 2 NJ 410 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_m00_axi 1 1 4 390 -40 NJ -40 NJ -40 1770
preplace netloc VCAP_R3_0_1 1 0 4 NJ 2010 NJ 2010 NJ 2010 NJ
preplace netloc VCAP_R0_0_1 1 0 4 NJ 2070 NJ 2070 NJ 2070 NJ
preplace netloc ZORRO_NLDS_1 1 0 4 NJ 1370 NJ 1370 NJ 1370 NJ
preplace netloc axi_interconnect_1_M00_AXI 1 3 1 1160
preplace netloc VCAP_B4_0_1 1 0 4 NJ 1830 NJ 1830 NJ 1830 NJ
preplace netloc ZORRO_C28D_0_1 1 0 4 NJ 1550 NJ 1550 NJ 1550 NJ
preplace netloc ps7_0_axi_periph_M00_AXI 1 3 1 1220
preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 5 10 -30 NJ -30 NJ -30 NJ -30 1750
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_INT6 1 4 2 NJ 1690 2220J
preplace netloc xlslice_1_Dout 1 5 1 NJ
preplace netloc ps7_0_axi_periph_M01_AXI 1 3 1 1190
preplace netloc VCAP_G1_0_1 1 0 4 NJ 1630 NJ 1630 NJ 1630 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NDTACK 1 4 2 NJ 1850 2140J
preplace netloc VCAP_B5_0_1 1 0 4 NJ 1810 NJ 1810 NJ 1810 NJ
preplace netloc VCAP_G2_0_1 1 0 4 NJ 1650 NJ 1650 NJ 1650 NJ
preplace netloc video_control_vblank 1 3 2 1260 2300 1760
preplace netloc xlslice_0_Dout 1 5 1 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_ADDRDIR2 1 4 2 NJ 1750 2190J
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NSLAVE 1 4 2 NJ 1810 2160J
preplace netloc ZORRO_DOE_1 1 0 4 NJ 1470 NJ 1470 NJ 1470 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_DATADIR 1 4 2 NJ 1710 2210J
preplace netloc axi_register_slice_1_M_AXI 1 3 1 1210
preplace netloc Net 1 4 2 NJ 1650 2240J
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NBRN 1 4 2 NJ 1770 2180J
preplace netloc Net1 1 4 2 NJ 1670 2230J
preplace netloc processing_system7_0_FCLK_CLK0 1 0 5 20 230 380 250 770 450 1150 660 1740
preplace netloc VCAP_R7_0_1 1 0 4 NJ 1930 NJ 1930 NJ 1930 NJ
preplace netloc axi_interconnect_2_M00_AXI 1 3 1 1170
preplace netloc VCAP_B6_0_1 1 0 4 NJ 1790 NJ 1790 NJ 1790 NJ
preplace netloc v_axi4s_vid_out_0_vid_data 1 4 1 1780
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_ADDRDIR 1 4 2 NJ 1730 2200J
preplace netloc VCAP_G0_0_1 1 0 4 NJ 1610 NJ 1610 NJ 1610 NJ
preplace netloc VCAP_R6_0_1 1 0 4 NJ 1950 NJ 1950 NJ 1950 NJ
preplace netloc proc_sys_reset_1_peripheral_aresetn 1 1 3 390 410 790 970 1130
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NCFGOUT 1 4 2 NJ 1790 2170J
preplace netloc ZORRO_NCFGIN_1 1 0 4 NJ 1510 NJ 1510 NJ 1510 NJ
preplace netloc ZORRO_NCCS_1 1 0 4 NJ 1430 NJ 1430 NJ 1430 NJ
preplace netloc VCAP_B7_0_1 1 0 4 NJ 1770 NJ 1770 NJ 1770 NJ
preplace netloc ZORRO_NBGN_0_1 1 0 4 NJ 1310 NJ 1310 NJ 1310 NJ
preplace netloc ZORRO_E7M_1 1 0 4 NJ 1530 NJ 1530 NJ 1530 NJ
preplace netloc ZORRO_READ_1 1 0 4 NJ 1330 NJ 1330 NJ 1330 NJ
preplace netloc video_subsystem_VGA_VS 1 4 2 NJ 1110 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_video_control_op 1 3 2 1240 2290 1750
preplace netloc VCAP_B1_0_1 1 0 4 NJ 1890 NJ 1890 NJ 1890 NJ
preplace netloc axi_interconnect_0_M00_AXI 1 3 1 1140
preplace netloc S00_AXI_1 1 2 3 810 960 NJ 960 1760
preplace netloc S00_ACLK_1 1 1 4 380 640 800 950 1230 650 1780
preplace netloc MNTZorro_v0_1_S00_AXI_0_video_control_interlace 1 3 2 1270 2280 1730
preplace netloc clk_1 1 3 3 1270 680 1780 770 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_video_control_data 1 3 2 1250 2270 1740
preplace netloc ZORRO_NUDS_1 1 0 4 NJ 1350 NJ 1350 NJ 1350 NJ
preplace netloc ZORRO_NFCS_1 1 0 4 NJ 1450 NJ 1450 NJ 1450 NJ
preplace netloc VCAP_G4_0_1 1 0 4 NJ 1690 NJ 1690 NJ 1690 NJ
levelinfo -pg 1 -10 200 590 980 1500 2000 2280 -top -110 -bot 2310
"
}

@@ -1340,9 +1372,9 @@ set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files zz9000_ps.bd ]

# Create 'synth_1' run (if not found)
if {[string equal [get_runs -quiet synth_1] ""]} {
create_run -name synth_1 -part xc7z020clg400-1 -flow {Vivado Synthesis 2018} -strategy "Flow_AreaOptimized_high" -report_strategy {No Reports} -constrset constrs_1
create_run -name synth_1 -part xc7z020clg400-1 -flow {Vivado Synthesis 2018} -strategy "Flow_PerfOptimized_high" -report_strategy {No Reports} -constrset constrs_1
} else {
set_property strategy "Flow_AreaOptimized_high" [get_runs synth_1]
set_property strategy "Flow_PerfOptimized_high" [get_runs synth_1]
set_property flow "Vivado Synthesis 2018" [get_runs synth_1]
}
set obj [get_runs synth_1]
@@ -1360,9 +1392,13 @@ set_property -name "display_name" -value "synth_1_synth_report_utilization_0" -o
}
set obj [get_runs synth_1]
set_property -name "part" -value "xc7z020clg400-1" -objects $obj
set_property -name "strategy" -value "Flow_AreaOptimized_high" -objects $obj
set_property -name "steps.synth_design.args.directive" -value "AreaOptimized_high" -objects $obj
set_property -name "steps.synth_design.args.control_set_opt_threshold" -value "1" -objects $obj
set_property -name "strategy" -value "Flow_PerfOptimized_high" -objects $obj
set_property -name "steps.synth_design.args.fanout_limit" -value "400" -objects $obj
set_property -name "steps.synth_design.args.fsm_extraction" -value "one_hot" -objects $obj
set_property -name "steps.synth_design.args.keep_equivalent_registers" -value "1" -objects $obj
set_property -name "steps.synth_design.args.resource_sharing" -value "off" -objects $obj
set_property -name "steps.synth_design.args.no_lc" -value "1" -objects $obj
set_property -name "steps.synth_design.args.shreg_min_size" -value "5" -objects $obj

# set the current synth run
current_run -synthesis [get_runs synth_1]


+ 0
- 1033
zz9000_ps.tcl
File diff suppressed because it is too large
View File


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