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branch out videocap into another HP AXI port, HP1

axi-dma-writes
mntmn 4 months ago
parent
commit
c42ee4264b
2 changed files with 52 additions and 23 deletions
  1. 1
    11
      ZZ9000_proto.sdk/ZZ9000Test/src/main.c
  2. 51
    12
      mntzorro.v

+ 1
- 11
ZZ9000_proto.sdk/ZZ9000Test/src/main.c View File

@@ -1215,8 +1215,6 @@ int main() {
break;
}

Xil_DCacheFlush();

uint8_t* bmp_data = (uint8_t*) ((u32) framebuffer
+ blitter_src_offset);

@@ -1311,8 +1309,6 @@ int main() {
set_fb((uint32_t*) ((u32) framebuffer + blitter_dst_offset),
blitter_dst_pitch);

Xil_DCacheFlush();

switch (zdata) {
case 1: // Regular BlitRect
copy_rect(rect_x1, rect_y1, rect_x2, rect_y2, rect_x3,
@@ -1329,6 +1325,7 @@ int main() {
blitter_src_pitch);
break;
}

break;

case MNT_BASE_RECTOP + 0x16: {
@@ -1363,8 +1360,6 @@ int main() {
printf("blitter_src_pitch: %d\n\n", blitter_src_pitch);*/
}

Xil_DCacheFlush();

pattern_fill_rect((blitter_colormode & 0x0F), rect_x1,
rect_y1, rect_x2, rect_y2, draw_mode, 0xff,
rect_rgb, rect_rgb2, rect_x3, rect_y3, tmpl_data,
@@ -1385,8 +1380,6 @@ int main() {
set_fb((uint32_t*) ((u32) framebuffer + blitter_dst_offset),
blitter_dst_pitch);

Xil_DCacheFlush();

p2c_rect(rect_x1, rect_y1, rect_x2, rect_y2, rect_x3,
rect_y3, num_rows, draw_mode, planes, mask,
layer_mask, blitter_src_pitch, bmp_data);
@@ -1419,15 +1412,12 @@ int main() {
set_fb((uint32_t*) ((u32) framebuffer + blitter_dst_offset),
blitter_dst_pitch);

Xil_DCacheFlush();

invert_rect(rect_x1, rect_y1, rect_x2, rect_y2,
zdata & 0xFF, blitter_colormode);
break;

// Ethernet
case MNT_BASE_ETH_TX:
Xil_DCacheFlush();
ethernet_send_result = ethernet_send_frame(zdata);
//printf("SEND frame sz: %ld res: %d\n",zdata,ethernet_send_result);
break;

+ 51
- 12
mntzorro.v View File

@@ -149,6 +149,32 @@ module MNTZorro_v0_1_S00_AXI
input wire [1 : 0] m00_axi_rresp,
input wire m00_axi_rlast,
input wire m00_axi_rvalid,*/
// HP master interface 2 to write to PS memory directly (for videocap)
input wire m01_axi_aclk,
input wire m01_axi_aresetn,
// write address channel
input wire m01_axi_awready,
output wire [`C_M00_AXI_ADDR_WIDTH-1 : 0] m01_axi_awaddr,
output reg [7:0] m01_axi_awlen,
output reg [2:0] m01_axi_awsize,
output reg [1:0] m01_axi_awburst,
output reg m01_axi_awlock,
output reg [3:0] m01_axi_awcache,
output reg [2:0] m01_axi_awprot,
output reg [3:0] m01_axi_awqos,
output wire m01_axi_awvalid,
// write channel
input wire m01_axi_wready,
output wire [`C_M00_AXI_DATA_WIDTH-1 : 0] m01_axi_wdata,
output wire [`C_M00_AXI_DATA_WIDTH/8-1 : 0] m01_axi_wstrb,
output reg m01_axi_wlast,
output wire m01_axi_wvalid,
// buffered write response channel
input wire [1 : 0] m01_axi_bresp,
input wire m01_axi_bvalid,
output reg m01_axi_bready,

// video_formatter control interface
output reg [31:0] video_control_data,
@@ -1067,9 +1093,6 @@ module MNTZorro_v0_1_S00_AXI
reg [31:0] videocap_save_addr=0;
reg [3:0] videocap_save_state=0; // FIXME
reg m00_axi_awready_reg;
reg m00_axi_wready_reg;
reg videocap_mode_sync;
reg [31:0] m00_axi_awaddr_out;
@@ -1082,20 +1105,26 @@ module MNTZorro_v0_1_S00_AXI
reg m00_axi_awvalid_z3 = 0;
reg m00_axi_wvalid_z3 = 0;
reg [3:0] m00_axi_wstrb_z3;
reg z3_axi_write = 1;
reg z3_axi_write = 0;
assign m00_axi_awaddr = (z3_axi_write ? m00_axi_awaddr_z3 : m00_axi_awaddr_out);
assign m00_axi_awvalid = (z3_axi_write ? m00_axi_awvalid_z3 : m00_axi_awvalid_out);
assign m00_axi_wdata = (z3_axi_write ? m00_axi_wdata_z3 : m00_axi_wdata_out);
assign m00_axi_wstrb = (z3_axi_write ? m00_axi_wstrb_z3 : 4'b1111);
assign m00_axi_wvalid = (z3_axi_write ? m00_axi_wvalid_z3 : m00_axi_wvalid_out);
/*assign m00_axi_awaddr = (!videocap_mode ? m00_axi_awaddr_z3 : m00_axi_awaddr_out);
assign m00_axi_awvalid = (!videocap_mode ? m00_axi_awvalid_z3 : m00_axi_awvalid_out);
assign m00_axi_wdata = (!videocap_mode ? m00_axi_wdata_z3 : m00_axi_wdata_out);
assign m00_axi_wstrb = (!videocap_mode ? m00_axi_wstrb_z3 : 4'b1111);
assign m00_axi_wvalid = (!videocap_mode ? m00_axi_wvalid_z3 : m00_axi_wvalid_out);*/
// when bypassing videocap:
/*assign m00_axi_awaddr = m00_axi_awaddr_z3;
assign m00_axi_awaddr = m00_axi_awaddr_z3;
assign m00_axi_awvalid = m00_axi_awvalid_z3;
assign m00_axi_wdata = m00_axi_wdata_z3;
assign m00_axi_wstrb = m00_axi_wstrb_z3;
assign m00_axi_wvalid = m00_axi_wvalid_z3;*/
assign m00_axi_wvalid = m00_axi_wvalid_z3;
assign m01_axi_awaddr = m00_axi_awaddr_out;
assign m01_axi_awvalid = m00_axi_awvalid_out;
assign m01_axi_wdata = m00_axi_wdata_out;
assign m01_axi_wstrb = 4'b1111;
assign m01_axi_wvalid = m00_axi_wvalid_out;
// FIXME i think this process can be dissolved
// AXI DMA arbiter
@@ -1103,12 +1132,22 @@ module MNTZorro_v0_1_S00_AXI
m00_axi_awlen <= 'h0; // 1 burst (1 write)
m00_axi_awsize <= 'h2; // 2^2 == 4 bytes
m00_axi_awburst <= 'h0; // FIXED (non incrementing)
m00_axi_awcache <= 'h1;
m00_axi_awcache <= 'h3;
m00_axi_awlock <= 'h0;
m00_axi_awprot <= 'h0;
m00_axi_awqos <= 'h0;
m00_axi_wlast <= 'h1;
m00_axi_bready <= 'h1;
m01_axi_awlen <= 'h0; // 1 burst (1 write)
m01_axi_awsize <= 'h2; // 2^2 == 4 bytes
m01_axi_awburst <= 'h0; // FIXED (non incrementing)
m01_axi_awcache <= 'h3;
m01_axi_awlock <= 'h0;
m01_axi_awprot <= 'h0;
m01_axi_awqos <= 'h0;
m01_axi_wlast <= 'h1;
m01_axi_bready <= 'h1;
end
always @(posedge S_AXI_ACLK) begin

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