@@ -0,0 +1,86 @@ | |||
proc init { cellpath otherInfo } { | |||
set cell_handle [get_bd_cells $cellpath] | |||
set all_busif [get_bd_intf_pins $cellpath/*] | |||
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] | |||
set full_sbusif_list [list ] | |||
foreach busif $all_busif { | |||
if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { | |||
set busif_param_list [list] | |||
set busif_name [get_property NAME $busif] | |||
if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { | |||
continue | |||
} | |||
foreach tparam $axi_standard_param_list { | |||
lappend busif_param_list "C_${busif_name}_${tparam}" | |||
} | |||
bd::mark_propagate_only $cell_handle $busif_param_list | |||
} | |||
} | |||
} | |||
proc pre_propagate {cellpath otherInfo } { | |||
set cell_handle [get_bd_cells $cellpath] | |||
set all_busif [get_bd_intf_pins $cellpath/*] | |||
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] | |||
foreach busif $all_busif { | |||
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { | |||
continue | |||
} | |||
if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { | |||
continue | |||
} | |||
set busif_name [get_property NAME $busif] | |||
foreach tparam $axi_standard_param_list { | |||
set busif_param_name "C_${busif_name}_${tparam}" | |||
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] | |||
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] | |||
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { | |||
if { $val_on_cell != "" } { | |||
set_property CONFIG.${tparam} $val_on_cell $busif | |||
} | |||
} | |||
} | |||
} | |||
} | |||
proc propagate {cellpath otherInfo } { | |||
set cell_handle [get_bd_cells $cellpath] | |||
set all_busif [get_bd_intf_pins $cellpath/*] | |||
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] | |||
foreach busif $all_busif { | |||
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { | |||
continue | |||
} | |||
if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { | |||
continue | |||
} | |||
set busif_name [get_property NAME $busif] | |||
foreach tparam $axi_standard_param_list { | |||
set busif_param_name "C_${busif_name}_${tparam}" | |||
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] | |||
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] | |||
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { | |||
#override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. | |||
if { $val_on_cell_intf_pin != "" } { | |||
set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle | |||
} | |||
} | |||
} | |||
} | |||
} | |||
@@ -0,0 +1,785 @@ | |||
<?xml version="1.0" encoding="UTF-8"?> | |||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> | |||
<spirit:vendor>user.org</spirit:vendor> | |||
<spirit:library>user</spirit:library> | |||
<spirit:name>MNTZorro</spirit:name> | |||
<spirit:version>1.0</spirit:version> | |||
<spirit:busInterfaces> | |||
<spirit:busInterface> | |||
<spirit:name>S00_AXI</spirit:name> | |||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/> | |||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/> | |||
<spirit:slave> | |||
<spirit:memoryMapRef spirit:memoryMapRef="S00_AXI"/> | |||
</spirit:slave> | |||
<spirit:portMaps> | |||
<spirit:portMap> | |||
<spirit:logicalPort> | |||
<spirit:name>AWADDR</spirit:name> | |||
</spirit:logicalPort> | |||
<spirit:physicalPort> | |||
<spirit:name>s00_axi_awaddr</spirit:name> | |||
</spirit:physicalPort> | |||
</spirit:portMap> | |||
<spirit:portMap> | |||
<spirit:logicalPort> | |||
<spirit:name>AWPROT</spirit:name> | |||
</spirit:logicalPort> | |||
<spirit:physicalPort> | |||
<spirit:name>s00_axi_awprot</spirit:name> | |||
</spirit:physicalPort> | |||
</spirit:portMap> | |||
<spirit:portMap> | |||
<spirit:logicalPort> | |||
<spirit:name>AWVALID</spirit:name> | |||
</spirit:logicalPort> | |||
<spirit:physicalPort> | |||
<spirit:name>s00_axi_awvalid</spirit:name> | |||
</spirit:physicalPort> | |||
</spirit:portMap> | |||
<spirit:portMap> | |||
<spirit:logicalPort> | |||
<spirit:name>AWREADY</spirit:name> | |||
</spirit:logicalPort> | |||
<spirit:physicalPort> | |||
<spirit:name>s00_axi_awready</spirit:name> | |||
</spirit:physicalPort> | |||
</spirit:portMap> | |||
<spirit:portMap> | |||
<spirit:logicalPort> | |||
<spirit:name>WDATA</spirit:name> | |||
</spirit:logicalPort> | |||
<spirit:physicalPort> | |||
<spirit:name>s00_axi_wdata</spirit:name> | |||
</spirit:physicalPort> | |||
</spirit:portMap> | |||
<spirit:portMap> | |||
<spirit:logicalPort> | |||
<spirit:name>WSTRB</spirit:name> | |||
</spirit:logicalPort> | |||
<spirit:physicalPort> | |||
<spirit:name>s00_axi_wstrb</spirit:name> | |||
</spirit:physicalPort> | |||
</spirit:portMap> | |||
<spirit:portMap> | |||
<spirit:logicalPort> | |||
<spirit:name>WVALID</spirit:name> | |||
</spirit:logicalPort> | |||
<spirit:physicalPort> | |||
<spirit:name>s00_axi_wvalid</spirit:name> | |||
</spirit:physicalPort> | |||
</spirit:portMap> | |||
<spirit:portMap> | |||
<spirit:logicalPort> | |||
<spirit:name>WREADY</spirit:name> | |||
</spirit:logicalPort> | |||
<spirit:physicalPort> | |||
<spirit:name>s00_axi_wready</spirit:name> | |||
</spirit:physicalPort> | |||
</spirit:portMap> | |||
<spirit:portMap> | |||
<spirit:logicalPort> | |||
<spirit:name>BRESP</spirit:name> | |||
</spirit:logicalPort> | |||
<spirit:physicalPort> | |||
<spirit:name>s00_axi_bresp</spirit:name> | |||
</spirit:physicalPort> | |||
</spirit:portMap> | |||
<spirit:portMap> | |||
<spirit:logicalPort> | |||
<spirit:name>BVALID</spirit:name> | |||
</spirit:logicalPort> | |||
<spirit:physicalPort> | |||
<spirit:name>s00_axi_bvalid</spirit:name> | |||
</spirit:physicalPort> | |||
</spirit:portMap> | |||
<spirit:portMap> | |||
<spirit:logicalPort> | |||
<spirit:name>BREADY</spirit:name> | |||
</spirit:logicalPort> | |||
<spirit:physicalPort> | |||
<spirit:name>s00_axi_bready</spirit:name> | |||
</spirit:physicalPort> | |||
</spirit:portMap> | |||
<spirit:portMap> | |||
<spirit:logicalPort> | |||
<spirit:name>ARADDR</spirit:name> | |||
</spirit:logicalPort> | |||
<spirit:physicalPort> | |||
<spirit:name>s00_axi_araddr</spirit:name> | |||
</spirit:physicalPort> | |||
</spirit:portMap> | |||
<spirit:portMap> | |||
<spirit:logicalPort> | |||
<spirit:name>ARPROT</spirit:name> | |||
</spirit:logicalPort> | |||
<spirit:physicalPort> | |||
<spirit:name>s00_axi_arprot</spirit:name> | |||
</spirit:physicalPort> | |||
</spirit:portMap> | |||
<spirit:portMap> | |||
<spirit:logicalPort> | |||
<spirit:name>ARVALID</spirit:name> | |||
</spirit:logicalPort> | |||
<spirit:physicalPort> | |||
<spirit:name>s00_axi_arvalid</spirit:name> | |||
</spirit:physicalPort> | |||
</spirit:portMap> | |||
<spirit:portMap> | |||
<spirit:logicalPort> | |||
<spirit:name>ARREADY</spirit:name> | |||
</spirit:logicalPort> | |||
<spirit:physicalPort> | |||
<spirit:name>s00_axi_arready</spirit:name> | |||
</spirit:physicalPort> | |||
</spirit:portMap> | |||
<spirit:portMap> | |||
<spirit:logicalPort> | |||
<spirit:name>RDATA</spirit:name> | |||
</spirit:logicalPort> | |||
<spirit:physicalPort> | |||
<spirit:name>s00_axi_rdata</spirit:name> | |||
</spirit:physicalPort> | |||
</spirit:portMap> | |||
<spirit:portMap> | |||
<spirit:logicalPort> | |||
<spirit:name>RRESP</spirit:name> | |||
</spirit:logicalPort> | |||
<spirit:physicalPort> | |||
<spirit:name>s00_axi_rresp</spirit:name> | |||
</spirit:physicalPort> | |||
</spirit:portMap> | |||
<spirit:portMap> | |||
<spirit:logicalPort> | |||
<spirit:name>RVALID</spirit:name> | |||
</spirit:logicalPort> | |||
<spirit:physicalPort> | |||
<spirit:name>s00_axi_rvalid</spirit:name> | |||
</spirit:physicalPort> | |||
</spirit:portMap> | |||
<spirit:portMap> | |||
<spirit:logicalPort> | |||
<spirit:name>RREADY</spirit:name> | |||
</spirit:logicalPort> | |||
<spirit:physicalPort> | |||
<spirit:name>s00_axi_rready</spirit:name> | |||
</spirit:physicalPort> | |||
</spirit:portMap> | |||
</spirit:portMaps> | |||
<spirit:parameters> | |||
<spirit:parameter> | |||
<spirit:name>WIZ_DATA_WIDTH</spirit:name> | |||
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_ea018de4">32</spirit:value> | |||
</spirit:parameter> | |||
<spirit:parameter> | |||
<spirit:name>WIZ_NUM_REG</spirit:name> | |||
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_NUM_REG" spirit:minimum="4" spirit:maximum="512" spirit:rangeType="long">4</spirit:value> | |||
</spirit:parameter> | |||
<spirit:parameter> | |||
<spirit:name>SUPPORTS_NARROW_BURST</spirit:name> | |||
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_pairs_ce1226b1">0</spirit:value> | |||
</spirit:parameter> | |||
</spirit:parameters> | |||
</spirit:busInterface> | |||
<spirit:busInterface> | |||
<spirit:name>S00_AXI_RST</spirit:name> | |||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/> | |||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/> | |||
<spirit:slave/> | |||
<spirit:portMaps> | |||
<spirit:portMap> | |||
<spirit:logicalPort> | |||
<spirit:name>RST</spirit:name> | |||
</spirit:logicalPort> | |||
<spirit:physicalPort> | |||
<spirit:name>s00_axi_aresetn</spirit:name> | |||
</spirit:physicalPort> | |||
</spirit:portMap> | |||
</spirit:portMaps> | |||
<spirit:parameters> | |||
<spirit:parameter> | |||
<spirit:name>POLARITY</spirit:name> | |||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_RST.POLARITY">ACTIVE_LOW</spirit:value> | |||
</spirit:parameter> | |||
</spirit:parameters> | |||
</spirit:busInterface> | |||
<spirit:busInterface> | |||
<spirit:name>S00_AXI_CLK</spirit:name> | |||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/> | |||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/> | |||
<spirit:slave/> | |||
<spirit:portMaps> | |||
<spirit:portMap> | |||
<spirit:logicalPort> | |||
<spirit:name>CLK</spirit:name> | |||
</spirit:logicalPort> | |||
<spirit:physicalPort> | |||
<spirit:name>s00_axi_aclk</spirit:name> | |||
</spirit:physicalPort> | |||
</spirit:portMap> | |||
</spirit:portMaps> | |||
<spirit:parameters> | |||
<spirit:parameter> | |||
<spirit:name>ASSOCIATED_BUSIF</spirit:name> | |||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_BUSIF">S00_AXI</spirit:value> | |||
</spirit:parameter> | |||
<spirit:parameter> | |||
<spirit:name>ASSOCIATED_RESET</spirit:name> | |||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_RESET">s00_axi_aresetn</spirit:value> | |||
</spirit:parameter> | |||
</spirit:parameters> | |||
</spirit:busInterface> | |||
</spirit:busInterfaces> | |||
<spirit:memoryMaps> | |||
<spirit:memoryMap> | |||
<spirit:name>S00_AXI</spirit:name> | |||
<spirit:addressBlock> | |||
<spirit:name>S00_AXI_reg</spirit:name> | |||
<spirit:baseAddress spirit:format="long" spirit:resolve="user">0</spirit:baseAddress> | |||
<spirit:range spirit:format="long">4096</spirit:range> | |||
<spirit:width spirit:format="long">32</spirit:width> | |||
<spirit:usage>register</spirit:usage> | |||
<spirit:parameters> | |||
<spirit:parameter> | |||
<spirit:name>OFFSET_BASE_PARAM</spirit:name> | |||
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI.S00_AXI_REG.OFFSET_BASE_PARAM">C_S00_AXI_BASEADDR</spirit:value> | |||
</spirit:parameter> | |||
<spirit:parameter> | |||
<spirit:name>OFFSET_HIGH_PARAM</spirit:name> | |||
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI.S00_AXI_REG.OFFSET_HIGH_PARAM">C_S00_AXI_HIGHADDR</spirit:value> | |||
</spirit:parameter> | |||
</spirit:parameters> | |||
</spirit:addressBlock> | |||
</spirit:memoryMap> | |||
</spirit:memoryMaps> | |||
<spirit:model> | |||
<spirit:views> | |||
<spirit:view> | |||
<spirit:name>xilinx_verilogsynthesis</spirit:name> | |||
<spirit:displayName>Verilog Synthesis</spirit:displayName> | |||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier> | |||
<spirit:language>verilog</spirit:language> | |||
<spirit:modelName>MNTZorro_v1_0</spirit:modelName> | |||
<spirit:fileSetRef> | |||
<spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName> | |||
</spirit:fileSetRef> | |||
</spirit:view> | |||
<spirit:view> | |||
<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name> | |||
<spirit:displayName>Verilog Simulation</spirit:displayName> | |||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier> | |||
<spirit:language>verilog</spirit:language> | |||
<spirit:modelName>MNTZorro_v1_0</spirit:modelName> | |||
<spirit:fileSetRef> | |||
<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName> | |||
</spirit:fileSetRef> | |||
</spirit:view> | |||
<spirit:view> | |||
<spirit:name>xilinx_softwaredriver</spirit:name> | |||
<spirit:displayName>Software Driver</spirit:displayName> | |||
<spirit:envIdentifier>:vivado.xilinx.com:sw.driver</spirit:envIdentifier> | |||
<spirit:fileSetRef> | |||
<spirit:localName>xilinx_softwaredriver_view_fileset</spirit:localName> | |||
</spirit:fileSetRef> | |||
</spirit:view> | |||
<spirit:view> | |||
<spirit:name>xilinx_xpgui</spirit:name> | |||
<spirit:displayName>UI Layout</spirit:displayName> | |||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier> | |||
<spirit:fileSetRef> | |||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName> | |||
</spirit:fileSetRef> | |||
</spirit:view> | |||
<spirit:view> | |||
<spirit:name>bd_tcl</spirit:name> | |||
<spirit:displayName>Block Diagram</spirit:displayName> | |||
<spirit:envIdentifier>:vivado.xilinx.com:block.diagram</spirit:envIdentifier> | |||
<spirit:fileSetRef> | |||
<spirit:localName>bd_tcl_view_fileset</spirit:localName> | |||
</spirit:fileSetRef> | |||
</spirit:view> | |||
</spirit:views> | |||
<spirit:ports> | |||
<spirit:port> | |||
<spirit:name>s00_axi_awaddr</spirit:name> | |||
<spirit:wire> | |||
<spirit:direction>in</spirit:direction> | |||
<spirit:vector> | |||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH'))-1)">3</spirit:left> | |||
<spirit:right spirit:format="long">0</spirit:right> | |||
</spirit:vector> | |||
<spirit:wireTypeDefs> | |||
<spirit:wireTypeDef> | |||
<spirit:typeName>wire</spirit:typeName> | |||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> | |||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> | |||
</spirit:wireTypeDef> | |||
</spirit:wireTypeDefs> | |||
</spirit:wire> | |||
</spirit:port> | |||
<spirit:port> | |||
<spirit:name>s00_axi_awprot</spirit:name> | |||
<spirit:wire> | |||
<spirit:direction>in</spirit:direction> | |||
<spirit:vector> | |||
<spirit:left spirit:format="long">2</spirit:left> | |||
<spirit:right spirit:format="long">0</spirit:right> | |||
</spirit:vector> | |||
<spirit:wireTypeDefs> | |||
<spirit:wireTypeDef> | |||
<spirit:typeName>wire</spirit:typeName> | |||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> | |||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> | |||
</spirit:wireTypeDef> | |||
</spirit:wireTypeDefs> | |||
</spirit:wire> | |||
</spirit:port> | |||
<spirit:port> | |||
<spirit:name>s00_axi_awvalid</spirit:name> | |||
<spirit:wire> | |||
<spirit:direction>in</spirit:direction> | |||
<spirit:wireTypeDefs> | |||
<spirit:wireTypeDef> | |||
<spirit:typeName>wire</spirit:typeName> | |||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> | |||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> | |||
</spirit:wireTypeDef> | |||
</spirit:wireTypeDefs> | |||
</spirit:wire> | |||
</spirit:port> | |||
<spirit:port> | |||
<spirit:name>s00_axi_awready</spirit:name> | |||
<spirit:wire> | |||
<spirit:direction>out</spirit:direction> | |||
<spirit:wireTypeDefs> | |||
<spirit:wireTypeDef> | |||
<spirit:typeName>wire</spirit:typeName> | |||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> | |||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> | |||
</spirit:wireTypeDef> | |||
</spirit:wireTypeDefs> | |||
</spirit:wire> | |||
</spirit:port> | |||
<spirit:port> | |||
<spirit:name>s00_axi_wdata</spirit:name> | |||
<spirit:wire> | |||
<spirit:direction>in</spirit:direction> | |||
<spirit:vector> | |||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH'))-1)">31</spirit:left> | |||
<spirit:right spirit:format="long">0</spirit:right> | |||
</spirit:vector> | |||
<spirit:wireTypeDefs> | |||
<spirit:wireTypeDef> | |||
<spirit:typeName>wire</spirit:typeName> | |||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> | |||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> | |||
</spirit:wireTypeDef> | |||
</spirit:wireTypeDefs> | |||
</spirit:wire> | |||
</spirit:port> | |||
<spirit:port> | |||
<spirit:name>s00_axi_wstrb</spirit:name> | |||
<spirit:wire> | |||
<spirit:direction>in</spirit:direction> | |||
<spirit:vector> | |||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH'))/8)-1)">3</spirit:left> | |||
<spirit:right spirit:format="long">0</spirit:right> | |||
</spirit:vector> | |||
<spirit:wireTypeDefs> | |||
<spirit:wireTypeDef> | |||
<spirit:typeName>wire</spirit:typeName> | |||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> | |||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> | |||
</spirit:wireTypeDef> | |||
</spirit:wireTypeDefs> | |||
</spirit:wire> | |||
</spirit:port> | |||
<spirit:port> | |||
<spirit:name>s00_axi_wvalid</spirit:name> | |||
<spirit:wire> | |||
<spirit:direction>in</spirit:direction> | |||
<spirit:wireTypeDefs> | |||
<spirit:wireTypeDef> | |||
<spirit:typeName>wire</spirit:typeName> | |||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> | |||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> | |||
</spirit:wireTypeDef> | |||
</spirit:wireTypeDefs> | |||
</spirit:wire> | |||
</spirit:port> | |||
<spirit:port> | |||
<spirit:name>s00_axi_wready</spirit:name> | |||
<spirit:wire> | |||
<spirit:direction>out</spirit:direction> | |||
<spirit:wireTypeDefs> | |||
<spirit:wireTypeDef> | |||
<spirit:typeName>wire</spirit:typeName> | |||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> | |||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> | |||
</spirit:wireTypeDef> | |||
</spirit:wireTypeDefs> | |||
</spirit:wire> | |||
</spirit:port> | |||
<spirit:port> | |||
<spirit:name>s00_axi_bresp</spirit:name> | |||
<spirit:wire> | |||
<spirit:direction>out</spirit:direction> | |||
<spirit:vector> | |||
<spirit:left spirit:format="long">1</spirit:left> | |||
<spirit:right spirit:format="long">0</spirit:right> | |||
</spirit:vector> | |||
<spirit:wireTypeDefs> | |||
<spirit:wireTypeDef> | |||
<spirit:typeName>wire</spirit:typeName> | |||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> | |||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> | |||
</spirit:wireTypeDef> | |||
</spirit:wireTypeDefs> | |||
</spirit:wire> | |||
</spirit:port> | |||
<spirit:port> | |||
<spirit:name>s00_axi_bvalid</spirit:name> | |||
<spirit:wire> | |||
<spirit:direction>out</spirit:direction> | |||
<spirit:wireTypeDefs> | |||
<spirit:wireTypeDef> | |||
<spirit:typeName>wire</spirit:typeName> | |||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> | |||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> | |||
</spirit:wireTypeDef> | |||
</spirit:wireTypeDefs> | |||
</spirit:wire> | |||
</spirit:port> | |||
<spirit:port> | |||
<spirit:name>s00_axi_bready</spirit:name> | |||
<spirit:wire> | |||
<spirit:direction>in</spirit:direction> | |||
<spirit:wireTypeDefs> | |||
<spirit:wireTypeDef> | |||
<spirit:typeName>wire</spirit:typeName> | |||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> | |||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> | |||
</spirit:wireTypeDef> | |||
</spirit:wireTypeDefs> | |||
</spirit:wire> | |||
</spirit:port> | |||
<spirit:port> | |||
<spirit:name>s00_axi_araddr</spirit:name> | |||
<spirit:wire> | |||
<spirit:direction>in</spirit:direction> | |||
<spirit:vector> | |||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH'))-1)">3</spirit:left> | |||
<spirit:right spirit:format="long">0</spirit:right> | |||
</spirit:vector> | |||
<spirit:wireTypeDefs> | |||
<spirit:wireTypeDef> | |||
<spirit:typeName>wire</spirit:typeName> | |||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> | |||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> | |||
</spirit:wireTypeDef> | |||
</spirit:wireTypeDefs> | |||
</spirit:wire> | |||
</spirit:port> | |||
<spirit:port> | |||
<spirit:name>s00_axi_arprot</spirit:name> | |||
<spirit:wire> | |||
<spirit:direction>in</spirit:direction> | |||
<spirit:vector> | |||
<spirit:left spirit:format="long">2</spirit:left> | |||
<spirit:right spirit:format="long">0</spirit:right> | |||
</spirit:vector> | |||
<spirit:wireTypeDefs> | |||
<spirit:wireTypeDef> | |||
<spirit:typeName>wire</spirit:typeName> | |||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> | |||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> | |||
</spirit:wireTypeDef> | |||
</spirit:wireTypeDefs> | |||
</spirit:wire> | |||
</spirit:port> | |||
<spirit:port> | |||
<spirit:name>s00_axi_arvalid</spirit:name> | |||
<spirit:wire> | |||
<spirit:direction>in</spirit:direction> | |||
<spirit:wireTypeDefs> | |||
<spirit:wireTypeDef> | |||
<spirit:typeName>wire</spirit:typeName> | |||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> | |||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> | |||
</spirit:wireTypeDef> | |||
</spirit:wireTypeDefs> | |||
</spirit:wire> | |||
</spirit:port> | |||
<spirit:port> | |||
<spirit:name>s00_axi_arready</spirit:name> | |||
<spirit:wire> | |||
<spirit:direction>out</spirit:direction> | |||
<spirit:wireTypeDefs> | |||
<spirit:wireTypeDef> | |||
<spirit:typeName>wire</spirit:typeName> | |||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> | |||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> | |||
</spirit:wireTypeDef> | |||
</spirit:wireTypeDefs> | |||
</spirit:wire> | |||
</spirit:port> | |||
<spirit:port> | |||
<spirit:name>s00_axi_rdata</spirit:name> | |||
<spirit:wire> | |||
<spirit:direction>out</spirit:direction> | |||
<spirit:vector> | |||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH'))-1)">31</spirit:left> | |||
<spirit:right spirit:format="long">0</spirit:right> | |||
</spirit:vector> | |||
<spirit:wireTypeDefs> | |||
<spirit:wireTypeDef> | |||
<spirit:typeName>wire</spirit:typeName> | |||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> | |||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> | |||
</spirit:wireTypeDef> | |||
</spirit:wireTypeDefs> | |||
</spirit:wire> | |||
</spirit:port> | |||
<spirit:port> | |||
<spirit:name>s00_axi_rresp</spirit:name> | |||
<spirit:wire> | |||
<spirit:direction>out</spirit:direction> | |||
<spirit:vector> | |||
<spirit:left spirit:format="long">1</spirit:left> | |||
<spirit:right spirit:format="long">0</spirit:right> | |||
</spirit:vector> | |||
<spirit:wireTypeDefs> | |||
<spirit:wireTypeDef> | |||
<spirit:typeName>wire</spirit:typeName> | |||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> | |||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> | |||
</spirit:wireTypeDef> | |||
</spirit:wireTypeDefs> | |||
</spirit:wire> | |||
</spirit:port> | |||
<spirit:port> | |||
<spirit:name>s00_axi_rvalid</spirit:name> | |||
<spirit:wire> | |||
<spirit:direction>out</spirit:direction> | |||
<spirit:wireTypeDefs> | |||
<spirit:wireTypeDef> | |||
<spirit:typeName>wire</spirit:typeName> | |||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> | |||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> | |||
</spirit:wireTypeDef> | |||
</spirit:wireTypeDefs> | |||
</spirit:wire> | |||
</spirit:port> | |||
<spirit:port> | |||
<spirit:name>s00_axi_rready</spirit:name> | |||
<spirit:wire> | |||
<spirit:direction>in</spirit:direction> | |||
<spirit:wireTypeDefs> | |||
<spirit:wireTypeDef> | |||
<spirit:typeName>wire</spirit:typeName> | |||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> | |||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> | |||
</spirit:wireTypeDef> | |||
</spirit:wireTypeDefs> | |||
</spirit:wire> | |||
</spirit:port> | |||
<spirit:port> | |||
<spirit:name>s00_axi_aclk</spirit:name> | |||
<spirit:wire> | |||
<spirit:direction>in</spirit:direction> | |||
<spirit:wireTypeDefs> | |||
<spirit:wireTypeDef> | |||
<spirit:typeName>wire</spirit:typeName> | |||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> | |||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> | |||
</spirit:wireTypeDef> | |||
</spirit:wireTypeDefs> | |||
</spirit:wire> | |||
</spirit:port> | |||
<spirit:port> | |||
<spirit:name>s00_axi_aresetn</spirit:name> | |||
<spirit:wire> | |||
<spirit:direction>in</spirit:direction> | |||
<spirit:wireTypeDefs> | |||
<spirit:wireTypeDef> | |||
<spirit:typeName>wire</spirit:typeName> | |||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> | |||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> | |||
</spirit:wireTypeDef> | |||
</spirit:wireTypeDefs> | |||
</spirit:wire> | |||
</spirit:port> | |||
</spirit:ports> | |||
<spirit:modelParameters> | |||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer"> | |||
<spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name> | |||
<spirit:displayName>C S00 AXI DATA WIDTH</spirit:displayName> | |||
<spirit:description>Width of S_AXI data bus</spirit:description> | |||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH" spirit:order="3" spirit:rangeType="long">32</spirit:value> | |||
</spirit:modelParameter> | |||
<spirit:modelParameter spirit:dataType="integer"> | |||
<spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name> | |||
<spirit:displayName>C S00 AXI ADDR WIDTH</spirit:displayName> | |||
<spirit:description>Width of S_AXI address bus</spirit:description> | |||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="4" spirit:rangeType="long">4</spirit:value> | |||
</spirit:modelParameter> | |||
</spirit:modelParameters> | |||
</spirit:model> | |||
<spirit:choices> | |||
<spirit:choice> | |||
<spirit:name>choice_list_ea018de4</spirit:name> | |||
<spirit:enumeration>32</spirit:enumeration> | |||
</spirit:choice> | |||
<spirit:choice> | |||
<spirit:name>choice_pairs_ce1226b1</spirit:name> | |||
<spirit:enumeration spirit:text="true">1</spirit:enumeration> | |||
<spirit:enumeration spirit:text="false">0</spirit:enumeration> | |||
</spirit:choice> | |||
</spirit:choices> | |||
<spirit:fileSets> | |||
<spirit:fileSet> | |||
<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name> | |||
<spirit:file> | |||
<spirit:name>hdl/MNTZorro_v1_0_S00_AXI.v</spirit:name> | |||
<spirit:fileType>verilogSource</spirit:fileType> | |||
</spirit:file> | |||
<spirit:file> | |||
<spirit:name>hdl/MNTZorro_v1_0.v</spirit:name> | |||
<spirit:fileType>verilogSource</spirit:fileType> | |||
<spirit:userFileType>CHECKSUM_da4d97ba</spirit:userFileType> | |||
</spirit:file> | |||
</spirit:fileSet> | |||
<spirit:fileSet> | |||
<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name> | |||
<spirit:file> | |||
<spirit:name>hdl/MNTZorro_v1_0_S00_AXI.v</spirit:name> | |||
<spirit:fileType>verilogSource</spirit:fileType> | |||
</spirit:file> | |||
<spirit:file> | |||
<spirit:name>hdl/MNTZorro_v1_0.v</spirit:name> | |||
<spirit:fileType>verilogSource</spirit:fileType> | |||
</spirit:file> | |||
</spirit:fileSet> | |||
<spirit:fileSet> | |||
<spirit:name>xilinx_softwaredriver_view_fileset</spirit:name> | |||
<spirit:file> | |||
<spirit:name>drivers/MNTZorro_v1_0/data/MNTZorro.mdd</spirit:name> | |||
<spirit:userFileType>mdd</spirit:userFileType> | |||
<spirit:userFileType>driver_mdd</spirit:userFileType> | |||
</spirit:file> | |||
<spirit:file> | |||
<spirit:name>drivers/MNTZorro_v1_0/data/MNTZorro.tcl</spirit:name> | |||
<spirit:fileType>tclSource</spirit:fileType> | |||
<spirit:userFileType>driver_tcl</spirit:userFileType> | |||
</spirit:file> | |||
<spirit:file> | |||
<spirit:name>drivers/MNTZorro_v1_0/src/Makefile</spirit:name> | |||
<spirit:userFileType>driver_src</spirit:userFileType> | |||
</spirit:file> | |||
<spirit:file> | |||
<spirit:name>drivers/MNTZorro_v1_0/src/MNTZorro.h</spirit:name> | |||
<spirit:fileType>cSource</spirit:fileType> | |||
<spirit:userFileType>driver_src</spirit:userFileType> | |||
</spirit:file> | |||
<spirit:file> | |||
<spirit:name>drivers/MNTZorro_v1_0/src/MNTZorro.c</spirit:name> | |||
<spirit:fileType>cSource</spirit:fileType> | |||
<spirit:userFileType>driver_src</spirit:userFileType> | |||
</spirit:file> | |||
<spirit:file> | |||
<spirit:name>drivers/MNTZorro_v1_0/src/MNTZorro_selftest.c</spirit:name> | |||
<spirit:fileType>cSource</spirit:fileType> | |||
<spirit:userFileType>driver_src</spirit:userFileType> | |||
</spirit:file> | |||
</spirit:fileSet> | |||
<spirit:fileSet> | |||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name> | |||
<spirit:file> | |||
<spirit:name>xgui/MNTZorro_v1_0.tcl</spirit:name> | |||
<spirit:fileType>tclSource</spirit:fileType> | |||
<spirit:userFileType>CHECKSUM_fd592ead</spirit:userFileType> | |||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType> | |||
</spirit:file> | |||
</spirit:fileSet> | |||
<spirit:fileSet> | |||
<spirit:name>bd_tcl_view_fileset</spirit:name> | |||
<spirit:file> | |||
<spirit:name>bd/bd.tcl</spirit:name> | |||
<spirit:fileType>tclSource</spirit:fileType> | |||
</spirit:file> | |||
</spirit:fileSet> | |||
</spirit:fileSets> | |||
<spirit:description>MNT Zorro to AXI</spirit:description> | |||
<spirit:parameters> | |||
<spirit:parameter> | |||
<spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name> | |||
<spirit:displayName>C S00 AXI DATA WIDTH</spirit:displayName> | |||
<spirit:description>Width of S_AXI data bus</spirit:description> | |||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_DATA_WIDTH" spirit:choiceRef="choice_list_ea018de4" spirit:order="3">32</spirit:value> | |||
<spirit:vendorExtensions> | |||
<xilinx:parameterInfo> | |||
<xilinx:enablement> | |||
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_DATA_WIDTH">false</xilinx:isEnabled> | |||
</xilinx:enablement> | |||
</xilinx:parameterInfo> | |||
</spirit:vendorExtensions> | |||
</spirit:parameter> | |||
<spirit:parameter> | |||
<spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name> | |||
<spirit:displayName>C S00 AXI ADDR WIDTH</spirit:displayName> | |||
<spirit:description>Width of S_AXI address bus</spirit:description> | |||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="4" spirit:rangeType="long">4</spirit:value> | |||
<spirit:vendorExtensions> | |||
<xilinx:parameterInfo> | |||
<xilinx:enablement> | |||
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_ADDR_WIDTH">false</xilinx:isEnabled> | |||
</xilinx:enablement> | |||
</xilinx:parameterInfo> | |||
</spirit:vendorExtensions> | |||
</spirit:parameter> | |||
<spirit:parameter> | |||
<spirit:name>C_S00_AXI_BASEADDR</spirit:name> | |||
<spirit:displayName>C S00 AXI BASEADDR</spirit:displayName> | |||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_BASEADDR" spirit:order="5" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value> | |||
<spirit:vendorExtensions> | |||
<xilinx:parameterInfo> | |||
<xilinx:enablement> | |||
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_BASEADDR">false</xilinx:isEnabled> | |||
</xilinx:enablement> | |||
</xilinx:parameterInfo> | |||
</spirit:vendorExtensions> | |||
</spirit:parameter> | |||
<spirit:parameter> | |||
<spirit:name>C_S00_AXI_HIGHADDR</spirit:name> | |||
<spirit:displayName>C S00 AXI HIGHADDR</spirit:displayName> | |||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_HIGHADDR" spirit:order="6" spirit:bitStringLength="32">0x00000000</spirit:value> | |||
<spirit:vendorExtensions> | |||
<xilinx:parameterInfo> | |||
<xilinx:enablement> | |||
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_HIGHADDR">false</xilinx:isEnabled> | |||
</xilinx:enablement> | |||
</xilinx:parameterInfo> | |||
</spirit:vendorExtensions> | |||
</spirit:parameter> | |||
<spirit:parameter> | |||
<spirit:name>Component_Name</spirit:name> | |||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">MNTZorro_v1_0</spirit:value> | |||
</spirit:parameter> | |||
</spirit:parameters> | |||
<spirit:vendorExtensions> | |||
<xilinx:coreExtensions> | |||
<xilinx:supportedFamilies> | |||
<xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family> | |||
</xilinx:supportedFamilies> | |||
<xilinx:taxonomies> | |||
<xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy> | |||
</xilinx:taxonomies> | |||
<xilinx:displayName>MNTZorro_v1.0</xilinx:displayName> | |||
<xilinx:coreRevision>1</xilinx:coreRevision> | |||
<xilinx:coreCreationDateTime>2019-01-07T20:54:57Z</xilinx:coreCreationDateTime> | |||
</xilinx:coreExtensions> | |||
<xilinx:packagingInfo> | |||
<xilinx:xilinxVersion>2018.3</xilinx:xilinxVersion> | |||
</xilinx:packagingInfo> | |||
</spirit:vendorExtensions> | |||
</spirit:component> |
@@ -0,0 +1,10 @@ | |||
OPTION psf_version = 2.1; | |||
BEGIN DRIVER MNTZorro | |||
OPTION supported_peripherals = (MNTZorro); | |||
OPTION copyfiles = all; | |||
OPTION VERSION = 1.0; | |||
OPTION NAME = MNTZorro; | |||
END DRIVER |
@@ -0,0 +1,5 @@ | |||
proc generate {drv_handle} { | |||
xdefine_include_file $drv_handle "xparameters.h" "MNTZorro" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR" | |||
} |
@@ -0,0 +1,6 @@ | |||
/***************************** Include Files *******************************/ | |||
#include "MNTZorro.h" | |||
/************************** Function Definitions ***************************/ |
@@ -0,0 +1,79 @@ | |||
#ifndef MNTZORRO_H | |||
#define MNTZORRO_H | |||
/****************** Include Files ********************/ | |||
#include "xil_types.h" | |||
#include "xstatus.h" | |||
#define MNTZORRO_S00_AXI_SLV_REG0_OFFSET 0 | |||
#define MNTZORRO_S00_AXI_SLV_REG1_OFFSET 4 | |||
#define MNTZORRO_S00_AXI_SLV_REG2_OFFSET 8 | |||
#define MNTZORRO_S00_AXI_SLV_REG3_OFFSET 12 | |||
/**************************** Type Definitions *****************************/ | |||
/** | |||
* | |||
* Write a value to a MNTZORRO register. A 32 bit write is performed. | |||
* If the component is implemented in a smaller width, only the least | |||
* significant data is written. | |||
* | |||
* @param BaseAddress is the base address of the MNTZORROdevice. | |||
* @param RegOffset is the register offset from the base to write to. | |||
* @param Data is the data written to the register. | |||
* | |||
* @return None. | |||
* | |||
* @note | |||
* C-style signature: | |||
* void MNTZORRO_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data) | |||
* | |||
*/ | |||
#define MNTZORRO_mWriteReg(BaseAddress, RegOffset, Data) \ | |||
Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data)) | |||
/** | |||
* | |||
* Read a value from a MNTZORRO register. A 32 bit read is performed. | |||
* If the component is implemented in a smaller width, only the least | |||
* significant data is read from the register. The most significant data | |||
* will be read as 0. | |||
* | |||
* @param BaseAddress is the base address of the MNTZORRO device. | |||
* @param RegOffset is the register offset from the base to write to. | |||
* | |||
* @return Data is the data from the register. | |||
* | |||
* @note | |||
* C-style signature: | |||
* u32 MNTZORRO_mReadReg(u32 BaseAddress, unsigned RegOffset) | |||
* | |||
*/ | |||
#define MNTZORRO_mReadReg(BaseAddress, RegOffset) \ | |||
Xil_In32((BaseAddress) + (RegOffset)) | |||
/************************** Function Prototypes ****************************/ | |||
/** | |||
* | |||
* Run a self-test on the driver/device. Note this may be a destructive test if | |||
* resets of the device are performed. | |||
* | |||
* If the hardware system is not built correctly, this function may never | |||
* return to the caller. | |||
* | |||
* @param baseaddr_p is the base address of the MNTZORRO instance to be worked on. | |||
* | |||
* @return | |||
* | |||
* - XST_SUCCESS if all self-test code passed | |||
* - XST_FAILURE if any self-test code failed | |||
* | |||
* @note Caching must be turned off for this function to work. | |||
* @note Self test may fail if data memory and device are not on the same bus. | |||
* | |||
*/ | |||
XStatus MNTZORRO_Reg_SelfTest(void * baseaddr_p); | |||
#endif // MNTZORRO_H |
@@ -0,0 +1,60 @@ | |||
/***************************** Include Files *******************************/ | |||
#include "MNTZorro.h" | |||
#include "xparameters.h" | |||
#include "stdio.h" | |||
#include "xil_io.h" | |||
/************************** Constant Definitions ***************************/ | |||
#define READ_WRITE_MUL_FACTOR 0x10 | |||
/************************** Function Definitions ***************************/ | |||
/** | |||
* | |||
* Run a self-test on the driver/device. Note this may be a destructive test if | |||
* resets of the device are performed. | |||
* | |||
* If the hardware system is not built correctly, this function may never | |||
* return to the caller. | |||
* | |||
* @param baseaddr_p is the base address of the MNTZORROinstance to be worked on. | |||
* | |||
* @return | |||
* | |||
* - XST_SUCCESS if all self-test code passed | |||
* - XST_FAILURE if any self-test code failed | |||
* | |||
* @note Caching must be turned off for this function to work. | |||
* @note Self test may fail if data memory and device are not on the same bus. | |||
* | |||
*/ | |||
XStatus MNTZORRO_Reg_SelfTest(void * baseaddr_p) | |||
{ | |||
u32 baseaddr; | |||
int write_loop_index; | |||
int read_loop_index; | |||
int Index; | |||
baseaddr = (u32) baseaddr_p; | |||
xil_printf("******************************\n\r"); | |||
xil_printf("* User Peripheral Self Test\n\r"); | |||
xil_printf("******************************\n\n\r"); | |||
/* | |||
* Write to user logic slave module register(s) and read back | |||
*/ | |||
xil_printf("User logic slave module test...\n\r"); | |||
for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++) | |||
MNTZORRO_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR); | |||
for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++) | |||
if ( MNTZORRO_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){ | |||
xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4); | |||
return XST_FAILURE; | |||
} | |||
xil_printf(" - slave register write/read passed\n\n\r"); | |||
return XST_SUCCESS; | |||
} |
@@ -0,0 +1,26 @@ | |||
COMPILER= | |||
ARCHIVER= | |||
CP=cp | |||
COMPILER_FLAGS= | |||
EXTRA_COMPILER_FLAGS= | |||
LIB=libxil.a | |||
RELEASEDIR=../../../lib | |||
INCLUDEDIR=../../../include | |||
INCLUDES=-I./. -I${INCLUDEDIR} | |||
INCLUDEFILES=*.h | |||
LIBSOURCES=*.c | |||
OUTS = *.o | |||
libs: | |||
echo "Compiling MNTZorro..." | |||
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) | |||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} | |||
make clean | |||
include: | |||
${CP} $(INCLUDEFILES) $(INCLUDEDIR) | |||
clean: | |||
rm -rf ${OUTS} |
@@ -0,0 +1,197 @@ | |||
`timescale 1ns / 1ps | |||
`include "MNTZorro_v1_0_tb_include.svh" | |||
import axi_vip_pkg::*; | |||
import MNTZorro_v1_0_bfm_1_master_0_0_pkg::*; | |||
module MNTZorro_v1_0_tb(); | |||
xil_axi_uint error_cnt = 0; | |||
xil_axi_uint comparison_cnt = 0; | |||
axi_transaction wr_transaction; | |||
axi_transaction rd_transaction; | |||
axi_monitor_transaction mst_monitor_transaction; | |||
axi_monitor_transaction master_moniter_transaction_queue[$]; | |||
xil_axi_uint master_moniter_transaction_queue_size =0; | |||
axi_monitor_transaction mst_scb_transaction; | |||
axi_monitor_transaction passthrough_monitor_transaction; | |||
axi_monitor_transaction passthrough_master_moniter_transaction_queue[$]; | |||
xil_axi_uint passthrough_master_moniter_transaction_queue_size =0; | |||
axi_monitor_transaction passthrough_mst_scb_transaction; | |||
axi_monitor_transaction passthrough_slave_moniter_transaction_queue[$]; | |||
xil_axi_uint passthrough_slave_moniter_transaction_queue_size =0; | |||
axi_monitor_transaction passthrough_slv_scb_transaction; | |||
axi_monitor_transaction slv_monitor_transaction; | |||
axi_monitor_transaction slave_moniter_transaction_queue[$]; | |||
xil_axi_uint slave_moniter_transaction_queue_size =0; | |||
axi_monitor_transaction slv_scb_transaction; | |||
xil_axi_uint mst_agent_verbosity = 0; | |||
xil_axi_uint slv_agent_verbosity = 0; | |||
xil_axi_uint passthrough_agent_verbosity = 0; | |||
bit clock; | |||
bit reset; | |||
integer result_slave; | |||
bit [31:0] S00_AXI_test_data[3:0]; | |||
localparam LC_AXI_BURST_LENGTH = 8; | |||
localparam LC_AXI_DATA_WIDTH = 32; | |||
task automatic COMPARE_DATA; | |||
input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]expected; | |||
input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]actual; | |||
begin | |||
if (expected === 'hx || actual === 'hx) begin | |||
$display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!"); | |||
result_slave = 0; $stop; | |||
end | |||
if (actual != expected) begin | |||
$display("TESTBENCH ERROR! Data expected is not equal to actual.", " expected = 0x%h",expected, " actual = 0x%h",actual); | |||
result_slave = 0; | |||
$stop; | |||
end | |||
else | |||
begin | |||
$display("TESTBENCH Passed! Data expected is equal to actual.", | |||
" expected = 0x%h",expected, " actual = 0x%h",actual); | |||
end | |||
end | |||
endtask | |||
integer i; | |||
integer j; | |||
xil_axi_uint trans_cnt_before_switch = 48; | |||
xil_axi_uint passthrough_cmd_switch_cnt = 0; | |||
event passthrough_mastermode_start_event; | |||
event passthrough_mastermode_end_event; | |||
event passthrough_slavemode_end_event; | |||
xil_axi_uint mtestID; | |||
xil_axi_ulong mtestADDR; | |||
xil_axi_len_t mtestBurstLength; | |||
xil_axi_size_t mtestDataSize; | |||
xil_axi_burst_t mtestBurstType; | |||
xil_axi_lock_t mtestLOCK; | |||
xil_axi_cache_t mtestCacheType = 0; | |||
xil_axi_prot_t mtestProtectionType = 3'b000; | |||
xil_axi_region_t mtestRegion = 4'b000; | |||
xil_axi_qos_t mtestQOS = 4'b000; | |||
xil_axi_data_beat dbeat; | |||
xil_axi_data_beat [255:0] mtestWUSER; | |||
xil_axi_data_beat mtestAWUSER = 'h0; | |||
xil_axi_data_beat mtestARUSER = 0; | |||
xil_axi_data_beat [255:0] mtestRUSER; | |||
xil_axi_uint mtestBUSER = 0; | |||
xil_axi_resp_t mtestBresp; | |||
xil_axi_resp_t[255:0] mtestRresp; | |||
bit [63:0] mtestWDataL; | |||
bit [63:0] mtestRDataL; | |||
axi_transaction pss_wr_transaction; | |||
axi_transaction pss_rd_transaction; | |||
axi_transaction reactive_transaction; | |||
axi_transaction rd_payload_transaction; | |||
axi_transaction wr_rand; | |||
axi_transaction rd_rand; | |||
axi_transaction wr_reactive; | |||
axi_transaction rd_reactive; | |||
axi_transaction wr_reactive2; | |||
axi_transaction rd_reactive2; | |||
axi_ready_gen bready_gen; | |||
axi_ready_gen rready_gen; | |||
axi_ready_gen awready_gen; | |||
axi_ready_gen wready_gen; | |||
axi_ready_gen arready_gen; | |||
axi_ready_gen bready_gen2; | |||
axi_ready_gen rready_gen2; | |||
axi_ready_gen awready_gen2; | |||
axi_ready_gen wready_gen2; | |||
axi_ready_gen arready_gen2; | |||
xil_axi_payload_byte data_mem[xil_axi_ulong]; | |||
MNTZorro_v1_0_bfm_1_master_0_0_mst_t mst_agent_0; | |||
`BD_WRAPPER DUT( | |||
.ARESETN(reset), | |||
.ACLK(clock) | |||
); | |||
initial begin | |||
mst_agent_0 = new("master vip agent",DUT.`BD_INST_NAME.master_0.inst.IF);//ms | |||
mst_agent_0.vif_proxy.set_dummy_drive_type(XIL_AXI_VIF_DRIVE_NONE); | |||
mst_agent_0.set_agent_tag("Master VIP"); | |||
mst_agent_0.set_verbosity(mst_agent_verbosity); | |||
mst_agent_0.start_master(); | |||
$timeformat (-12, 1, " ps", 1); | |||
end | |||
initial begin | |||
reset <= 1'b0; | |||
#200ns; | |||
reset <= 1'b1; | |||
repeat (5) @(negedge clock); | |||
end | |||
always #5 clock <= ~clock; | |||
initial begin | |||
S_AXI_TEST ( ); | |||
#1ns; | |||
$finish; | |||
end | |||
task automatic S_AXI_TEST; | |||
begin | |||
#1; | |||
$display("Sequential write transfers example similar to AXI BFM WRITE_BURST method starts"); | |||
mtestID = 0; | |||
mtestADDR = 64'h00000000; | |||
mtestBurstLength = 0; | |||
mtestDataSize = xil_axi_size_t'(xil_clog2(32/8)); | |||
mtestBurstType = XIL_AXI_BURST_TYPE_INCR; | |||
mtestLOCK = XIL_AXI_ALOCK_NOLOCK; | |||
mtestCacheType = 0; | |||
mtestProtectionType = 0; | |||
mtestRegion = 0; | |||
mtestQOS = 0; | |||
result_slave = 1; | |||
mtestWDataL[31:0] = 32'h00000001; | |||
for(int i = 0; i < 4;i++) begin | |||
S00_AXI_test_data[i] <= mtestWDataL[31:0]; | |||
mst_agent_0.AXI4LITE_WRITE_BURST( | |||
mtestADDR, | |||
mtestProtectionType, | |||
mtestWDataL, | |||
mtestBresp | |||
); | |||
mtestWDataL[31:0] = mtestWDataL[31:0] + 1; | |||
mtestADDR = mtestADDR + 64'h4; | |||
end | |||
$display("Sequential write transfers example similar to AXI BFM WRITE_BURST method completes"); | |||
$display("Sequential read transfers example similar to AXI BFM READ_BURST method starts"); | |||
mtestID = 0; | |||
mtestADDR = 64'h00000000; | |||
mtestBurstLength = 0; | |||
mtestDataSize = xil_axi_size_t'(xil_clog2(32/8)); | |||
mtestBurstType = XIL_AXI_BURST_TYPE_INCR; | |||
mtestLOCK = XIL_AXI_ALOCK_NOLOCK; | |||
mtestCacheType = 0; | |||
mtestProtectionType = 0; | |||
mtestRegion = 0; | |||
mtestQOS = 0; | |||
for(int i = 0; i < 4;i++) begin | |||
mst_agent_0.AXI4LITE_READ_BURST( | |||
mtestADDR, | |||
mtestProtectionType, | |||
mtestRDataL, | |||
mtestRresp | |||
); | |||
mtestADDR = mtestADDR + 64'h4; | |||
COMPARE_DATA(S00_AXI_test_data[i],mtestRDataL); | |||
end | |||
$display("Sequential read transfers example similar to AXI BFM READ_BURST method completes"); | |||
$display("Sequential read transfers example similar to AXI VIP READ_BURST method completes"); | |||
$display("---------------------------------------------------------"); | |||
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!"); | |||
if ( result_slave ) begin | |||
$display("PTGEN_TEST: PASSED!"); | |||
end else begin | |||
$display("PTGEN_TEST: FAILED!"); | |||
end | |||
$display("---------------------------------------------------------"); | |||
end | |||
endtask | |||
endmodule |
@@ -0,0 +1,88 @@ | |||
proc create_ipi_design { offsetfile design_name } { | |||
create_bd_design $design_name | |||
open_bd_design $design_name | |||
# Create Clock and Reset Ports | |||
set ACLK [ create_bd_port -dir I -type clk ACLK ] | |||
set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK | |||
set ARESETN [ create_bd_port -dir I -type rst ARESETN ] | |||
set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN | |||
set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK | |||
# Create instance: MNTZorro_0, and set properties | |||
set MNTZorro_0 [ create_bd_cell -type ip -vlnv user.org:user:MNTZorro:1.0 MNTZorro_0] | |||
# Create instance: master_0, and set properties | |||
set master_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vip master_0] | |||
set_property -dict [ list CONFIG.PROTOCOL {AXI4LITE} CONFIG.INTERFACE_MODE {MASTER} ] $master_0 | |||
# Create interface connections | |||
connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI ] [get_bd_intf_pins MNTZorro_0/S00_AXI] | |||
# Create port connections | |||
connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/ACLK] [get_bd_pins MNTZorro_0/S00_AXI_ACLK] | |||
connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/ARESETN] [get_bd_pins MNTZorro_0/S00_AXI_ARESETN] | |||
set_property target_simulator XSim [current_project] | |||
set_property -name {xsim.simulate.runtime} -value {100ms} -objects [get_filesets sim_1] | |||
# Auto assign address | |||
assign_bd_address | |||
# Copy all address to interface_address.vh file | |||
set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]] | |||
upvar 1 $offsetfile offset_file | |||
set offset_file "${bd_path}/MNTZorro_v1_0_tb_include.svh" | |||
set fp [open $offset_file "w"] | |||
puts $fp "`ifndef MNTZorro_v1_0_tb_include_vh_" | |||
puts $fp "`define MNTZorro_v1_0_tb_include_vh_\n" | |||
puts $fp "//Configuration current bd names" | |||
puts $fp "`define BD_NAME ${design_name}" | |||
puts $fp "`define BD_INST_NAME ${design_name}_i" | |||
puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n" | |||
puts $fp "//Configuration address parameters" | |||
puts $fp "`endif" | |||
close $fp | |||
} | |||
set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:MNTZorro:1.0]]]] | |||
set test_bench_file ${ip_path}/example_designs/bfm_design/MNTZorro_v1_0_tb.sv | |||
set interface_address_vh_file "" | |||
# Set IP Repository and Update IP Catalogue | |||
set repo_paths [get_property ip_repo_paths [current_fileset]] | |||
if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } { | |||
set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset] | |||
update_ip_catalog | |||
} | |||
set design_name "" | |||
set all_bd {} | |||
set all_bd_files [get_files *.bd -quiet] | |||
foreach file $all_bd_files { | |||
set file_name [string range $file [expr {[string last "/" $file] + 1}] end] | |||
set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]] | |||
lappend all_bd $bd_name | |||
} | |||
for { set i 1 } { 1 } { incr i } { | |||
set design_name "MNTZorro_v1_0_bfm_${i}" | |||
if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } { | |||
break | |||
} | |||
} | |||
create_ipi_design interface_address_vh_file ${design_name} | |||
validate_bd_design | |||
set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force] | |||
import_files -force -norecurse $wrapper_file | |||
set_property SOURCE_SET sources_1 [get_filesets sim_1] | |||
import_files -fileset sim_1 -norecurse -force $test_bench_file | |||
remove_files -quiet -fileset sim_1 MNTZorro_v1_0_tb_include.vh | |||
import_files -fileset sim_1 -norecurse -force $interface_address_vh_file | |||
set_property top MNTZorro_v1_0_tb [get_filesets sim_1] | |||
set_property top_lib {} [get_filesets sim_1] | |||
set_property top_file {} [get_filesets sim_1] | |||
launch_simulation -simset sim_1 -mode behavioral |
@@ -0,0 +1,45 @@ | |||
# Runtime Tcl commands to interact with - MNTZorro_v1_0 | |||
# Sourcing design address info tcl | |||
set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd | |||
source ${bd_path}/MNTZorro_v1_0_include.tcl | |||
# jtag axi master interface hardware name, change as per your design. | |||
set jtag_axi_master hw_axi_1 | |||
set ec 0 | |||
# hw test script | |||
# Delete all previous axis transactions | |||
if { [llength [get_hw_axi_txns -quiet]] } { | |||
delete_hw_axi_txn [get_hw_axi_txns -quiet] | |||
} | |||
# Test all lite slaves. | |||
set wdata_1 abcd1234 | |||
# Test: S00_AXI | |||
# Create a write transaction at s00_axi_addr address | |||
create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1 | |||
# Create a read transaction at s00_axi_addr address | |||
create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr | |||
# Initiate transactions | |||
run_hw_axi r_s00_axi_addr | |||
run_hw_axi w_s00_axi_addr | |||
run_hw_axi r_s00_axi_addr | |||
set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]] | |||
# Compare read data | |||
if { $rdata_tmp == $wdata_1 } { | |||
puts "Data comparison test pass for - S00_AXI" | |||
} else { | |||
puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp" | |||
inc ec | |||
} | |||
# Check error flag | |||
if { $ec == 0 } { | |||
puts "PTGEN_TEST: PASSED!" | |||
} else { | |||
puts "PTGEN_TEST: FAILED!" | |||
} | |||
@@ -0,0 +1,118 @@ | |||
proc create_ipi_design { offsetfile design_name } { | |||
create_bd_design $design_name | |||
open_bd_design $design_name | |||
# Create and configure Clock/Reset | |||
create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0 | |||
create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0 | |||
#Constraints will be provided manually while pin planning. | |||
create_bd_port -dir I -type rst reset_rtl | |||
set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl] | |||
connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl] | |||
connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset] | |||
set external_reset_port reset_rtl | |||
create_bd_port -dir I -type clk clock_rtl | |||
connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl] | |||
set external_clock_port clock_rtl | |||
#Avoid IPI DRC, make clock port synchronous to reset | |||
if { $external_clock_port ne "" && $external_reset_port ne "" } { | |||
set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port] | |||
} | |||
# Connect other sys_reset pins | |||
connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1] | |||
connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked] | |||
# Create instance: MNTZorro_0, and set properties | |||
set MNTZorro_0 [ create_bd_cell -type ip -vlnv user.org:user:MNTZorro:1.0 MNTZorro_0 ] | |||
# Create instance: jtag_axi_0, and set properties | |||
set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ] | |||
set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0] | |||
connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1] | |||
connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn] | |||
# Create instance: axi_peri_interconnect, and set properties | |||
set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ] | |||
connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1] | |||
connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn] | |||
set_property -dict [ list CONFIG.NUM_SI {1} ] $axi_peri_interconnect | |||
connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1] | |||
connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn] | |||
connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI] | |||
set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect | |||
connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1] | |||
connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn] | |||
# Connect all clock & reset of MNTZorro_0 slave interfaces.. | |||
connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins MNTZorro_0/S00_AXI] | |||
connect_bd_net [get_bd_pins MNTZorro_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1] | |||
connect_bd_net [get_bd_pins MNTZorro_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn] | |||
# Auto assign address | |||
assign_bd_address | |||
# Copy all address to MNTZorro_v1_0_include.tcl file | |||
set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd | |||
upvar 1 $offsetfile offset_file | |||
set offset_file "${bd_path}/MNTZorro_v1_0_include.tcl" | |||
set fp [open $offset_file "w"] | |||
puts $fp "# Configuration address parameters" | |||
set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_MNTZorro_0_S00_AXI_* ]] | |||
puts $fp "set s00_axi_addr ${offset}" | |||
close $fp | |||
} | |||
# Set IP Repository and Update IP Catalogue | |||
set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:MNTZorro:1.0]]]] | |||
set hw_test_file ${ip_path}/example_designs/debug_hw_design/MNTZorro_v1_0_hw_test.tcl | |||
set repo_paths [get_property ip_repo_paths [current_fileset]] | |||
if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } { | |||
set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset] | |||
update_ip_catalog | |||
} | |||
set design_name "" | |||
set all_bd {} | |||
set all_bd_files [get_files *.bd -quiet] | |||
foreach file $all_bd_files { | |||
set file_name [string range $file [expr {[string last "/" $file] + 1}] end] | |||
set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]] | |||
lappend all_bd $bd_name | |||
} | |||
for { set i 1 } { 1 } { incr i } { | |||
set design_name "MNTZorro_v1_0_hw_${i}" | |||
if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } { | |||
break | |||
} | |||
} | |||
set intf_address_include_file "" | |||
create_ipi_design intf_address_include_file ${design_name} | |||
save_bd_design | |||
validate_bd_design | |||
set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force] | |||
import_files -force -norecurse $wrapper_file | |||
puts "-------------------------------------------------------------------------------------------------" | |||
puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, " | |||
puts " please perform following steps to test design in targeted board." | |||
puts "1. Generate bitstream" | |||
puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target" | |||
puts "3. Download generated bitstream" | |||
puts "4. Run generated hardware test using below command, this invokes basic read/write operation" | |||
puts " to every interface present in the peripheral : xilinx.com:user:myip:1.0" | |||
puts " : source -notrace ${hw_test_file}" | |||
puts "-------------------------------------------------------------------------------------------------" | |||
@@ -0,0 +1,78 @@ | |||
`timescale 1 ns / 1 ps | |||
module MNTZorro_v1_0 # | |||
( | |||
// Users to add parameters here | |||
// User parameters ends | |||
// Do not modify the parameters beyond this line | |||
// Parameters of Axi Slave Bus Interface S00_AXI | |||
parameter integer C_S00_AXI_DATA_WIDTH = 32, | |||
parameter integer C_S00_AXI_ADDR_WIDTH = 4 | |||
) | |||
( | |||
// Users to add ports here | |||
// User ports ends | |||
// Do not modify the ports beyond this line | |||
// Ports of Axi Slave Bus Interface S00_AXI | |||
input wire s00_axi_aclk, | |||
input wire s00_axi_aresetn, | |||
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr, | |||
input wire [2 : 0] s00_axi_awprot, | |||
input wire s00_axi_awvalid, | |||
output wire s00_axi_awready, | |||
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata, | |||
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb, | |||
input wire s00_axi_wvalid, | |||
output wire s00_axi_wready, | |||
output wire [1 : 0] s00_axi_bresp, | |||
output wire s00_axi_bvalid, | |||
input wire s00_axi_bready, | |||
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr, | |||
input wire [2 : 0] s00_axi_arprot, | |||
input wire s00_axi_arvalid, | |||
output wire s00_axi_arready, | |||
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata, | |||
output wire [1 : 0] s00_axi_rresp, | |||
output wire s00_axi_rvalid, | |||
input wire s00_axi_rready | |||
); | |||
// Instantiation of Axi Bus Interface S00_AXI | |||
MNTZorro_v1_0_S00_AXI # ( | |||
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH), | |||
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH) | |||
) MNTZorro_v1_0_S00_AXI_inst ( | |||
.S_AXI_ACLK(s00_axi_aclk), | |||
.S_AXI_ARESETN(s00_axi_aresetn), | |||
.S_AXI_AWADDR(s00_axi_awaddr), | |||
.S_AXI_AWPROT(s00_axi_awprot), | |||
.S_AXI_AWVALID(s00_axi_awvalid), | |||
.S_AXI_AWREADY(s00_axi_awready), | |||
.S_AXI_WDATA(s00_axi_wdata), | |||
.S_AXI_WSTRB(s00_axi_wstrb), | |||
.S_AXI_WVALID(s00_axi_wvalid), | |||
.S_AXI_WREADY(s00_axi_wready), | |||
.S_AXI_BRESP(s00_axi_bresp), | |||
.S_AXI_BVALID(s00_axi_bvalid), | |||
.S_AXI_BREADY(s00_axi_bready), | |||
.S_AXI_ARADDR(s00_axi_araddr), | |||
.S_AXI_ARPROT(s00_axi_arprot), | |||
.S_AXI_ARVALID(s00_axi_arvalid), | |||
.S_AXI_ARREADY(s00_axi_arready), | |||
.S_AXI_RDATA(s00_axi_rdata), | |||
.S_AXI_RRESP(s00_axi_rresp), | |||
.S_AXI_RVALID(s00_axi_rvalid), | |||
.S_AXI_RREADY(s00_axi_rready) | |||
); | |||
// Add user logic here | |||
// User logic ends | |||
endmodule |
@@ -0,0 +1,404 @@ | |||
`timescale 1 ns / 1 ps | |||
module MNTZorro_v1_0_S00_AXI # | |||
( | |||
// Users to add parameters here | |||
// User parameters ends | |||
// Do not modify the parameters beyond this line | |||
// Width of S_AXI data bus | |||
parameter integer C_S_AXI_DATA_WIDTH = 32, | |||
// Width of S_AXI address bus | |||
parameter integer C_S_AXI_ADDR_WIDTH = 4 | |||
) | |||
( | |||
// Users to add ports here | |||
// User ports ends | |||
// Do not modify the ports beyond this line | |||
// Global Clock Signal | |||
input wire S_AXI_ACLK, | |||
// Global Reset Signal. This Signal is Active LOW | |||
input wire S_AXI_ARESETN, | |||
// Write address (issued by master, acceped by Slave) | |||
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR, | |||
// Write channel Protection type. This signal indicates the | |||
// privilege and security level of the transaction, and whether | |||
// the transaction is a data access or an instruction access. | |||
input wire [2 : 0] S_AXI_AWPROT, | |||
// Write address valid. This signal indicates that the master signaling | |||
// valid write address and control information. | |||
input wire S_AXI_AWVALID, | |||
// Write address ready. This signal indicates that the slave is ready | |||
// to accept an address and associated control signals. | |||
output wire S_AXI_AWREADY, | |||
// Write data (issued by master, acceped by Slave) | |||
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA, | |||
// Write strobes. This signal indicates which byte lanes hold | |||
// valid data. There is one write strobe bit for each eight | |||
// bits of the write data bus. | |||
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB, | |||
// Write valid. This signal indicates that valid write | |||
// data and strobes are available. | |||
input wire S_AXI_WVALID, | |||
// Write ready. This signal indicates that the slave | |||
// can accept the write data. | |||
output wire S_AXI_WREADY, | |||
// Write response. This signal indicates the status | |||
// of the write transaction. | |||
output wire [1 : 0] S_AXI_BRESP, | |||
// Write response valid. This signal indicates that the channel | |||
// is signaling a valid write response. | |||
output wire S_AXI_BVALID, | |||
// Response ready. This signal indicates that the master | |||
// can accept a write response. | |||
input wire S_AXI_BREADY, | |||
// Read address (issued by master, acceped by Slave) | |||
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR, | |||
// Protection type. This signal indicates the privilege | |||
// and security level of the transaction, and whether the | |||
// transaction is a data access or an instruction access. | |||
input wire [2 : 0] S_AXI_ARPROT, | |||
// Read address valid. This signal indicates that the channel | |||
// is signaling valid read address and control information. | |||
input wire S_AXI_ARVALID, | |||
// Read address ready. This signal indicates that the slave is | |||
// ready to accept an address and associated control signals. | |||
output wire S_AXI_ARREADY, | |||
// Read data (issued by slave) | |||
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA, | |||
// Read response. This signal indicates the status of the | |||
// read transfer. | |||
output wire [1 : 0] S_AXI_RRESP, | |||
// Read valid. This signal indicates that the channel is | |||
// signaling the required read data. | |||
output wire S_AXI_RVALID, | |||
// Read ready. This signal indicates that the master can | |||
// accept the read data and response information. | |||
input wire S_AXI_RREADY | |||
); | |||
// AXI4LITE signals | |||
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr; | |||
reg axi_awready; | |||
reg axi_wready; | |||
reg [1 : 0] axi_bresp; | |||
reg axi_bvalid; | |||
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr; | |||
reg axi_arready; | |||
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata; | |||
reg [1 : 0] axi_rresp; | |||
reg axi_rvalid; | |||
// Example-specific design signals | |||
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH | |||
// ADDR_LSB is used for addressing 32/64 bit registers/memories | |||
// ADDR_LSB = 2 for 32 bits (n downto 2) | |||
// ADDR_LSB = 3 for 64 bits (n downto 3) | |||
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1; | |||
localparam integer OPT_MEM_ADDR_BITS = 1; | |||
//---------------------------------------------- | |||
//-- Signals for user logic register space example | |||
//------------------------------------------------ | |||
//-- Number of Slave Registers 4 | |||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0; | |||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1; | |||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2; | |||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3; | |||
wire slv_reg_rden; | |||
wire slv_reg_wren; | |||
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out; | |||
integer byte_index; | |||
reg aw_en; | |||
// I/O Connections assignments | |||
assign S_AXI_AWREADY = axi_awready; | |||
assign S_AXI_WREADY = axi_wready; | |||
assign S_AXI_BRESP = axi_bresp; | |||
assign S_AXI_BVALID = axi_bvalid; | |||
assign S_AXI_ARREADY = axi_arready; | |||
assign S_AXI_RDATA = axi_rdata; | |||
assign S_AXI_RRESP = axi_rresp; | |||
assign S_AXI_RVALID = axi_rvalid; | |||
// Implement axi_awready generation | |||
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both | |||
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is | |||
// de-asserted when reset is low. | |||
always @( posedge S_AXI_ACLK ) | |||
begin | |||
if ( S_AXI_ARESETN == 1'b0 ) | |||
begin | |||
axi_awready <= 1'b0; | |||
aw_en <= 1'b1; | |||
end | |||
else | |||
begin | |||
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en) | |||
begin | |||
// slave is ready to accept write address when | |||
// there is a valid write address and write data | |||
// on the write address and data bus. This design | |||
// expects no outstanding transactions. | |||
axi_awready <= 1'b1; | |||
aw_en <= 1'b0; | |||
end | |||
else if (S_AXI_BREADY && axi_bvalid) | |||
begin | |||
aw_en <= 1'b1; | |||
axi_awready <= 1'b0; | |||
end | |||
else | |||
begin | |||
axi_awready <= 1'b0; | |||
end | |||
end | |||
end | |||
// Implement axi_awaddr latching | |||
// This process is used to latch the address when both | |||
// S_AXI_AWVALID and S_AXI_WVALID are valid. | |||
always @( posedge S_AXI_ACLK ) | |||
begin | |||
if ( S_AXI_ARESETN == 1'b0 ) | |||
begin | |||
axi_awaddr <= 0; | |||
end | |||
else | |||
begin | |||
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en) | |||
begin | |||
// Write Address latching | |||
axi_awaddr <= S_AXI_AWADDR; | |||
end | |||
end | |||
end | |||
// Implement axi_wready generation | |||
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both | |||
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is | |||
// de-asserted when reset is low. | |||
always @( posedge S_AXI_ACLK ) | |||
begin | |||
if ( S_AXI_ARESETN == 1'b0 ) | |||
begin | |||
axi_wready <= 1'b0; | |||
end | |||
else | |||
begin | |||
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en ) | |||
begin | |||
// slave is ready to accept write data when | |||
// there is a valid write address and write data | |||
// on the write address and data bus. This design | |||
// expects no outstanding transactions. | |||
axi_wready <= 1'b1; | |||
end | |||
else | |||
begin | |||
axi_wready <= 1'b0; | |||
end | |||
end | |||
end | |||
// Implement memory mapped register select and write logic generation | |||
// The write data is accepted and written to memory mapped registers when | |||
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to | |||
// select byte enables of slave registers while writing. | |||
// These registers are cleared when reset (active low) is applied. | |||
// Slave register write enable is asserted when valid address and data are available | |||
// and the slave is ready to accept the write address and write data. | |||
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID; | |||
always @( posedge S_AXI_ACLK ) | |||
begin | |||
if ( S_AXI_ARESETN == 1'b0 ) | |||
begin | |||
slv_reg0 <= 0; | |||
slv_reg1 <= 0; | |||
slv_reg2 <= 0; | |||
slv_reg3 <= 0; | |||
end | |||
else begin | |||
if (slv_reg_wren) | |||
begin | |||
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) | |||
2'h0: | |||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) | |||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin | |||
// Respective byte enables are asserted as per write strobes | |||
// Slave register 0 | |||
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; | |||
end | |||
2'h1: | |||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) | |||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin | |||
// Respective byte enables are asserted as per write strobes | |||
// Slave register 1 | |||
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; | |||
end | |||
2'h2: | |||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) | |||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin | |||
// Respective byte enables are asserted as per write strobes | |||
// Slave register 2 | |||
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; | |||
end | |||
2'h3: | |||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) | |||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin | |||
// Respective byte enables are asserted as per write strobes | |||
// Slave register 3 | |||
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; | |||
end | |||
default : begin | |||
slv_reg0 <= slv_reg0; | |||
slv_reg1 <= slv_reg1; | |||
slv_reg2 <= slv_reg2; | |||
slv_reg3 <= slv_reg3; | |||
end | |||
endcase | |||
end | |||
end | |||
end | |||
// Implement write response logic generation | |||
// The write response and response valid signals are asserted by the slave | |||
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. | |||
// This marks the acceptance of address and indicates the status of | |||
// write transaction. | |||
always @( posedge S_AXI_ACLK ) | |||
begin | |||
if ( S_AXI_ARESETN == 1'b0 ) | |||
begin | |||
axi_bvalid <= 0; | |||
axi_bresp <= 2'b0; | |||
end | |||
else | |||
begin | |||
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID) | |||
begin | |||
// indicates a valid write response is available | |||
axi_bvalid <= 1'b1; | |||
axi_bresp <= 2'b0; // 'OKAY' response | |||
end // work error responses in future | |||
else | |||
begin | |||
if (S_AXI_BREADY && axi_bvalid) | |||
//check if bready is asserted while bvalid is high) | |||
//(there is a possibility that bready is always asserted high) | |||
begin | |||
axi_bvalid <= 1'b0; | |||
end | |||
end | |||
end | |||
end | |||
// Implement axi_arready generation | |||
// axi_arready is asserted for one S_AXI_ACLK clock cycle when | |||
// S_AXI_ARVALID is asserted. axi_awready is | |||
// de-asserted when reset (active low) is asserted. | |||
// The read address is also latched when S_AXI_ARVALID is | |||
// asserted. axi_araddr is reset to zero on reset assertion. | |||
always @( posedge S_AXI_ACLK ) | |||
begin | |||
if ( S_AXI_ARESETN == 1'b0 ) | |||
begin | |||
axi_arready <= 1'b0; | |||
axi_araddr <= 32'b0; | |||
end | |||
else | |||
begin | |||
if (~axi_arready && S_AXI_ARVALID) | |||
begin | |||
// indicates that the slave has acceped the valid read address | |||
axi_arready <= 1'b1; | |||
// Read address latching | |||
axi_araddr <= S_AXI_ARADDR; | |||
end | |||
else | |||
begin | |||
axi_arready <= 1'b0; | |||
end | |||
end | |||
end | |||
// Implement axi_arvalid generation | |||
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both | |||
// S_AXI_ARVALID and axi_arready are asserted. The slave registers | |||
// data are available on the axi_rdata bus at this instance. The | |||
// assertion of axi_rvalid marks the validity of read data on the | |||
// bus and axi_rresp indicates the status of read transaction.axi_rvalid | |||
// is deasserted on reset (active low). axi_rresp and axi_rdata are | |||
// cleared to zero on reset (active low). | |||
always @( posedge S_AXI_ACLK ) | |||
begin | |||
if ( S_AXI_ARESETN == 1'b0 ) | |||
begin | |||
axi_rvalid <= 0; | |||
axi_rresp <= 0; | |||
end | |||
else | |||
begin | |||
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid) | |||
begin | |||
// Valid read data is available at the read data bus | |||
axi_rvalid <= 1'b1; | |||
axi_rresp <= 2'b0; // 'OKAY' response | |||
end | |||
else if (axi_rvalid && S_AXI_RREADY) | |||
begin | |||
// Read data is accepted by the master | |||
axi_rvalid <= 1'b0; | |||
end | |||
end | |||
end | |||
// Implement memory mapped register select and read logic generation | |||
// Slave register read enable is asserted when valid address is available | |||
// and the slave is ready to accept the read address. | |||
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid; | |||
always @(*) | |||
begin | |||
// Address decoding for reading registers | |||
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) | |||
2'h0 : reg_data_out <= slv_reg0; | |||
2'h1 : reg_data_out <= slv_reg1; | |||
2'h2 : reg_data_out <= slv_reg2; | |||
2'h3 : reg_data_out <= slv_reg3; | |||
default : reg_data_out <= 0; | |||
endcase | |||
end | |||
// Output register or memory read data | |||
always @( posedge S_AXI_ACLK ) | |||
begin | |||
if ( S_AXI_ARESETN == 1'b0 ) | |||
begin | |||
axi_rdata <= 0; | |||
end | |||
else | |||
begin | |||
// When there is a valid read address (S_AXI_ARVALID) with | |||
// acceptance of read address by the slave (axi_arready), | |||
// output the read dada | |||
if (slv_reg_rden) | |||
begin | |||
axi_rdata <= reg_data_out; // register read data | |||
end | |||
end | |||
end | |||
// Add user logic here | |||
// User logic ends | |||
endmodule |
@@ -0,0 +1,62 @@ | |||
# Definitional proc to organize widgets for parameters. | |||
proc init_gui { IPINST } { | |||
ipgui::add_param $IPINST -name "Component_Name" | |||
#Adding Page | |||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"] | |||
set C_S00_AXI_DATA_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox] | |||
set_property tooltip {Width of S_AXI data bus} ${C_S00_AXI_DATA_WIDTH} | |||
set C_S00_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}] | |||
set_property tooltip {Width of S_AXI address bus} ${C_S00_AXI_ADDR_WIDTH} | |||
ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0} | |||
ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0} | |||
} | |||
proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { | |||
# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change | |||
} | |||
proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { | |||
# Procedure called to validate C_S00_AXI_DATA_WIDTH | |||
return true | |||
} | |||
proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { | |||
# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change | |||
} | |||
proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { | |||
# Procedure called to validate C_S00_AXI_ADDR_WIDTH | |||
return true | |||
} | |||
proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } { | |||
# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change | |||
} | |||
proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } { | |||
# Procedure called to validate C_S00_AXI_BASEADDR | |||
return true | |||
} | |||
proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } { | |||
# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change | |||
} | |||
proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } { | |||
# Procedure called to validate C_S00_AXI_HIGHADDR | |||
return true | |||
} | |||
proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { | |||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value | |||
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH} | |||
} | |||
proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { | |||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value | |||
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH} | |||
} | |||