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move test files around

tags/1.1
mntmn 1 month ago
parent
commit
0f184d7920
3 changed files with 69 additions and 3 deletions
  1. 0
    3
      simulate.sh
  2. 3
    0
      test/simulate.sh
  3. 66
    0
      test/testbench2.v

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- 3
simulate.sh View File

@@ -1,3 +0,0 @@
set -e
iverilog -DSIMULATION=1 -otestbench testbench.v ./video_tester.v
./testbench

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- 0
test/simulate.sh View File

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set -e
iverilog -DSIMULATION=1 -otestbench testbench.v ./video_formatter.v
./testbench

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test/testbench2.v View File

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`timescale 1ns/1ns

module testbench;
reg aclk = 0;
reg ready = 0;

reg aresetn = 0;
wire [31:0] s_axis_vid_tdata;
wire s_axis_vid_tlast;
reg s_axis_vid_tready;
wire s_axis_vid_tuser;
wire s_axis_vid_tvalid;
reg s_axis_vid_aclk;

reg [15:0] col_count = 0;
reg [15:0] last_col_count = 0;
video_tester vt(
.m_axis_vid_aclk(aclk),
.s_axis_vid_tdata(s_axis_vid_tdata),
.s_axis_vid_tlast(s_axis_vid_tlast),
.s_axis_vid_tready(ready),
.s_axis_vid_tuser(s_axis_vid_tuser),
.s_axis_vid_tvalid(s_axis_vid_tvalid)
);
initial
begin
$dumpfile("testbench.vcd");
$dumpvars(0,vt);
ready = 0;
aresetn = 1;
//$display("testbench_state: %h %t",testbench_state,$time);

#1010 ready = 0;
#1000 ready = 1;
#1000000 ready = 0;
#1000000 ready = 1;
#100 ready = 0;
#20 ready = 1;
#20 ready = 0;
#20 ready = 1;
#20 ready = 0;
#20 ready = 1;
#20 ready = 0;
#20 ready = 1;
#100000000 $finish;
end

always
begin
#10 aclk = !aclk;
if (aclk) begin
if (s_axis_vid_tvalid && ready) begin
col_count = col_count + 1;
if (s_axis_vid_tlast) begin
col_count = 0;
end
end
end
end
endmodule

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