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update gitignore; update zz9000_project.tcl for new block design

tags/1.5.1
mntmn 3 mesi fa
parent
commit
092905a6fc
38 ha cambiato i file con 213 aggiunte e 12 eliminazioni
  1. 0
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      .gitignore
  2. 0
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      ZZ9000_proto.sdk/ZZ9000OS/Debug/makefile
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      ZZ9000_proto.sdk/ZZ9000OS/Debug/objects.mk
  4. 0
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      ZZ9000_proto.sdk/ZZ9000OS/Debug/sources.mk
  5. 0
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      ZZ9000_proto.sdk/ZZ9000OS/bootimage/ZZ9000OS.bif
  6. 0
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      ZZ9000_proto.sdk/ZZ9000OS/src/Xilinx.spec
  7. 0
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      ZZ9000_proto.sdk/ZZ9000OS/src/ethernet.c
  8. 0
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      ZZ9000_proto.sdk/ZZ9000OS/src/ethernet.h
  9. 0
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      ZZ9000_proto.sdk/ZZ9000OS/src/gfx.c
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      ZZ9000_proto.sdk/ZZ9000OS/src/gfx.h
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      ZZ9000_proto.sdk/ZZ9000OS/src/lscript.ld
  12. 0
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      ZZ9000_proto.sdk/ZZ9000OS/src/main.c
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      ZZ9000_proto.sdk/ZZ9000OS/src/platform.c
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      ZZ9000_proto.sdk/ZZ9000OS/src/platform.h
  15. 0
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      ZZ9000_proto.sdk/ZZ9000OS/src/platform_config.h
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      ZZ9000_proto.sdk/ZZ9000OS/src/usb.c
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      ZZ9000_proto.sdk/ZZ9000OS/src/usb.h
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      ZZ9000_proto.sdk/ZZ9000OS/src/usb/blk.h
  19. 0
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      ZZ9000_proto.sdk/ZZ9000OS/src/usb/ehci-ci.h
  20. 0
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      ZZ9000_proto.sdk/ZZ9000OS/src/usb/ehci-hcd.c
  21. 0
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      ZZ9000_proto.sdk/ZZ9000OS/src/usb/ehci-zynq.c
  22. 0
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      ZZ9000_proto.sdk/ZZ9000OS/src/usb/ehci.h
  23. 0
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      ZZ9000_proto.sdk/ZZ9000OS/src/usb/generic-phy.h
  24. 0
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      ZZ9000_proto.sdk/ZZ9000OS/src/usb/io-generic.h
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      ZZ9000_proto.sdk/ZZ9000OS/src/usb/io.h
  26. 0
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      ZZ9000_proto.sdk/ZZ9000OS/src/usb/list.h
  27. 0
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      ZZ9000_proto.sdk/ZZ9000OS/src/usb/memalign.h
  28. 0
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      ZZ9000_proto.sdk/ZZ9000OS/src/usb/part.h
  29. 0
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      ZZ9000_proto.sdk/ZZ9000OS/src/usb/scsi.h
  30. 0
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      ZZ9000_proto.sdk/ZZ9000OS/src/usb/ulpi-viewport.c
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      ZZ9000_proto.sdk/ZZ9000OS/src/usb/ulpi.c
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      ZZ9000_proto.sdk/ZZ9000OS/src/usb/ulpi.h
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      ZZ9000_proto.sdk/ZZ9000OS/src/usb/usb.c
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      ZZ9000_proto.sdk/ZZ9000OS/src/usb/usb.h
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      ZZ9000_proto.sdk/ZZ9000OS/src/usb/usb_defs.h
  36. 0
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      ZZ9000_proto.sdk/ZZ9000OS/src/usb/usb_hub.c
  37. 0
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      ZZ9000_proto.sdk/ZZ9000OS/src/usb/usb_storage.c
  38. 213
    11
      zz9000_project.tcl

+ 0
- 1
.gitignore Vedi File

@@ -5,7 +5,6 @@ wave
*.jou
*.hdf
ZZ9000_proto.srcs/sources_1/bd
ZZ9000_proto.sdk/zz9000_ps_wrapper_hw_platform_0
ZZ9000_proto.runs
ZZ9000_proto.sim
ZZ9000_proto.hw

ZZ9000_proto.sdk/ZZ9000Test/Debug/makefile → ZZ9000_proto.sdk/ZZ9000OS/Debug/makefile Vedi File


ZZ9000_proto.sdk/ZZ9000Test/Debug/objects.mk → ZZ9000_proto.sdk/ZZ9000OS/Debug/objects.mk Vedi File


ZZ9000_proto.sdk/ZZ9000Test/Debug/sources.mk → ZZ9000_proto.sdk/ZZ9000OS/Debug/sources.mk Vedi File


ZZ9000_proto.sdk/ZZ9000Test/bootimage/ZZ9000OS.bif → ZZ9000_proto.sdk/ZZ9000OS/bootimage/ZZ9000OS.bif Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/Xilinx.spec → ZZ9000_proto.sdk/ZZ9000OS/src/Xilinx.spec Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/ethernet.c → ZZ9000_proto.sdk/ZZ9000OS/src/ethernet.c Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/ethernet.h → ZZ9000_proto.sdk/ZZ9000OS/src/ethernet.h Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/gfx.c → ZZ9000_proto.sdk/ZZ9000OS/src/gfx.c Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/gfx.h → ZZ9000_proto.sdk/ZZ9000OS/src/gfx.h Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/lscript.ld → ZZ9000_proto.sdk/ZZ9000OS/src/lscript.ld Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/main.c → ZZ9000_proto.sdk/ZZ9000OS/src/main.c Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/platform.c → ZZ9000_proto.sdk/ZZ9000OS/src/platform.c Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/platform.h → ZZ9000_proto.sdk/ZZ9000OS/src/platform.h Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/platform_config.h → ZZ9000_proto.sdk/ZZ9000OS/src/platform_config.h Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/usb.c → ZZ9000_proto.sdk/ZZ9000OS/src/usb.c Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/usb.h → ZZ9000_proto.sdk/ZZ9000OS/src/usb.h Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/usb/blk.h → ZZ9000_proto.sdk/ZZ9000OS/src/usb/blk.h Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/usb/ehci-ci.h → ZZ9000_proto.sdk/ZZ9000OS/src/usb/ehci-ci.h Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/usb/ehci-hcd.c → ZZ9000_proto.sdk/ZZ9000OS/src/usb/ehci-hcd.c Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/usb/ehci-zynq.c → ZZ9000_proto.sdk/ZZ9000OS/src/usb/ehci-zynq.c Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/usb/ehci.h → ZZ9000_proto.sdk/ZZ9000OS/src/usb/ehci.h Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/usb/generic-phy.h → ZZ9000_proto.sdk/ZZ9000OS/src/usb/generic-phy.h Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/usb/io-generic.h → ZZ9000_proto.sdk/ZZ9000OS/src/usb/io-generic.h Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/usb/io.h → ZZ9000_proto.sdk/ZZ9000OS/src/usb/io.h Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/usb/list.h → ZZ9000_proto.sdk/ZZ9000OS/src/usb/list.h Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/usb/memalign.h → ZZ9000_proto.sdk/ZZ9000OS/src/usb/memalign.h Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/usb/part.h → ZZ9000_proto.sdk/ZZ9000OS/src/usb/part.h Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/usb/scsi.h → ZZ9000_proto.sdk/ZZ9000OS/src/usb/scsi.h Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/usb/ulpi-viewport.c → ZZ9000_proto.sdk/ZZ9000OS/src/usb/ulpi-viewport.c Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/usb/ulpi.c → ZZ9000_proto.sdk/ZZ9000OS/src/usb/ulpi.c Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/usb/ulpi.h → ZZ9000_proto.sdk/ZZ9000OS/src/usb/ulpi.h Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/usb/usb.c → ZZ9000_proto.sdk/ZZ9000OS/src/usb/usb.c Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/usb/usb.h → ZZ9000_proto.sdk/ZZ9000OS/src/usb/usb.h Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/usb/usb_defs.h → ZZ9000_proto.sdk/ZZ9000OS/src/usb/usb_defs.h Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/usb/usb_hub.c → ZZ9000_proto.sdk/ZZ9000OS/src/usb/usb_hub.c Vedi File


ZZ9000_proto.sdk/ZZ9000Test/src/usb/usb_storage.c → ZZ9000_proto.sdk/ZZ9000OS/src/usb/usb_storage.c Vedi File


+ 213
- 11
zz9000_project.tcl Vedi File

@@ -3,7 +3,7 @@
#
# zz9000_project.tcl: Tcl script for re-creating project 'ZZ9000_proto'
#
# Generated by Vivado on Thu Sep 12 17:01:16 CEST 2019
# Generated by Vivado on Sun Jan 05 13:42:02 CET 2020
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -206,6 +206,10 @@ if {[string equal [get_filesets -quiet sim_1] ""]} {
# Set 'sim_1' fileset object
set obj [get_filesets sim_1]
# Import local files from the original project
set files [list \
[file normalize "${origin_dir}/zz9000_ps_wrapper_func_synth.wcfg" ]\
]
set imported_files [import_files -fileset sim_1 $files]

# Set 'sim_1' fileset file properties for remote files
# None
@@ -261,6 +265,7 @@ proc cr_bd_zz9000_ps { parentCell } {
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:axi_dwidth_converter:2.1\
xilinx.com:ip:axi_protocol_converter:2.1\
xilinx.com:ip:axi_register_slice:2.1\
xilinx.com:ip:clk_wiz:6.0\
@@ -368,6 +373,7 @@ proc create_hier_cell_video { parentCell nameHier } {
create_bd_pin -dir I -from 31 -to 0 control_data
create_bd_pin -dir I control_interlace
create_bd_pin -dir I -from 7 -to 0 control_op
create_bd_pin -dir O control_vblank
create_bd_pin -dir O -from 31 -to 0 dvi_rgb
create_bd_pin -dir I -type clk m_axi_mm2s_aclk
create_bd_pin -dir I -type clk s_axi_lite_aclk
@@ -418,6 +424,7 @@ proc create_hier_cell_video { parentCell nameHier } {
connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_pins s_axi_lite_aclk] [get_bd_pins axi_vdma_0/s_axi_lite_aclk]
connect_bd_net -net rst_ps7_0_25M_peripheral_aresetn [get_bd_pins axi_resetn] [get_bd_pins axi_vdma_0/axi_resetn]
connect_bd_net -net v_axi4s_vid_out_0_vid_data [get_bd_pins dvi_rgb] [get_bd_pins video_formatter_0/dvi_rgb]
connect_bd_net -net video_formatter_0_control_vblank [get_bd_pins control_vblank] [get_bd_pins video_formatter_0/control_vblank]
connect_bd_net -net video_subsystem_VGA_DE [get_bd_pins VGA_DE] [get_bd_pins video_formatter_0/dvi_active_video]
connect_bd_net -net video_subsystem_VGA_HS [get_bd_pins VGA_HS] [get_bd_pins video_formatter_0/dvi_hsync]
connect_bd_net -net video_subsystem_VGA_VS [get_bd_pins VGA_VS] [get_bd_pins video_formatter_0/dvi_vsync]
@@ -526,6 +533,15 @@ proc create_hier_cell_video { parentCell nameHier } {
return 1
}
# Create instance: axi_dwidth_converter_0, and set properties
set axi_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_0 ]

# Create instance: axi_mem_intercon, and set properties
set axi_mem_intercon [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon ]
set_property -dict [ list \
CONFIG.NUM_MI {1} \
] $axi_mem_intercon

# Create instance: axi_protocol_convert_0, and set properties
set axi_protocol_convert_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_converter:2.1 axi_protocol_convert_0 ]

@@ -659,6 +675,7 @@ proc create_hier_cell_video { parentCell nameHier } {
CONFIG.PCW_EN_SDIO0 {1} \
CONFIG.PCW_EN_TTC0 {0} \
CONFIG.PCW_EN_UART1 {1} \
CONFIG.PCW_EN_USB0 {1} \
CONFIG.PCW_EN_WDT {0} \
CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
@@ -777,7 +794,7 @@ proc create_hier_cell_video { parentCell nameHier } {
CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_28_PULLUP {enabled} \
CONFIG.PCW_MIO_28_SLEW {slow} \
CONFIG.PCW_MIO_29_DIRECTION {inout} \
CONFIG.PCW_MIO_29_DIRECTION {in} \
CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_29_PULLUP {enabled} \
CONFIG.PCW_MIO_29_SLEW {slow} \
@@ -785,11 +802,11 @@ proc create_hier_cell_video { parentCell nameHier } {
CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_2_PULLUP {disabled} \
CONFIG.PCW_MIO_2_SLEW {slow} \
CONFIG.PCW_MIO_30_DIRECTION {inout} \
CONFIG.PCW_MIO_30_DIRECTION {out} \
CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_30_PULLUP {enabled} \
CONFIG.PCW_MIO_30_SLEW {slow} \
CONFIG.PCW_MIO_31_DIRECTION {inout} \
CONFIG.PCW_MIO_31_DIRECTION {in} \
CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_31_PULLUP {enabled} \
CONFIG.PCW_MIO_31_SLEW {slow} \
@@ -809,7 +826,7 @@ proc create_hier_cell_video { parentCell nameHier } {
CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_35_PULLUP {enabled} \
CONFIG.PCW_MIO_35_SLEW {slow} \
CONFIG.PCW_MIO_36_DIRECTION {inout} \
CONFIG.PCW_MIO_36_DIRECTION {in} \
CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_36_PULLUP {enabled} \
CONFIG.PCW_MIO_36_SLEW {slow} \
@@ -909,8 +926,8 @@ proc create_hier_cell_video { parentCell nameHier } {
CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_9_PULLUP {enabled} \
CONFIG.PCW_MIO_9_SLEW {slow} \
CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO#GPIO#UART 1#UART 1#I2C 0#I2C 0#Enet 0#Enet 0} \
CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#gpio[1]#gpio[2]#gpio[3]#gpio[4]#gpio[5]#gpio[6]#gpio[7]#gpio[8]#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#gpio[28]#gpio[29]#gpio[30]#gpio[31]#gpio[32]#gpio[33]#gpio[34]#gpio[35]#gpio[36]#gpio[37]#gpio[38]#gpio[39]#clk#cmd#data[0]#data[1]#data[2]#data[3]#gpio[46]#gpio[47]#tx#rx#scl#sda#mdc#mdio} \
CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO#GPIO#UART 1#UART 1#I2C 0#I2C 0#Enet 0#Enet 0} \
CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#gpio[1]#gpio[2]#gpio[3]#gpio[4]#gpio[5]#gpio[6]#gpio[7]#gpio[8]#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#gpio[46]#gpio[47]#tx#rx#scl#sda#mdc#mdio} \
CONFIG.PCW_P2F_ENET0_INTR {1} \
CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
@@ -977,13 +994,18 @@ proc create_hier_cell_video { parentCell nameHier } {
CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
CONFIG.PCW_USB0_RESET_ENABLE {0} \
CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
CONFIG.PCW_USB1_RESET_ENABLE {0} \
CONFIG.PCW_USB_RESET_ENABLE {0} \
CONFIG.PCW_USE_AXI_NONSECURE {0} \
CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {1} \
CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \
CONFIG.PCW_USE_M_AXI_GP0 {1} \
CONFIG.PCW_USE_M_AXI_GP1 {1} \
CONFIG.PCW_USE_S_AXI_ACP {1} \
CONFIG.PCW_USE_S_AXI_GP0 {0} \
CONFIG.PCW_USE_S_AXI_HP0 {1} \
CONFIG.PCW_USE_S_AXI_HP1 {1} \
@@ -1043,13 +1065,16 @@ proc create_hier_cell_video { parentCell nameHier } {

# Create interface connections
connect_bd_intf_net -intf_net MNTZorro_v0_1_S00_AXI_0_m00_axi [get_bd_intf_pins MNTZorro_v0_1_S00_AXI_0/m00_axi] [get_bd_intf_pins axi_protocol_convert_2/S_AXI]
connect_bd_intf_net -intf_net MNTZorro_v0_1_S00_AXI_0_m01_axi [get_bd_intf_pins MNTZorro_v0_1_S00_AXI_0/m01_axi] [get_bd_intf_pins axi_mem_intercon/S00_AXI]
connect_bd_intf_net -intf_net axi_dwidth_converter_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/M_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_ACP]
connect_bd_intf_net -intf_net axi_mem_intercon_M00_AXI [get_bd_intf_pins axi_mem_intercon/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP1]
connect_bd_intf_net -intf_net axi_protocol_convert_0_M_AXI [get_bd_intf_pins MNTZorro_v0_1_S00_AXI_0/S_AXI] [get_bd_intf_pins axi_protocol_convert_0/M_AXI]
connect_bd_intf_net -intf_net axi_protocol_convert_1_M_AXI [get_bd_intf_pins axi_protocol_convert_1/M_AXI] [get_bd_intf_pins axi_register_slice_1/S_AXI]
connect_bd_intf_net -intf_net axi_protocol_convert_2_M_AXI [get_bd_intf_pins axi_protocol_convert_2/M_AXI] [get_bd_intf_pins axi_register_slice_3/S_AXI]
connect_bd_intf_net -intf_net axi_register_slice_0_M_AXI [get_bd_intf_pins axi_register_slice_0/M_AXI] [get_bd_intf_pins axi_register_slice_2/S_AXI]
connect_bd_intf_net -intf_net axi_register_slice_1_M_AXI [get_bd_intf_pins axi_register_slice_1/M_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0]
connect_bd_intf_net -intf_net axi_register_slice_2_M_AXI [get_bd_intf_pins axi_protocol_convert_1/S_AXI] [get_bd_intf_pins axi_register_slice_2/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_3_M_AXI [get_bd_intf_pins axi_register_slice_3/M_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP1]
connect_bd_intf_net -intf_net axi_register_slice_3_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/S_AXI] [get_bd_intf_pins axi_register_slice_3/M_AXI]
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins axi_protocol_convert_0/S_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
@@ -1114,12 +1139,13 @@ proc create_hier_cell_video { parentCell nameHier } {
connect_bd_net -net ZORRO_NUDS_1 [get_bd_ports ZORRO_NUDS] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_NUDS]
connect_bd_net -net ZORRO_READ_1 [get_bd_ports ZORRO_READ] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/ZORRO_READ]
connect_bd_net -net clk_1 [get_bd_ports VGA_PCLK] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins video/VGA_PCLK]
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins MNTZorro_v0_1_S00_AXI_0/S_AXI_ARESETN] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/m00_axi_aresetn] [get_bd_pins axi_protocol_convert_0/aresetn] [get_bd_pins axi_protocol_convert_1/aresetn] [get_bd_pins axi_protocol_convert_2/aresetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins axi_register_slice_1/aresetn] [get_bd_pins axi_register_slice_2/aresetn] [get_bd_pins axi_register_slice_3/aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins video/aresetn]
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins MNTZorro_v0_1_S00_AXI_0/S_AXI_ACLK] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/m00_axi_aclk] [get_bd_pins axi_protocol_convert_0/aclk] [get_bd_pins axi_protocol_convert_1/aclk] [get_bd_pins axi_protocol_convert_2/aclk] [get_bd_pins axi_register_slice_0/aclk] [get_bd_pins axi_register_slice_1/aclk] [get_bd_pins axi_register_slice_2/aclk] [get_bd_pins axi_register_slice_3/aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins video/m_axi_mm2s_aclk]
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins MNTZorro_v0_1_S00_AXI_0/S_AXI_ARESETN] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/m00_axi_aresetn] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/m01_axi_aresetn] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn] [get_bd_pins axi_mem_intercon/ARESETN] [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins axi_protocol_convert_0/aresetn] [get_bd_pins axi_protocol_convert_1/aresetn] [get_bd_pins axi_protocol_convert_2/aresetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins axi_register_slice_1/aresetn] [get_bd_pins axi_register_slice_2/aresetn] [get_bd_pins axi_register_slice_3/aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins video/aresetn]
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins MNTZorro_v0_1_S00_AXI_0/S_AXI_ACLK] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/m00_axi_aclk] [get_bd_pins MNTZorro_v0_1_S00_AXI_0/m01_axi_aclk] [get_bd_pins axi_dwidth_converter_0/s_axi_aclk] [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axi_protocol_convert_0/aclk] [get_bd_pins axi_protocol_convert_1/aclk] [get_bd_pins axi_protocol_convert_2/aclk] [get_bd_pins axi_register_slice_0/aclk] [get_bd_pins axi_register_slice_1/aclk] [get_bd_pins axi_register_slice_2/aclk] [get_bd_pins axi_register_slice_3/aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_ACP_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins video/m_axi_mm2s_aclk]
connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_pins clk_wiz_0/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK1] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_25M/slowest_sync_clk] [get_bd_pins video/s_axi_lite_aclk]
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_25M/ext_reset_in]
connect_bd_net -net rst_ps7_0_25M_peripheral_aresetn [get_bd_pins clk_wiz_0/s_axi_aresetn] [get_bd_pins rst_ps7_0_25M/peripheral_aresetn] [get_bd_pins video/axi_resetn]
connect_bd_net -net v_axi4s_vid_out_0_vid_data [get_bd_pins video/dvi_rgb] [get_bd_pins xlslice_0/Din] [get_bd_pins xlslice_1/Din] [get_bd_pins xlslice_2/Din]
connect_bd_net -net video_control_vblank [get_bd_pins MNTZorro_v0_1_S00_AXI_0/video_control_vblank] [get_bd_pins video/control_vblank]
connect_bd_net -net video_subsystem_VGA_DE [get_bd_ports VGA_DE] [get_bd_pins video/VGA_DE]
connect_bd_net -net video_subsystem_VGA_HS [get_bd_ports VGA_HS] [get_bd_pins video/VGA_HS]
connect_bd_net -net video_subsystem_VGA_VS [get_bd_ports VGA_VS] [get_bd_pins video/VGA_VS]
@@ -1128,12 +1154,188 @@ proc create_hier_cell_video { parentCell nameHier } {
connect_bd_net -net xlslice_2_Dout [get_bd_ports VGA_B] [get_bd_pins xlslice_2/Dout]

# Create address segments
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces MNTZorro_v0_1_S00_AXI_0/m00_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces MNTZorro_v0_1_S00_AXI_0/m00_axi] [get_bd_addr_segs processing_system7_0/S_AXI_ACP/ACP_DDR_LOWOCM] SEG_processing_system7_0_ACP_DDR_LOWOCM
create_bd_addr_seg -range 0x00400000 -offset 0xE0000000 [get_bd_addr_spaces MNTZorro_v0_1_S00_AXI_0/m00_axi] [get_bd_addr_segs processing_system7_0/S_AXI_ACP/ACP_IOP] SEG_processing_system7_0_ACP_IOP
create_bd_addr_seg -range 0x40000000 -offset 0x40000000 [get_bd_addr_spaces MNTZorro_v0_1_S00_AXI_0/m00_axi] [get_bd_addr_segs processing_system7_0/S_AXI_ACP/ACP_M_AXI_GP0] SEG_processing_system7_0_ACP_M_AXI_GP0
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces MNTZorro_v0_1_S00_AXI_0/m00_axi] [get_bd_addr_segs processing_system7_0/S_AXI_ACP/ACP_M_AXI_GP1] SEG_processing_system7_0_ACP_M_AXI_GP1
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces MNTZorro_v0_1_S00_AXI_0/m01_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs MNTZorro_v0_1_S00_AXI_0/S_AXI/reg0] SEG_MNTZorro_v0_1_S00_AXI_0_reg0
create_bd_addr_seg -range 0x00010000 -offset 0x83000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs video/axi_vdma_0/S_AXI_LITE/Reg] SEG_axi_vdma_0_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x83C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs clk_wiz_0/s_axi_lite/Reg] SEG_clk_wiz_0_Reg
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces video/axi_vdma_0/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM

# Perform GUI Layout
regenerate_bd_layout -layout_string {
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 6.8.11 2018-08-07 bk=1.4403 VDI=40 GEI=35 GUI=JA:9.0 TLS
# -string -flagsOSRD
preplace port ZORRO_C28D -pg 1 -y 1520 -defaultsOSRD
preplace port VCAP_B7 -pg 1 -y 1740 -defaultsOSRD
preplace port VCAP_R6 -pg 1 -y 1920 -defaultsOSRD
preplace port ZORRO_NIORST -pg 1 -y 1460 -defaultsOSRD
preplace port ZORRO_NDS1 -pg 1 -y 1360 -defaultsOSRD
preplace port ZORRO_NLDS -pg 1 -y 1340 -defaultsOSRD
preplace port DDR -pg 1 -y 600 -defaultsOSRD
preplace port VCAP_R7 -pg 1 -y 1900 -defaultsOSRD
preplace port ZORRO_DATADIR -pg 1 -y 1660 -defaultsOSRD
preplace port ZORRO_NCFGIN -pg 1 -y 1480 -defaultsOSRD
preplace port ZORRO_DOE -pg 1 -y 1440 -defaultsOSRD
preplace port VGA_PCLK -pg 1 -y 80 -defaultsOSRD
preplace port ZORRO_NBRN -pg 1 -y 1720 -defaultsOSRD
preplace port VCAP_G0 -pg 1 -y 1580 -defaultsOSRD
preplace port VGA_VS -pg 1 -y 270 -defaultsOSRD
preplace port VCAP_G1 -pg 1 -y 1600 -defaultsOSRD
preplace port ZORRO_READ -pg 1 -y 1300 -defaultsOSRD
preplace port ZORRO_NCFGOUT -pg 1 -y 1740 -defaultsOSRD
preplace port VCAP_B0 -pg 1 -y 1880 -defaultsOSRD
preplace port VCAP_G2 -pg 1 -y 1620 -defaultsOSRD
preplace port ZORRO_NFCS -pg 1 -y 1420 -defaultsOSRD
preplace port ZORRO_ADDRDIR -pg 1 -y 1680 -defaultsOSRD
preplace port ZORRO_INT6 -pg 1 -y 1640 -defaultsOSRD
preplace port VCAP_R0 -pg 1 -y 2040 -defaultsOSRD
preplace port VCAP_B1 -pg 1 -y 1860 -defaultsOSRD
preplace port VCAP_G3 -pg 1 -y 1640 -defaultsOSRD
preplace port ZORRO_NUDS -pg 1 -y 1320 -defaultsOSRD
preplace port VGA_DE -pg 1 -y 290 -defaultsOSRD
preplace port VCAP_R1 -pg 1 -y 2020 -defaultsOSRD
preplace port VCAP_G4 -pg 1 -y 1660 -defaultsOSRD
preplace port VCAP_B2 -pg 1 -y 1840 -defaultsOSRD
preplace port ZORRO_NDTACK -pg 1 -y 1800 -defaultsOSRD
preplace port FIXED_IO -pg 1 -y 620 -defaultsOSRD
preplace port VCAP_R2 -pg 1 -y 2000 -defaultsOSRD
preplace port VCAP_G5 -pg 1 -y 1680 -defaultsOSRD
preplace port VCAP_VSYNC -pg 1 -y 1540 -defaultsOSRD
preplace port VCAP_B3 -pg 1 -y 1820 -defaultsOSRD
preplace port ZORRO_NCINH -pg 1 -y 1780 -defaultsOSRD
preplace port ZORRO_ADDRDIR2 -pg 1 -y 1700 -defaultsOSRD
preplace port VCAP_R3 -pg 1 -y 1980 -defaultsOSRD
preplace port VCAP_B4 -pg 1 -y 1800 -defaultsOSRD
preplace port VCAP_G6 -pg 1 -y 1700 -defaultsOSRD
preplace port VCAP_R4 -pg 1 -y 1960 -defaultsOSRD
preplace port VCAP_B5 -pg 1 -y 1780 -defaultsOSRD
preplace port VCAP_G7 -pg 1 -y 1720 -defaultsOSRD
preplace port ZORRO_E7M -pg 1 -y 1500 -defaultsOSRD
preplace port ZORRO_NSLAVE -pg 1 -y 1760 -defaultsOSRD
preplace port VGA_HS -pg 1 -y 250 -defaultsOSRD
preplace port ZORRO_NBGN -pg 1 -y 1280 -defaultsOSRD
preplace port VCAP_R5 -pg 1 -y 1940 -defaultsOSRD
preplace port VCAP_B6 -pg 1 -y 1760 -defaultsOSRD
preplace port VCAP_HSYNC -pg 1 -y 1560 -defaultsOSRD
preplace port ZORRO_NCCS -pg 1 -y 1400 -defaultsOSRD
preplace port ZORRO_NDS0 -pg 1 -y 1380 -defaultsOSRD
preplace portBus VGA_B -pg 1 -y 540 -defaultsOSRD
preplace portBus ZORRO_ADDR -pg 1 -y 1600 -defaultsOSRD
preplace portBus VGA_R -pg 1 -y 340 -defaultsOSRD
preplace portBus ZORRO_DATA -pg 1 -y 1620 -defaultsOSRD
preplace portBus VGA_G -pg 1 -y 440 -defaultsOSRD
preplace inst rst_ps7_0_25M -pg 1 -lvl 4 -y 370 -defaultsOSRD
preplace inst xlslice_0 -pg 1 -lvl 7 -y 340 -defaultsOSRD
preplace inst xlslice_1 -pg 1 -lvl 7 -y 440 -defaultsOSRD
preplace inst xlslice_2 -pg 1 -lvl 7 -y 540 -defaultsOSRD
preplace inst axi_dwidth_converter_0 -pg 1 -lvl 5 -y 760 -defaultsOSRD
preplace inst axi_register_slice_0 -pg 1 -lvl 2 -y 390 -defaultsOSRD
preplace inst proc_sys_reset_0 -pg 1 -lvl 1 -y 580 -defaultsOSRD
preplace inst axi_register_slice_1 -pg 1 -lvl 5 -y 600 -defaultsOSRD
preplace inst axi_register_slice_2 -pg 1 -lvl 3 -y 560 -defaultsOSRD
preplace inst axi_protocol_convert_0 -pg 1 -lvl 5 -y 1090 -defaultsOSRD
preplace inst axi_register_slice_3 -pg 1 -lvl 4 -y 740 -defaultsOSRD
preplace inst axi_protocol_convert_1 -pg 1 -lvl 4 -y 580 -defaultsOSRD
preplace inst MNTZorro_v0_1_S00_AXI_0 -pg 1 -lvl 6 -y 1944 -defaultsOSRD
preplace inst axi_protocol_convert_2 -pg 1 -lvl 3 -y 730 -defaultsOSRD
preplace inst ps7_0_axi_periph -pg 1 -lvl 5 -y 230 -defaultsOSRD
preplace inst video -pg 1 -lvl 6 -y 322 -defaultsOSRD
preplace inst clk_wiz_0 -pg 1 -lvl 6 -y 90 -defaultsOSRD
preplace inst axi_mem_intercon -pg 1 -lvl 7 -y 1154 -defaultsOSRD
preplace inst processing_system7_0 -pg 1 -lvl 6 -y 884 -defaultsOSRD
preplace netloc xlslice_2_Dout 1 7 1 NJ
preplace netloc axi_protocol_convert_1_M_AXI 1 4 1 N
preplace netloc VCAP_R4_0_1 1 0 6 NJ 1960 NJ 1960 NJ 1960 NJ 1960 NJ 1960 1790J
preplace netloc VCAP_B2_0_1 1 0 6 NJ 1840 NJ 1840 NJ 1840 NJ 1840 NJ 1840 1850J
preplace netloc processing_system7_0_FIXED_IO 1 6 2 2850J 620 NJ
preplace netloc VCAP_VSYNC_0_1 1 0 6 NJ 1540 NJ 1540 NJ 1540 NJ 1540 NJ 1540 2020J
preplace netloc VCAP_B0_0_1 1 0 6 NJ 1880 NJ 1880 NJ 1880 NJ 1880 NJ 1880 1830J
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NCINH 1 6 2 2850J 1780 NJ
preplace netloc rst_ps7_0_25M_peripheral_aresetn 1 4 2 NJ 410 1980
preplace netloc VCAP_G6_0_1 1 0 6 NJ 1700 NJ 1700 NJ 1700 NJ 1700 NJ 1700 1920J
preplace netloc VCAP_R2_0_1 1 0 6 NJ 2000 NJ 2000 NJ 2000 NJ 2000 NJ 2000 1770J
preplace netloc VCAP_G5_0_1 1 0 6 NJ 1680 NJ 1680 NJ 1680 NJ 1680 NJ 1680 1930J
preplace netloc video_subsystem_VGA_HS 1 6 2 2720J 250 NJ
preplace netloc video_subsystem_M_AXI_MM2S 1 1 6 390 90 NJ 90 NJ 90 NJ 90 2180J 180 2710
preplace netloc axi_dwidth_converter_0_M_AXI 1 5 1 2120
preplace netloc VCAP_R5_0_1 1 0 6 NJ 1940 NJ 1940 NJ 1940 NJ 1940 NJ 1940 1800J
preplace netloc VCAP_G3_0_1 1 0 6 NJ 1640 NJ 1640 NJ 1640 NJ 1640 NJ 1640 1950J
preplace netloc VCAP_R1_0_1 1 0 6 NJ 2020 NJ 2020 NJ 2020 NJ 2020 NJ 2020 1760J
preplace netloc ZORRO_NIORST_1 1 0 6 NJ 1460 NJ 1460 NJ 1460 NJ 1460 NJ 1460 2060J
preplace netloc axi_register_slice_2_M_AXI 1 3 1 N
preplace netloc VCAP_B3_0_1 1 0 6 NJ 1820 NJ 1820 NJ 1820 NJ 1820 NJ 1820 1860J
preplace netloc ZORRO_NDS0_1 1 0 6 NJ 1380 NJ 1380 NJ 1380 NJ 1380 NJ 1380 2100J
preplace netloc ZORRO_NDS1_1 1 0 6 NJ 1360 NJ 1360 NJ 1360 NJ 1360 NJ 1360 2110J
preplace netloc video_subsystem_VGA_DE 1 6 2 2840J 280 3650J
preplace netloc VCAP_G7_0_1 1 0 6 NJ 1720 NJ 1720 NJ 1720 NJ 1720 NJ 1720 1910J
preplace netloc VCAP_HSYNC_0_1 1 0 6 NJ 1560 NJ 1560 NJ 1560 NJ 1560 NJ 1560 2010J
preplace netloc processing_system7_0_DDR 1 6 2 2840J 600 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_m00_axi 1 2 5 690 2464 NJ 2464 NJ 2464 NJ 2464 2670
preplace netloc VCAP_R3_0_1 1 0 6 NJ 1980 NJ 1980 NJ 1980 NJ 1980 NJ 1980 1780J
preplace netloc VCAP_R0_0_1 1 0 6 NJ 2040 NJ 2040 NJ 2040 NJ 2040 NJ 2040 1750J
preplace netloc ZORRO_NLDS_1 1 0 6 NJ 1340 NJ 1340 NJ 1340 NJ 1340 NJ 1340 2120J
preplace netloc axi_protocol_convert_0_M_AXI 1 5 1 2160
preplace netloc VCAP_B4_0_1 1 0 6 NJ 1800 NJ 1800 NJ 1800 NJ 1800 NJ 1800 1870J
preplace netloc ZORRO_C28D_0_1 1 0 6 NJ 1520 NJ 1520 NJ 1520 NJ 1520 NJ 1520 2030J
preplace netloc ps7_0_axi_periph_M00_AXI 1 5 1 1970
preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 7 30 480 NJ 480 650J 460 1010 472 NJ 472 NJ 472 2700
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_INT6 1 6 2 2780J 1640 NJ
preplace netloc xlslice_1_Dout 1 7 1 NJ
preplace netloc ps7_0_axi_periph_M01_AXI 1 5 1 2180
preplace netloc VCAP_G1_0_1 1 0 6 NJ 1600 NJ 1600 NJ 1600 NJ 1600 NJ 1600 1970J
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NDTACK 1 6 2 2860J 1800 NJ
preplace netloc VCAP_B5_0_1 1 0 6 NJ 1780 NJ 1780 NJ 1780 NJ 1780 NJ 1780 1880J
preplace netloc VCAP_G2_0_1 1 0 6 NJ 1620 NJ 1620 NJ 1620 NJ 1620 NJ 1620 1960J
preplace netloc video_control_vblank 1 5 2 2170 502 2710
preplace netloc xlslice_0_Dout 1 7 1 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_ADDRDIR2 1 6 2 2810J 1700 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NSLAVE 1 6 2 2840J 1760 NJ
preplace netloc ZORRO_DOE_1 1 0 6 NJ 1440 NJ 1440 NJ 1440 NJ 1440 NJ 1440 2070J
preplace netloc axi_protocol_convert_2_M_AXI 1 3 1 1010
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_DATADIR 1 6 2 2790J 1660 NJ
preplace netloc axi_register_slice_1_M_AXI 1 5 1 2130
preplace netloc Net 1 6 2 2760J 1600 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NBRN 1 6 2 2820J 1720 NJ
preplace netloc Net1 1 6 2 2770J 1620 NJ
preplace netloc processing_system7_0_FCLK_CLK0 1 0 7 20 470 390 470 670 470 1000 500 1380 500 1990 1044 2840
preplace netloc processing_system7_0_FCLK_CLK1 1 3 4 1010 270 1380 80 2140 1034 2670
preplace netloc VCAP_R7_0_1 1 0 6 NJ 1900 NJ 1900 NJ 1900 NJ 1900 NJ 1900 1820J
preplace netloc VCAP_B6_0_1 1 0 6 NJ 1760 NJ 1760 NJ 1760 NJ 1760 NJ 1760 1890J
preplace netloc axi_register_slice_0_M_AXI 1 2 1 660
preplace netloc v_axi4s_vid_out_0_vid_data 1 6 1 2850
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_ADDRDIR 1 6 2 2800J 1680 NJ
preplace netloc VCAP_G0_0_1 1 0 6 NJ 1580 NJ 1580 NJ 1580 NJ 1580 NJ 1580 1980J
preplace netloc VCAP_R6_0_1 1 0 6 NJ 1920 NJ 1920 NJ 1920 NJ 1920 NJ 1920 1810J
preplace netloc proc_sys_reset_1_peripheral_aresetn 1 1 6 400 490 680 480 990 660 1390 680 2000 1134 2850
preplace netloc MNTZorro_v0_1_S00_AXI_0_ZORRO_NCFGOUT 1 6 2 2830J 1740 NJ
preplace netloc M00_ARESETN_1 1 4 1 1390
preplace netloc ZORRO_NCFGIN_1 1 0 6 NJ 1480 NJ 1480 NJ 1480 NJ 1480 NJ 1480 2050J
preplace netloc ZORRO_NCCS_1 1 0 6 NJ 1400 NJ 1400 NJ 1400 NJ 1400 NJ 1400 2090J
preplace netloc VCAP_B7_0_1 1 0 6 NJ 1740 NJ 1740 NJ 1740 NJ 1740 NJ 1740 1900J
preplace netloc ZORRO_NBGN_0_1 1 0 6 NJ 1280 NJ 1280 NJ 1280 NJ 1280 NJ 1280 2150J
preplace netloc processing_system7_0_M_AXI_GP0 1 4 3 1410 1170 NJ 1170 2690
preplace netloc processing_system7_0_M_AXI_GP1 1 4 3 1400 1180 NJ 1180 2680
preplace netloc ZORRO_E7M_1 1 0 6 NJ 1500 NJ 1500 NJ 1500 NJ 1500 NJ 1500 2040J
preplace netloc axi_mem_intercon_M00_AXI 1 5 3 2180 734 NJ 734 3650
preplace netloc MNTZorro_v0_1_S00_AXI_0_m01_axi 1 6 1 2750
preplace netloc ZORRO_READ_1 1 0 6 NJ 1300 NJ 1300 NJ 1300 NJ 1300 NJ 1300 2140J
preplace netloc video_subsystem_VGA_VS 1 6 2 2740J 270 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_video_control_op 1 5 2 2160 492 2720
preplace netloc axi_register_slice_3_M_AXI 1 4 1 N
preplace netloc VCAP_B1_0_1 1 0 6 NJ 1860 NJ 1860 NJ 1860 NJ 1860 NJ 1860 1840J
preplace netloc MNTZorro_v0_1_S00_AXI_0_video_control_interlace 1 5 2 2180 462 2740
preplace netloc clk_1 1 5 3 2170 452 2730 80 NJ
preplace netloc MNTZorro_v0_1_S00_AXI_0_video_control_data 1 5 2 2150 482 2730
preplace netloc ZORRO_NUDS_1 1 0 6 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ 1320 2130J
preplace netloc ZORRO_NFCS_1 1 0 6 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 2080J
preplace netloc VCAP_G4_0_1 1 0 6 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 1940J
levelinfo -pg 1 0 210 530 840 1200 1580 2450 3500 3670 -top 0 -bot 3270
"
}

# Restore current instance
current_bd_instance $oldCurInst

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