@@ -0,0 +1,18 @@ | |||
connect -url tcp:127.0.0.1:3121 | |||
source /home/mntmn/code/ZZ9000_proto/ZZ9000_proto.sdk/zz9000_ps_wrapper_hw_platform_0/ps7_init.tcl | |||
targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Platform Cable USB usb2.24"} -index 0 | |||
rst -system | |||
after 3000 | |||
targets -set -filter {jtag_cable_name =~ "Platform Cable USB usb2.24" && level==0} -index 1 | |||
fpga -file /home/mntmn/code/ZZ9000_proto/ZZ9000_proto.sdk/zz9000_ps_wrapper_hw_platform_0/zz9000_ps_wrapper.bit | |||
targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Platform Cable USB usb2.24"} -index 0 | |||
loadhw -hw /home/mntmn/code/ZZ9000_proto/ZZ9000_proto.sdk/zz9000_ps_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] | |||
configparams force-mem-access 1 | |||
targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Platform Cable USB usb2.24"} -index 0 | |||
ps7_init | |||
ps7_post_config | |||
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB usb2.24"} -index 0 | |||
dow /home/mntmn/code/ZZ9000_proto/ZZ9000_proto.sdk/ZZ9000Test/Debug/ZZ9000Test.elf | |||
configparams force-mem-access 0 | |||
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB usb2.24"} -index 0 | |||
con |
@@ -0,0 +1,18 @@ | |||
connect -url tcp:127.0.0.1:3121 | |||
source /home/mntmn/code/ZZ9000_proto/ZZ9000_proto.sdk/zz9000_ps_wrapper_hw_platform_0/ps7_init.tcl | |||
targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Platform Cable USB usb2.22"} -index 0 | |||
rst -system | |||
after 3000 | |||
targets -set -filter {jtag_cable_name =~ "Platform Cable USB usb2.22" && level==0} -index 1 | |||
fpga -file /home/mntmn/code/ZZ9000_proto/ZZ9000_proto.sdk/zz9000_ps_wrapper_hw_platform_0/zz9000_ps_wrapper.bit | |||
targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Platform Cable USB usb2.22"} -index 0 | |||
loadhw -hw /home/mntmn/code/ZZ9000_proto/ZZ9000_proto.sdk/zz9000_ps_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] | |||
configparams force-mem-access 1 | |||
targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Platform Cable USB usb2.22"} -index 0 | |||
ps7_init | |||
ps7_post_config | |||
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB usb2.22"} -index 0 | |||
dow /home/mntmn/code/ZZ9000_proto/ZZ9000_proto.sdk/ZZ9000Test/Release/ZZ9000Test.elf | |||
configparams force-mem-access 0 | |||
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB usb2.22"} -index 0 | |||
con |
@@ -0,0 +1,16 @@ | |||
connect -url tcp:127.0.0.1:3121 | |||
source /home/mntmn/code/ZZ9000_proto/ZZ9000_proto.sdk/zz9000_ps_wrapper_hw_platform_0/ps7_init.tcl | |||
targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Platform Cable USB usb1.48"} -index 0 | |||
loadhw -hw /home/mntmn/code/ZZ9000_proto/ZZ9000_proto.sdk/zz9000_ps_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] | |||
configparams force-mem-access 1 | |||
targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Platform Cable USB usb1.48"} -index 0 | |||
stop | |||
ps7_init | |||
ps7_post_config | |||
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB usb1.48"} -index 0 | |||
rst -processor | |||
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB usb1.48"} -index 0 | |||
dow /home/mntmn/code/ZZ9000_proto/ZZ9000_proto.sdk/ZZ9000Test/Debug/ZZ9000Test.elf | |||
configparams force-mem-access 0 | |||
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB usb1.48"} -index 0 | |||
con |
@@ -0,0 +1,225 @@ | |||
PARAMETER VERSION = 2.2.0 | |||
BEGIN OS | |||
PARAMETER OS_NAME = standalone | |||
PARAMETER OS_VER = 6.4 | |||
PARAMETER PROC_INSTANCE = ps7_cortexa9_0 | |||
PARAMETER stdin = ps7_uart_1 | |||
PARAMETER stdout = ps7_uart_1 | |||
END | |||
BEGIN PROCESSOR | |||
PARAMETER DRIVER_NAME = cpu_cortexa9 | |||
PARAMETER DRIVER_VER = 2.5 | |||
PARAMETER HW_INSTANCE = ps7_cortexa9_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = generic | |||
PARAMETER DRIVER_VER = 2.0 | |||
PARAMETER HW_INSTANCE = ps7_afi_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = generic | |||
PARAMETER DRIVER_VER = 2.0 | |||
PARAMETER HW_INSTANCE = ps7_afi_1 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = generic | |||
PARAMETER DRIVER_VER = 2.0 | |||
PARAMETER HW_INSTANCE = ps7_afi_2 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = generic | |||
PARAMETER DRIVER_VER = 2.0 | |||
PARAMETER HW_INSTANCE = ps7_afi_3 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = coresightps_dcc | |||
PARAMETER DRIVER_VER = 1.4 | |||
PARAMETER HW_INSTANCE = ps7_coresight_comp_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = devcfg | |||
PARAMETER DRIVER_VER = 3.5 | |||
PARAMETER HW_INSTANCE = ps7_dev_cfg_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = dmaps | |||
PARAMETER DRIVER_VER = 2.3 | |||
PARAMETER HW_INSTANCE = ps7_dma_ns | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = dmaps | |||
PARAMETER DRIVER_VER = 2.3 | |||
PARAMETER HW_INSTANCE = ps7_dma_s | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = generic | |||
PARAMETER DRIVER_VER = 2.0 | |||
PARAMETER HW_INSTANCE = ps7_globaltimer_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = generic | |||
PARAMETER DRIVER_VER = 2.0 | |||
PARAMETER HW_INSTANCE = ps7_gpv_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = generic | |||
PARAMETER DRIVER_VER = 2.0 | |||
PARAMETER HW_INSTANCE = ps7_intc_dist_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = generic | |||
PARAMETER DRIVER_VER = 2.0 | |||
PARAMETER HW_INSTANCE = ps7_iop_bus_config_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = generic | |||
PARAMETER DRIVER_VER = 2.0 | |||
PARAMETER HW_INSTANCE = ps7_l2cachec_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = generic | |||
PARAMETER DRIVER_VER = 2.0 | |||
PARAMETER HW_INSTANCE = ps7_ocmc_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = generic | |||
PARAMETER DRIVER_VER = 2.0 | |||
PARAMETER HW_INSTANCE = ps7_pl310_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = generic | |||
PARAMETER DRIVER_VER = 2.0 | |||
PARAMETER HW_INSTANCE = ps7_pmu_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = generic | |||
PARAMETER DRIVER_VER = 2.0 | |||
PARAMETER HW_INSTANCE = ps7_ram_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = generic | |||
PARAMETER DRIVER_VER = 2.0 | |||
PARAMETER HW_INSTANCE = ps7_ram_1 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = generic | |||
PARAMETER DRIVER_VER = 2.0 | |||
PARAMETER HW_INSTANCE = ps7_scuc_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = scugic | |||
PARAMETER DRIVER_VER = 3.8 | |||
PARAMETER HW_INSTANCE = ps7_scugic_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = scutimer | |||
PARAMETER DRIVER_VER = 2.1 | |||
PARAMETER HW_INSTANCE = ps7_scutimer_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = scuwdt | |||
PARAMETER DRIVER_VER = 2.1 | |||
PARAMETER HW_INSTANCE = ps7_scuwdt_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = generic | |||
PARAMETER DRIVER_VER = 2.0 | |||
PARAMETER HW_INSTANCE = ps7_slcr_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = uartps | |||
PARAMETER DRIVER_VER = 3.4 | |||
PARAMETER HW_INSTANCE = ps7_uart_1 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = xadcps | |||
PARAMETER DRIVER_VER = 2.2 | |||
PARAMETER HW_INSTANCE = ps7_xadc_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = iicps | |||
PARAMETER DRIVER_VER = 3.5 | |||
PARAMETER HW_INSTANCE = ps7_i2c_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = ddrps | |||
PARAMETER DRIVER_VER = 1.0 | |||
PARAMETER HW_INSTANCE = ps7_ddr_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = generic | |||
PARAMETER DRIVER_VER = 2.0 | |||
PARAMETER HW_INSTANCE = ps7_ddrc_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = clk_wiz | |||
PARAMETER DRIVER_VER = 1.2 | |||
PARAMETER HW_INSTANCE = clk_wiz_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = vtc | |||
PARAMETER DRIVER_VER = 8.0 | |||
PARAMETER HW_INSTANCE = video_subsystem_v_tc_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = axivdma | |||
PARAMETER DRIVER_VER = 6.6 | |||
PARAMETER HW_INSTANCE = video_subsystem_axi_vdma_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = MNTZorro | |||
PARAMETER DRIVER_VER = 1.0 | |||
PARAMETER HW_INSTANCE = MNTZorro_v0_1_S00_AXI_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = gpiops | |||
PARAMETER DRIVER_VER = 3.4 | |||
PARAMETER HW_INSTANCE = ps7_gpio_0 | |||
END | |||
BEGIN DRIVER | |||
PARAMETER DRIVER_NAME = sdps | |||
PARAMETER DRIVER_VER = 3.6 | |||
PARAMETER HW_INSTANCE = ps7_sd_0 | |||
END | |||
@@ -0,0 +1,10 @@ | |||
OPTION psf_version = 2.1; | |||
BEGIN DRIVER MNTZorro | |||
OPTION supported_peripherals = (MNTZorro); | |||
OPTION copyfiles = all; | |||
OPTION VERSION = 1.0; | |||
OPTION NAME = MNTZorro; | |||
END DRIVER |
@@ -0,0 +1,5 @@ | |||
proc generate {drv_handle} { | |||
xdefine_include_file $drv_handle "xparameters.h" "MNTZorro" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR" | |||
} |
@@ -0,0 +1,6 @@ | |||
/***************************** Include Files *******************************/ | |||
#include "MNTZorro.h" | |||
/************************** Function Definitions ***************************/ |
@@ -0,0 +1,79 @@ | |||
#ifndef MNTZORRO_H | |||
#define MNTZORRO_H | |||
/****************** Include Files ********************/ | |||
#include "xil_types.h" | |||
#include "xstatus.h" | |||
#define MNTZORRO_S00_AXI_SLV_REG0_OFFSET 0 | |||
#define MNTZORRO_S00_AXI_SLV_REG1_OFFSET 4 | |||
#define MNTZORRO_S00_AXI_SLV_REG2_OFFSET 8 | |||
#define MNTZORRO_S00_AXI_SLV_REG3_OFFSET 12 | |||
/**************************** Type Definitions *****************************/ | |||
/** | |||
* | |||
* Write a value to a MNTZORRO register. A 32 bit write is performed. | |||
* If the component is implemented in a smaller width, only the least | |||
* significant data is written. | |||
* | |||
* @param BaseAddress is the base address of the MNTZORROdevice. | |||
* @param RegOffset is the register offset from the base to write to. | |||
* @param Data is the data written to the register. | |||
* | |||
* @return None. | |||
* | |||
* @note | |||
* C-style signature: | |||
* void MNTZORRO_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data) | |||
* | |||
*/ | |||
#define MNTZORRO_mWriteReg(BaseAddress, RegOffset, Data) \ | |||
Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data)) | |||
/** | |||
* | |||
* Read a value from a MNTZORRO register. A 32 bit read is performed. | |||
* If the component is implemented in a smaller width, only the least | |||
* significant data is read from the register. The most significant data | |||
* will be read as 0. | |||
* | |||
* @param BaseAddress is the base address of the MNTZORRO device. | |||
* @param RegOffset is the register offset from the base to write to. | |||
* | |||
* @return Data is the data from the register. | |||
* | |||
* @note | |||
* C-style signature: | |||
* u32 MNTZORRO_mReadReg(u32 BaseAddress, unsigned RegOffset) | |||
* | |||
*/ | |||
#define MNTZORRO_mReadReg(BaseAddress, RegOffset) \ | |||
Xil_In32((BaseAddress) + (RegOffset)) | |||
/************************** Function Prototypes ****************************/ | |||
/** | |||
* | |||
* Run a self-test on the driver/device. Note this may be a destructive test if | |||
* resets of the device are performed. | |||
* | |||
* If the hardware system is not built correctly, this function may never | |||
* return to the caller. | |||
* | |||
* @param baseaddr_p is the base address of the MNTZORRO instance to be worked on. | |||
* | |||
* @return | |||
* | |||
* - XST_SUCCESS if all self-test code passed | |||
* - XST_FAILURE if any self-test code failed | |||
* | |||
* @note Caching must be turned off for this function to work. | |||
* @note Self test may fail if data memory and device are not on the same bus. | |||
* | |||
*/ | |||
XStatus MNTZORRO_Reg_SelfTest(void * baseaddr_p); | |||
#endif // MNTZORRO_H |
@@ -0,0 +1,60 @@ | |||
/***************************** Include Files *******************************/ | |||
#include "MNTZorro.h" | |||
#include "xparameters.h" | |||
#include "stdio.h" | |||
#include "xil_io.h" | |||
/************************** Constant Definitions ***************************/ | |||
#define READ_WRITE_MUL_FACTOR 0x10 | |||
/************************** Function Definitions ***************************/ | |||
/** | |||
* | |||
* Run a self-test on the driver/device. Note this may be a destructive test if | |||
* resets of the device are performed. | |||
* | |||
* If the hardware system is not built correctly, this function may never | |||
* return to the caller. | |||
* | |||
* @param baseaddr_p is the base address of the MNTZORROinstance to be worked on. | |||
* | |||
* @return | |||
* | |||
* - XST_SUCCESS if all self-test code passed | |||
* - XST_FAILURE if any self-test code failed | |||
* | |||
* @note Caching must be turned off for this function to work. | |||
* @note Self test may fail if data memory and device are not on the same bus. | |||
* | |||
*/ | |||
XStatus MNTZORRO_Reg_SelfTest(void * baseaddr_p) | |||
{ | |||
u32 baseaddr; | |||
int write_loop_index; | |||
int read_loop_index; | |||
int Index; | |||
baseaddr = (u32) baseaddr_p; | |||
xil_printf("******************************\n\r"); | |||
xil_printf("* User Peripheral Self Test\n\r"); | |||
xil_printf("******************************\n\n\r"); | |||
/* | |||
* Write to user logic slave module register(s) and read back | |||
*/ | |||
xil_printf("User logic slave module test...\n\r"); | |||
for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++) | |||
MNTZORRO_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR); | |||
for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++) | |||
if ( MNTZORRO_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){ | |||
xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4); | |||
return XST_FAILURE; | |||
} | |||
xil_printf(" - slave register write/read passed\n\n\r"); | |||
return XST_SUCCESS; | |||
} |
@@ -0,0 +1,26 @@ | |||
COMPILER= | |||
ARCHIVER= | |||
CP=cp | |||
COMPILER_FLAGS= | |||
EXTRA_COMPILER_FLAGS= | |||
LIB=libxil.a | |||
RELEASEDIR=../../../lib | |||
INCLUDEDIR=../../../include | |||
INCLUDES=-I./. -I${INCLUDEDIR} | |||
INCLUDEFILES=*.h | |||
LIBSOURCES=*.c | |||
OUTS = *.o | |||
libs: | |||
echo "Compiling MNTZorro..." | |||
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) | |||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} | |||
make clean | |||
include: | |||
${CP} $(INCLUDEFILES) $(INCLUDEDIR) | |||
clean: | |||
rm -rf ${OUTS} |
@@ -0,0 +1,139 @@ | |||
/****************************************************************************** | |||
* | |||
* Copyright (C) 2018 Xilinx, Inc. All rights reserved. | |||
* | |||
* Permission is hereby granted, free of charge, to any person obtaining a copy | |||
* of this software and associated documentation files (the "Software"), to deal | |||
* in the Software without restriction, including without limitation the rights | |||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |||
* copies of the Software, and to permit persons to whom the Software is | |||
* furnished to do so, subject to the following conditions: | |||
* | |||
* The above copyright notice and this permission notice shall be included in | |||
* all copies or substantial portions of the Software. | |||
* | |||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE | |||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF | |||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |||
* SOFTWARE. | |||
* | |||
* Except as contained in this notice, the name of the Xilinx shall not be used | |||
* in advertising or otherwise to promote the sale, use or other dealings in | |||
* this Software without prior written authorization from Xilinx. | |||
* | |||
******************************************************************************/ | |||
/****************************************************************************/ | |||
/** | |||
* | |||
* @file ps7_init.h | |||
* | |||
* This file can be included in FSBL code | |||
* to get prototype of ps7_init() function | |||
* and error codes | |||
* | |||
*****************************************************************************/ | |||
#ifdef __cplusplus | |||
extern "C" { | |||
#endif | |||
//typedef unsigned int u32; | |||
/** do we need to make this name more unique ? **/ | |||
//extern u32 ps7_init_data[]; | |||
extern unsigned long * ps7_ddr_init_data; | |||
extern unsigned long * ps7_mio_init_data; | |||
extern unsigned long * ps7_pll_init_data; | |||
extern unsigned long * ps7_clock_init_data; | |||
extern unsigned long * ps7_peripherals_init_data; | |||
#define OPCODE_EXIT 0U | |||
#define OPCODE_CLEAR 1U | |||
#define OPCODE_WRITE 2U | |||
#define OPCODE_MASKWRITE 3U | |||
#define OPCODE_MASKPOLL 4U | |||
#define OPCODE_MASKDELAY 5U | |||
#define NEW_PS7_ERR_CODE 1 | |||
/* Encode number of arguments in last nibble */ | |||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) | |||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr | |||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val | |||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val | |||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask | |||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask | |||
/* Returns codes of PS7_Init */ | |||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C | |||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now | |||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out | |||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init | |||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit | |||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init | |||
/* Silicon Versions */ | |||
#define PCW_SILICON_VERSION_1 0 | |||
#define PCW_SILICON_VERSION_2 1 | |||
#define PCW_SILICON_VERSION_3 2 | |||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ | |||
#define PS7_POST_CONFIG | |||
/* Freq of all peripherals */ | |||
#define APU_FREQ 666666687 | |||
#define DDR_FREQ 533333374 | |||
#define DCI_FREQ 10158730 | |||
#define QSPI_FREQ 10000000 | |||
#define SMC_FREQ 10000000 | |||
#define ENET0_FREQ 10000000 | |||
#define ENET1_FREQ 10000000 | |||
#define USB0_FREQ 60000000 | |||
#define USB1_FREQ 60000000 | |||
#define SDIO_FREQ 50000000 | |||
#define UART_FREQ 100000000 | |||
#define SPI_FREQ 10000000 | |||
#define I2C_FREQ 111111115 | |||
#define WDT_FREQ 111111115 | |||
#define TTC_FREQ 50000000 | |||
#define CAN_FREQ 10000000 | |||
#define PCAP_FREQ 200000000 | |||
#define TPIU_FREQ 200000000 | |||
#define FPGA0_FREQ 75000000 | |||
#define FPGA1_FREQ 10000000 | |||
#define FPGA2_FREQ 10000000 | |||
#define FPGA3_FREQ 10000000 | |||
/* For delay calculation using global registers*/ | |||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 | |||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 | |||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 | |||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 | |||
int ps7_config( unsigned long*); | |||
int ps7_init(); | |||
int ps7_post_config(); | |||
int ps7_debug(); | |||
char* getPS7MessageInfo(unsigned key); | |||
void perf_start_clock(void); | |||
void perf_disable_clock(void); | |||
void perf_reset_clock(void); | |||
void perf_reset_and_start_timer(); | |||
int get_number_of_cycles_for_delay(unsigned int delay); | |||
#ifdef __cplusplus | |||
} | |||
#endif | |||
@@ -0,0 +1,823 @@ | |||
proc ps7_pll_init_data_3_0 {} { | |||
mwr -force 0XF8000008 0x0000DF0D | |||
mask_write 0XF8000110 0x003FFFF0 0x000FA220 | |||
mask_write 0XF8000100 0x0007F000 0x00028000 | |||
mask_write 0XF8000100 0x00000010 0x00000010 | |||
mask_write 0XF8000100 0x00000001 0x00000001 | |||
mask_write 0XF8000100 0x00000001 0x00000000 | |||
mask_poll 0XF800010C 0x00000001 | |||
mask_write 0XF8000100 0x00000010 0x00000000 | |||
mask_write 0XF8000120 0x1F003F30 0x1F000200 | |||
mask_write 0XF8000114 0x003FFFF0 0x0012C220 | |||
mask_write 0XF8000104 0x0007F000 0x00020000 | |||
mask_write 0XF8000104 0x00000010 0x00000010 | |||
mask_write 0XF8000104 0x00000001 0x00000001 | |||
mask_write 0XF8000104 0x00000001 0x00000000 | |||
mask_poll 0XF800010C 0x00000002 | |||
mask_write 0XF8000104 0x00000010 0x00000000 | |||
mask_write 0XF8000124 0xFFF00003 0x0C200003 | |||
mask_write 0XF8000118 0x003FFFF0 0x00113220 | |||
mask_write 0XF8000108 0x0007F000 0x00024000 | |||
mask_write 0XF8000108 0x00000010 0x00000010 | |||
mask_write 0XF8000108 0x00000001 0x00000001 | |||
mask_write 0XF8000108 0x00000001 0x00000000 | |||
mask_poll 0XF800010C 0x00000004 | |||
mask_write 0XF8000108 0x00000010 0x00000000 | |||
mwr -force 0XF8000004 0x0000767B | |||
} | |||
proc ps7_clock_init_data_3_0 {} { | |||
mwr -force 0XF8000008 0x0000DF0D | |||
mask_write 0XF8000128 0x03F03F01 0x00700F01 | |||
mask_write 0XF8000150 0x00003F33 0x00001801 | |||
mask_write 0XF8000154 0x00003F33 0x00000C02 | |||
mask_write 0XF8000168 0x00003F31 0x00000601 | |||
mask_write 0XF8000170 0x03F03F30 0x00400400 | |||
mask_write 0XF80001C4 0x00000001 0x00000001 | |||
mask_write 0XF800012C 0x01FFCCCD 0x016C040D | |||
mwr -force 0XF8000004 0x0000767B | |||
} | |||
proc ps7_ddr_init_data_3_0 {} { | |||
mask_write 0XF8006000 0x0001FFFF 0x00000080 | |||
mask_write 0XF8006004 0x0007FFFF 0x00001082 | |||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F | |||
mask_write 0XF800600C 0x03FFFFFF 0x02001001 | |||
mask_write 0XF8006010 0x03FFFFFF 0x00014001 | |||
mask_write 0XF8006014 0x001FFFFF 0x0004285B | |||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 | |||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 | |||
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 | |||
mask_write 0XF8006024 0x0FFFFFC3 0x00000000 | |||
mask_write 0XF8006028 0x00003FFF 0x00002007 | |||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 | |||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 | |||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 | |||
mask_write 0XF8006038 0x00000003 0x00000000 | |||
mask_write 0XF800603C 0x000FFFFF 0x00000777 | |||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 | |||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 | |||
mask_write 0XF8006048 0x0003F03F 0x0003C008 | |||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800 | |||
mask_write 0XF8006058 0x00010000 0x00000000 | |||
mask_write 0XF800605C 0x0000FFFF 0x00005003 | |||
mask_write 0XF8006060 0x000017FF 0x0000003E | |||
mask_write 0XF8006064 0x00021FE0 0x00020000 | |||
mask_write 0XF8006068 0x03FFFFFF 0x00284141 | |||
mask_write 0XF800606C 0x0000FFFF 0x00001610 | |||
mask_write 0XF8006078 0x03FFFFFF 0x00466111 | |||
mask_write 0XF800607C 0x000FFFFF 0x00032222 | |||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 | |||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 | |||
mask_write 0XF80060AC 0x000001FF 0x000001FE | |||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF | |||
mask_write 0XF80060B4 0x00000200 0x00000200 | |||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 | |||
mask_write 0XF80060C4 0x00000003 0x00000000 | |||
mask_write 0XF80060C8 0x000000FF 0x00000000 | |||
mask_write 0XF80060DC 0x00000001 0x00000000 | |||
mask_write 0XF80060F0 0x0000FFFF 0x00000000 | |||
mask_write 0XF80060F4 0x0000000F 0x00000008 | |||
mask_write 0XF8006114 0x000000FF 0x00000000 | |||
mask_write 0XF8006118 0x7FFFFFCF 0x40000001 | |||
mask_write 0XF800611C 0x7FFFFFCF 0x40000001 | |||
mask_write 0XF8006120 0x7FFFFFCF 0x40000001 | |||
mask_write 0XF8006124 0x7FFFFFCF 0x40000001 | |||
mask_write 0XF800612C 0x000FFFFF 0x0002A81F | |||
mask_write 0XF8006130 0x000FFFFF 0x00029822 | |||
mask_write 0XF8006134 0x000FFFFF 0x00026C10 | |||
mask_write 0XF8006138 0x000FFFFF 0x00026013 | |||
mask_write 0XF8006140 0x000FFFFF 0x00000035 | |||
mask_write 0XF8006144 0x000FFFFF 0x00000035 | |||
mask_write 0XF8006148 0x000FFFFF 0x00000035 | |||
mask_write 0XF800614C 0x000FFFFF 0x00000035 | |||
mask_write 0XF8006154 0x000FFFFF 0x0000009F | |||
mask_write 0XF8006158 0x000FFFFF 0x000000A2 | |||
mask_write 0XF800615C 0x000FFFFF 0x00000090 | |||
mask_write 0XF8006160 0x000FFFFF 0x00000093 | |||
mask_write 0XF8006168 0x001FFFFF 0x000000FF | |||
mask_write 0XF800616C 0x001FFFFF 0x000000FB | |||
mask_write 0XF8006170 0x001FFFFF 0x000000F0 | |||
mask_write 0XF8006174 0x001FFFFF 0x000000ED | |||
mask_write 0XF800617C 0x000FFFFF 0x000000DF | |||
mask_write 0XF8006180 0x000FFFFF 0x000000E2 | |||
mask_write 0XF8006184 0x000FFFFF 0x000000D0 | |||
mask_write 0XF8006188 0x000FFFFF 0x000000D3 | |||
mask_write 0XF8006190 0x6FFFFEFE 0x00040080 | |||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82 | |||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000 | |||
mask_write 0XF8006208 0x000703FF 0x000003FF | |||
mask_write 0XF800620C 0x000703FF 0x000003FF | |||
mask_write 0XF8006210 0x000703FF 0x000003FF | |||
mask_write 0XF8006214 0x000703FF 0x000003FF | |||
mask_write 0XF8006218 0x000F03FF 0x000003FF | |||
mask_write 0XF800621C 0x000F03FF 0x000003FF | |||
mask_write 0XF8006220 0x000F03FF 0x000003FF | |||
mask_write 0XF8006224 0x000F03FF 0x000003FF | |||
mask_write 0XF80062A8 0x00000FF5 0x00000000 | |||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 | |||
mask_write 0XF80062B0 0x003FFFFF 0x00005125 | |||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 | |||
mask_poll 0XF8000B74 0x00002000 | |||
mask_write 0XF8006000 0x0001FFFF 0x00000081 | |||
mask_poll 0XF8006054 0x00000007 | |||
} | |||
proc ps7_mio_init_data_3_0 {} { | |||
mwr -force 0XF8000008 0x0000DF0D | |||
mask_write 0XF8000B40 0x00000FFF 0x00000600 | |||
mask_write 0XF8000B44 0x00000FFF 0x00000600 | |||
mask_write 0XF8000B48 0x00000FFF 0x00000672 | |||
mask_write 0XF8000B4C 0x00000FFF 0x00000672 | |||
mask_write 0XF8000B50 0x00000FFF 0x00000674 | |||
mask_write 0XF8000B54 0x00000FFF 0x00000674 | |||
mask_write 0XF8000B58 0x00000FFF 0x00000600 | |||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C | |||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C | |||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C | |||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C | |||
mask_write 0XF8000B6C 0x00007FFF 0x00000260 | |||
mask_write 0XF8000B70 0x00000001 0x00000001 | |||
mask_write 0XF8000B70 0x00000021 0x00000020 | |||
mask_write 0XF8000B70 0x07FEFFFF 0x00000823 | |||
mask_write 0XF8000700 0x00003FFF 0x00001600 | |||
mask_write 0XF8000704 0x00003FFF 0x00001600 | |||
mask_write 0XF8000708 0x00003FFF 0x00000600 | |||
mask_write 0XF800070C 0x00003FFF 0x00000600 | |||
mask_write 0XF8000710 0x00003FFF 0x00000600 | |||
mask_write 0XF8000714 0x00003FFF 0x00000600 | |||
mask_write 0XF8000718 0x00003FFF 0x00000600 | |||
mask_write 0XF800071C 0x00003FFF 0x00000600 | |||
mask_write 0XF8000720 0x00003FFF 0x00000600 | |||
mask_write 0XF8000724 0x00003FFF 0x00001600 | |||
mask_write 0XF8000728 0x00003FFF 0x00001600 | |||
mask_write 0XF800072C 0x00003FFF 0x00001600 | |||
mask_write 0XF8000730 0x00003FFF 0x00001600 | |||
mask_write 0XF8000734 0x00003FFF 0x00001600 | |||
mask_write 0XF8000738 0x00003FFF 0x00001600 | |||
mask_write 0XF800073C 0x00003FFF 0x00001600 | |||
mask_write 0XF8000740 0x00003FFF 0x00001200 | |||
mask_write 0XF8000744 0x00003FFF 0x00001200 | |||
mask_write 0XF8000748 0x00003FFF 0x00001200 | |||
mask_write 0XF800074C 0x00003FFF 0x00001200 | |||
mask_write 0XF8000750 0x00003FFF 0x00001200 | |||
mask_write 0XF8000754 0x00003FFF 0x00001200 | |||
mask_write 0XF8000758 0x00003FFF 0x00001200 | |||
mask_write 0XF800075C 0x00003FFF 0x00001200 | |||
mask_write 0XF8000760 0x00003FFF 0x00001200 | |||
mask_write 0XF8000764 0x00003FFF 0x00001200 | |||
mask_write 0XF8000768 0x00003FFF 0x00001200 | |||
mask_write 0XF800076C 0x00003FFF 0x00001200 | |||
mask_write 0XF8000770 0x00003FFF 0x00001200 | |||
mask_write 0XF8000774 0x00003FFF 0x00001200 | |||
mask_write 0XF8000778 0x00003FFF 0x00001200 | |||
mask_write 0XF800077C 0x00003FFF 0x00001200 | |||
mask_write 0XF8000780 0x00003FFF 0x00001200 | |||
mask_write 0XF8000784 0x00003FFF 0x00001200 | |||
mask_write 0XF8000788 0x00003FFF 0x00001200 | |||
mask_write 0XF800078C 0x00003FFF 0x00001200 | |||
mask_write 0XF8000790 0x00003FFF 0x00001200 | |||
mask_write 0XF8000794 0x00003FFF 0x00001200 | |||
mask_write 0XF8000798 0x00003FFF 0x00001200 | |||
mask_write 0XF800079C 0x00003FFF 0x00001200 | |||
mask_write 0XF80007A0 0x00003FFF 0x00001280 | |||
mask_write 0XF80007A4 0x00003FFF 0x00001280 | |||
mask_write 0XF80007A8 0x00003FFF 0x00001280 | |||
mask_write 0XF80007AC 0x00003FFF 0x00001280 | |||
mask_write 0XF80007B0 0x00003FFF 0x00001280 | |||
mask_write 0XF80007B4 0x00003FFF 0x00001280 | |||
mask_write 0XF80007B8 0x00003FFF 0x00001200 | |||
mask_write 0XF80007BC 0x00003FFF 0x00001200 | |||
mask_write 0XF80007C0 0x00003FFF 0x000012E0 | |||
mask_write 0XF80007C4 0x00003FFF 0x000012E1 | |||
mask_write 0XF80007C8 0x00003FFF 0x00001200 | |||
mask_write 0XF80007CC 0x00003FFF 0x00001200 | |||
mask_write 0XF80007D0 0x00003FFF 0x00001200 | |||
mask_write 0XF80007D4 0x00003FFF 0x00001200 | |||
mask_write 0XF8000830 0x003F003F 0x00380037 | |||
mwr -force 0XF8000004 0x0000767B | |||
} | |||
proc ps7_peripherals_init_data_3_0 {} { | |||
mwr -force 0XF8000008 0x0000DF0D | |||
mask_write 0XF8000B48 0x00000180 0x00000180 | |||
mask_write 0XF8000B4C 0x00000180 0x00000180 | |||
mask_write 0XF8000B50 0x00000180 0x00000180 | |||
mask_write 0XF8000B54 0x00000180 0x00000180 | |||
mwr -force 0XF8000004 0x0000767B | |||
mask_write 0XE0001034 0x000000FF 0x00000006 | |||
mask_write 0XE0001018 0x0000FFFF 0x0000007C | |||
mask_write 0XE0001000 0x000001FF 0x00000017 | |||
mask_write 0XE0001004 0x000003FF 0x00000020 | |||
mask_write 0XE000D000 0x00080000 0x00080000 | |||
mask_write 0XF8007000 0x20000000 0x00000000 | |||
mask_write 0XE000A204 0xFFFFFFFF 0x00000004 | |||
mask_write 0XE000A000 0xFFFFFFFF 0xFFFB0004 | |||
mask_write 0XE000A208 0xFFFFFFFF 0x00000004 | |||
mask_write 0XE000A000 0xFFFFFFFF 0xFFFB0000 | |||
mask_delay 0XF8F00200 1 | |||
mask_write 0XE000A000 0xFFFFFFFF 0xFFFB0004 | |||
} | |||
proc ps7_post_config_3_0 {} { | |||
mwr -force 0XF8000008 0x0000DF0D | |||
mask_write 0XF8000900 0x0000000F 0x0000000F | |||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000 | |||
mwr -force 0XF8000004 0x0000767B | |||
} | |||
proc ps7_debug_3_0 {} { | |||
mwr -force 0XF8898FB0 0xC5ACCE55 | |||
mwr -force 0XF8899FB0 0xC5ACCE55 | |||
mwr -force 0XF8809FB0 0xC5ACCE55 | |||
} | |||
proc ps7_pll_init_data_2_0 {} { | |||
mwr -force 0XF8000008 0x0000DF0D | |||
mask_write 0XF8000110 0x003FFFF0 0x000FA220 | |||
mask_write 0XF8000100 0x0007F000 0x00028000 | |||
mask_write 0XF8000100 0x00000010 0x00000010 | |||
mask_write 0XF8000100 0x00000001 0x00000001 | |||
mask_write 0XF8000100 0x00000001 0x00000000 | |||
mask_poll 0XF800010C 0x00000001 | |||
mask_write 0XF8000100 0x00000010 0x00000000 | |||
mask_write 0XF8000120 0x1F003F30 0x1F000200 | |||
mask_write 0XF8000114 0x003FFFF0 0x0012C220 | |||
mask_write 0XF8000104 0x0007F000 0x00020000 | |||
mask_write 0XF8000104 0x00000010 0x00000010 | |||
mask_write 0XF8000104 0x00000001 0x00000001 | |||
mask_write 0XF8000104 0x00000001 0x00000000 | |||
mask_poll 0XF800010C 0x00000002 | |||
mask_write 0XF8000104 0x00000010 0x00000000 | |||
mask_write 0XF8000124 0xFFF00003 0x0C200003 | |||
mask_write 0XF8000118 0x003FFFF0 0x00113220 | |||
mask_write 0XF8000108 0x0007F000 0x00024000 | |||
mask_write 0XF8000108 0x00000010 0x00000010 | |||
mask_write 0XF8000108 0x00000001 0x00000001 | |||
mask_write 0XF8000108 0x00000001 0x00000000 | |||
mask_poll 0XF800010C 0x00000004 | |||
mask_write 0XF8000108 0x00000010 0x00000000 | |||
mwr -force 0XF8000004 0x0000767B | |||
} | |||
proc ps7_clock_init_data_2_0 {} { | |||
mwr -force 0XF8000008 0x0000DF0D | |||
mask_write 0XF8000128 0x03F03F01 0x00700F01 | |||
mask_write 0XF8000150 0x00003F33 0x00001801 | |||
mask_write 0XF8000154 0x00003F33 0x00000C02 | |||
mask_write 0XF8000168 0x00003F31 0x00000601 | |||
mask_write 0XF8000170 0x03F03F30 0x00400400 | |||
mask_write 0XF80001C4 0x00000001 0x00000001 | |||
mask_write 0XF800012C 0x01FFCCCD 0x016C040D | |||
mwr -force 0XF8000004 0x0000767B | |||
} | |||
proc ps7_ddr_init_data_2_0 {} { | |||
mask_write 0XF8006000 0x0001FFFF 0x00000080 | |||
mask_write 0XF8006004 0x1FFFFFFF 0x00081082 | |||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F | |||
mask_write 0XF800600C 0x03FFFFFF 0x02001001 | |||
mask_write 0XF8006010 0x03FFFFFF 0x00014001 | |||
mask_write 0XF8006014 0x001FFFFF 0x0004285B | |||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 | |||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 | |||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 | |||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C | |||
mask_write 0XF8006028 0x00003FFF 0x00002007 | |||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 | |||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 | |||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 | |||
mask_write 0XF8006038 0x00001FC3 0x00000000 | |||
mask_write 0XF800603C 0x000FFFFF 0x00000777 | |||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 | |||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 | |||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 | |||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800 | |||
mask_write 0XF8006058 0x0001FFFF 0x00000101 | |||
mask_write 0XF800605C 0x0000FFFF 0x00005003 | |||
mask_write 0XF8006060 0x000017FF 0x0000003E | |||
mask_write 0XF8006064 0x00021FE0 0x00020000 | |||
mask_write 0XF8006068 0x03FFFFFF 0x00284141 | |||
mask_write 0XF800606C 0x0000FFFF 0x00001610 | |||
mask_write 0XF8006078 0x03FFFFFF 0x00466111 | |||
mask_write 0XF800607C 0x000FFFFF 0x00032222 | |||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000 | |||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 | |||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 | |||
mask_write 0XF80060AC 0x000001FF 0x000001FE | |||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF | |||
mask_write 0XF80060B4 0x000007FF 0x00000200 | |||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 | |||
mask_write 0XF80060C4 0x00000003 0x00000000 | |||
mask_write 0XF80060C8 0x000000FF 0x00000000 | |||
mask_write 0XF80060DC 0x00000001 0x00000000 | |||
mask_write 0XF80060F0 0x0000FFFF 0x00000000 | |||
mask_write 0XF80060F4 0x0000000F 0x00000008 | |||
mask_write 0XF8006114 0x000000FF 0x00000000 | |||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001 | |||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001 | |||
mask_write 0XF8006120 0x7FFFFFFF 0x40000001 | |||
mask_write 0XF8006124 0x7FFFFFFF 0x40000001 | |||
mask_write 0XF800612C 0x000FFFFF 0x0002A81F | |||
mask_write 0XF8006130 0x000FFFFF 0x00029822 | |||
mask_write 0XF8006134 0x000FFFFF 0x00026C10 | |||
mask_write 0XF8006138 0x000FFFFF 0x00026013 | |||
mask_write 0XF8006140 0x000FFFFF 0x00000035 | |||
mask_write 0XF8006144 0x000FFFFF 0x00000035 | |||
mask_write 0XF8006148 0x000FFFFF 0x00000035 | |||
mask_write 0XF800614C 0x000FFFFF 0x00000035 | |||
mask_write 0XF8006154 0x000FFFFF 0x0000009F | |||
mask_write 0XF8006158 0x000FFFFF 0x000000A2 | |||
mask_write 0XF800615C 0x000FFFFF 0x00000090 | |||
mask_write 0XF8006160 0x000FFFFF 0x00000093 | |||
mask_write 0XF8006168 0x001FFFFF 0x000000FF | |||
mask_write 0XF800616C 0x001FFFFF 0x000000FB | |||
mask_write 0XF8006170 0x001FFFFF 0x000000F0 | |||
mask_write 0XF8006174 0x001FFFFF 0x000000ED | |||
mask_write 0XF800617C 0x000FFFFF 0x000000DF | |||
mask_write 0XF8006180 0x000FFFFF 0x000000E2 | |||
mask_write 0XF8006184 0x000FFFFF 0x000000D0 | |||
mask_write 0XF8006188 0x000FFFFF 0x000000D3 | |||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080 | |||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82 | |||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000 | |||
mask_write 0XF8006208 0x000F03FF 0x000803FF | |||
mask_write 0XF800620C 0x000F03FF 0x000803FF | |||
mask_write 0XF8006210 0x000F03FF 0x000803FF | |||
mask_write 0XF8006214 0x000F03FF 0x000803FF | |||
mask_write 0XF8006218 0x000F03FF 0x000003FF | |||
mask_write 0XF800621C 0x000F03FF 0x000003FF | |||
mask_write 0XF8006220 0x000F03FF 0x000003FF | |||
mask_write 0XF8006224 0x000F03FF 0x000003FF | |||
mask_write 0XF80062A8 0x00000FF7 0x00000000 | |||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 | |||
mask_write 0XF80062B0 0x003FFFFF 0x00005125 | |||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 | |||
mask_poll 0XF8000B74 0x00002000 | |||
mask_write 0XF8006000 0x0001FFFF 0x00000081 | |||
mask_poll 0XF8006054 0x00000007 | |||
} | |||
proc ps7_mio_init_data_2_0 {} { | |||
mwr -force 0XF8000008 0x0000DF0D | |||
mask_write 0XF8000B40 0x00000FFF 0x00000600 | |||
mask_write 0XF8000B44 0x00000FFF 0x00000600 | |||
mask_write 0XF8000B48 0x00000FFF 0x00000672 | |||
mask_write 0XF8000B4C 0x00000FFF 0x00000672 | |||
mask_write 0XF8000B50 0x00000FFF 0x00000674 | |||
mask_write 0XF8000B54 0x00000FFF 0x00000674 | |||
mask_write 0XF8000B58 0x00000FFF 0x00000600 | |||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C | |||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C | |||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C | |||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C | |||
mask_write 0XF8000B6C 0x00007FFF 0x00000260 | |||
mask_write 0XF8000B70 0x00000021 0x00000021 | |||
mask_write 0XF8000B70 0x00000021 0x00000020 | |||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823 | |||
mask_write 0XF8000700 0x00003FFF 0x00001600 | |||
mask_write 0XF8000704 0x00003FFF 0x00001600 | |||
mask_write 0XF8000708 0x00003FFF 0x00000600 | |||
mask_write 0XF800070C 0x00003FFF 0x00000600 | |||
mask_write 0XF8000710 0x00003FFF 0x00000600 | |||
mask_write 0XF8000714 0x00003FFF 0x00000600 | |||
mask_write 0XF8000718 0x00003FFF 0x00000600 | |||
mask_write 0XF800071C 0x00003FFF 0x00000600 | |||
mask_write 0XF8000720 0x00003FFF 0x00000600 | |||
mask_write 0XF8000724 0x00003FFF 0x00001600 | |||
mask_write 0XF8000728 0x00003FFF 0x00001600 | |||
mask_write 0XF800072C 0x00003FFF 0x00001600 | |||
mask_write 0XF8000730 0x00003FFF 0x00001600 | |||
mask_write 0XF8000734 0x00003FFF 0x00001600 | |||
mask_write 0XF8000738 0x00003FFF 0x00001600 | |||
mask_write 0XF800073C 0x00003FFF 0x00001600 | |||
mask_write 0XF8000740 0x00003FFF 0x00001200 | |||
mask_write 0XF8000744 0x00003FFF 0x00001200 | |||
mask_write 0XF8000748 0x00003FFF 0x00001200 | |||
mask_write 0XF800074C 0x00003FFF 0x00001200 | |||
mask_write 0XF8000750 0x00003FFF 0x00001200 | |||
mask_write 0XF8000754 0x00003FFF 0x00001200 | |||
mask_write 0XF8000758 0x00003FFF 0x00001200 | |||
mask_write 0XF800075C 0x00003FFF 0x00001200 | |||
mask_write 0XF8000760 0x00003FFF 0x00001200 | |||
mask_write 0XF8000764 0x00003FFF 0x00001200 | |||
mask_write 0XF8000768 0x00003FFF 0x00001200 | |||
mask_write 0XF800076C 0x00003FFF 0x00001200 | |||
mask_write 0XF8000770 0x00003FFF 0x00001200 | |||
mask_write 0XF8000774 0x00003FFF 0x00001200 | |||
mask_write 0XF8000778 0x00003FFF 0x00001200 | |||
mask_write 0XF800077C 0x00003FFF 0x00001200 | |||
mask_write 0XF8000780 0x00003FFF 0x00001200 | |||
mask_write 0XF8000784 0x00003FFF 0x00001200 | |||
mask_write 0XF8000788 0x00003FFF 0x00001200 | |||
mask_write 0XF800078C 0x00003FFF 0x00001200 | |||
mask_write 0XF8000790 0x00003FFF 0x00001200 | |||
mask_write 0XF8000794 0x00003FFF 0x00001200 | |||
mask_write 0XF8000798 0x00003FFF 0x00001200 | |||
mask_write 0XF800079C 0x00003FFF 0x00001200 | |||
mask_write 0XF80007A0 0x00003FFF 0x00001280 | |||
mask_write 0XF80007A4 0x00003FFF 0x00001280 | |||
mask_write 0XF80007A8 0x00003FFF 0x00001280 | |||
mask_write 0XF80007AC 0x00003FFF 0x00001280 | |||
mask_write 0XF80007B0 0x00003FFF 0x00001280 | |||
mask_write 0XF80007B4 0x00003FFF 0x00001280 | |||
mask_write 0XF80007B8 0x00003FFF 0x00001200 | |||
mask_write 0XF80007BC 0x00003FFF 0x00001200 | |||
mask_write 0XF80007C0 0x00003FFF 0x000012E0 | |||
mask_write 0XF80007C4 0x00003FFF 0x000012E1 | |||
mask_write 0XF80007C8 0x00003FFF 0x00001200 | |||
mask_write 0XF80007CC 0x00003FFF 0x00001200 | |||
mask_write 0XF80007D0 0x00003FFF 0x00001200 | |||
mask_write 0XF80007D4 0x00003FFF 0x00001200 | |||
mask_write 0XF8000830 0x003F003F 0x00380037 | |||
mwr -force 0XF8000004 0x0000767B | |||
} | |||
proc ps7_peripherals_init_data_2_0 {} { | |||
mwr -force 0XF8000008 0x0000DF0D | |||
mask_write 0XF8000B48 0x00000180 0x00000180 | |||
mask_write 0XF8000B4C 0x00000180 0x00000180 | |||
mask_write 0XF8000B50 0x00000180 0x00000180 | |||
mask_write 0XF8000B54 0x00000180 0x00000180 | |||
mwr -force 0XF8000004 0x0000767B | |||
mask_write 0XE0001034 0x000000FF 0x00000006 | |||
mask_write 0XE0001018 0x0000FFFF 0x0000007C | |||
mask_write 0XE0001000 0x000001FF 0x00000017 | |||
mask_write 0XE0001004 0x00000FFF 0x00000020 | |||
mask_write 0XE000D000 0x00080000 0x00080000 | |||
mask_write 0XF8007000 0x20000000 0x00000000 | |||
mask_write 0XE000A204 0xFFFFFFFF 0x00000004 | |||
mask_write 0XE000A000 0xFFFFFFFF 0xFFFB0004 | |||
mask_write 0XE000A208 0xFFFFFFFF 0x00000004 | |||
mask_write 0XE000A000 0xFFFFFFFF 0xFFFB0000 | |||
mask_delay 0XF8F00200 1 | |||
mask_write 0XE000A000 0xFFFFFFFF 0xFFFB0004 | |||
} | |||
proc ps7_post_config_2_0 {} { | |||
mwr -force 0XF8000008 0x0000DF0D | |||
mask_write 0XF8000900 0x0000000F 0x0000000F | |||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000 | |||
mwr -force 0XF8000004 0x0000767B | |||
} | |||
proc ps7_debug_2_0 {} { | |||
mwr -force 0XF8898FB0 0xC5ACCE55 | |||
mwr -force 0XF8899FB0 0xC5ACCE55 | |||
mwr -force 0XF8809FB0 0xC5ACCE55 | |||
} | |||
proc ps7_pll_init_data_1_0 {} { | |||
mwr -force 0XF8000008 0x0000DF0D | |||
mask_write 0XF8000110 0x003FFFF0 0x000FA220 | |||
mask_write 0XF8000100 0x0007F000 0x00028000 | |||
mask_write 0XF8000100 0x00000010 0x00000010 | |||
mask_write 0XF8000100 0x00000001 0x00000001 | |||
mask_write 0XF8000100 0x00000001 0x00000000 | |||
mask_poll 0XF800010C 0x00000001 | |||
mask_write 0XF8000100 0x00000010 0x00000000 | |||
mask_write 0XF8000120 0x1F003F30 0x1F000200 | |||
mask_write 0XF8000114 0x003FFFF0 0x0012C220 | |||
mask_write 0XF8000104 0x0007F000 0x00020000 | |||
mask_write 0XF8000104 0x00000010 0x00000010 | |||
mask_write 0XF8000104 0x00000001 0x00000001 | |||
mask_write 0XF8000104 0x00000001 0x00000000 | |||
mask_poll 0XF800010C 0x00000002 | |||
mask_write 0XF8000104 0x00000010 0x00000000 | |||
mask_write 0XF8000124 0xFFF00003 0x0C200003 | |||
mask_write 0XF8000118 0x003FFFF0 0x00113220 | |||
mask_write 0XF8000108 0x0007F000 0x00024000 | |||
mask_write 0XF8000108 0x00000010 0x00000010 | |||
mask_write 0XF8000108 0x00000001 0x00000001 | |||
mask_write 0XF8000108 0x00000001 0x00000000 | |||
mask_poll 0XF800010C 0x00000004 | |||
mask_write 0XF8000108 0x00000010 0x00000000 | |||
mwr -force 0XF8000004 0x0000767B | |||
} | |||
proc ps7_clock_init_data_1_0 {} { | |||
mwr -force 0XF8000008 0x0000DF0D | |||
mask_write 0XF8000128 0x03F03F01 0x00700F01 | |||
mask_write 0XF8000150 0x00003F33 0x00001801 | |||
mask_write 0XF8000154 0x00003F33 0x00000C02 | |||
mask_write 0XF8000168 0x00003F31 0x00000601 | |||
mask_write 0XF8000170 0x03F03F30 0x00400400 | |||
mask_write 0XF80001C4 0x00000001 0x00000001 | |||
mask_write 0XF800012C 0x01FFCCCD 0x016C040D | |||
mwr -force 0XF8000004 0x0000767B | |||
} | |||
proc ps7_ddr_init_data_1_0 {} { | |||
mask_write 0XF8006000 0x0001FFFF 0x00000080 | |||
mask_write 0XF8006004 0x1FFFFFFF 0x00081082 | |||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F | |||
mask_write 0XF800600C 0x03FFFFFF 0x02001001 | |||
mask_write 0XF8006010 0x03FFFFFF 0x00014001 | |||
mask_write 0XF8006014 0x001FFFFF 0x0004285B | |||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 | |||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 | |||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 | |||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C | |||
mask_write 0XF8006028 0x00003FFF 0x00002007 | |||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 | |||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 | |||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 | |||
mask_write 0XF8006038 0x00001FC3 0x00000000 | |||
mask_write 0XF800603C 0x000FFFFF 0x00000777 | |||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 | |||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 | |||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 | |||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800 | |||
mask_write 0XF8006058 0x0001FFFF 0x00000101 | |||
mask_write 0XF800605C 0x0000FFFF 0x00005003 | |||
mask_write 0XF8006060 0x000017FF 0x0000003E | |||
mask_write 0XF8006064 0x00021FE0 0x00020000 | |||
mask_write 0XF8006068 0x03FFFFFF 0x00284141 | |||
mask_write 0XF800606C 0x0000FFFF 0x00001610 | |||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000 | |||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 | |||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 | |||
mask_write 0XF80060AC 0x000001FF 0x000001FE | |||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF | |||
mask_write 0XF80060B4 0x000007FF 0x00000200 | |||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 | |||
mask_write 0XF80060C4 0x00000003 0x00000000 | |||
mask_write 0XF80060C8 0x000000FF 0x00000000 | |||
mask_write 0XF80060DC 0x00000001 0x00000000 | |||
mask_write 0XF80060F0 0x0000FFFF 0x00000000 | |||
mask_write 0XF80060F4 0x0000000F 0x00000008 | |||
mask_write 0XF8006114 0x000000FF 0x00000000 | |||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001 | |||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001 | |||
mask_write 0XF8006120 0x7FFFFFFF 0x40000001 | |||
mask_write 0XF8006124 0x7FFFFFFF 0x40000001 | |||
mask_write 0XF800612C 0x000FFFFF 0x0002A81F | |||
mask_write 0XF8006130 0x000FFFFF 0x00029822 | |||
mask_write 0XF8006134 0x000FFFFF 0x00026C10 | |||
mask_write 0XF8006138 0x000FFFFF 0x00026013 | |||
mask_write 0XF8006140 0x000FFFFF 0x00000035 | |||
mask_write 0XF8006144 0x000FFFFF 0x00000035 | |||
mask_write 0XF8006148 0x000FFFFF 0x00000035 | |||
mask_write 0XF800614C 0x000FFFFF 0x00000035 | |||
mask_write 0XF8006154 0x000FFFFF 0x0000009F | |||
mask_write 0XF8006158 0x000FFFFF 0x000000A2 | |||
mask_write 0XF800615C 0x000FFFFF 0x00000090 | |||
mask_write 0XF8006160 0x000FFFFF 0x00000093 | |||
mask_write 0XF8006168 0x001FFFFF 0x000000FF | |||
mask_write 0XF800616C 0x001FFFFF 0x000000FB | |||
mask_write 0XF8006170 0x001FFFFF 0x000000F0 | |||
mask_write 0XF8006174 0x001FFFFF 0x000000ED | |||
mask_write 0XF800617C 0x000FFFFF 0x000000DF | |||
mask_write 0XF8006180 0x000FFFFF 0x000000E2 | |||
mask_write 0XF8006184 0x000FFFFF 0x000000D0 | |||
mask_write 0XF8006188 0x000FFFFF 0x000000D3 | |||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080 | |||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82 | |||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000 | |||
mask_write 0XF8006208 0x000F03FF 0x000803FF | |||
mask_write 0XF800620C 0x000F03FF 0x000803FF | |||
mask_write 0XF8006210 0x000F03FF 0x000803FF | |||
mask_write 0XF8006214 0x000F03FF 0x000803FF | |||
mask_write 0XF8006218 0x000F03FF 0x000003FF | |||
mask_write 0XF800621C 0x000F03FF 0x000003FF | |||
mask_write 0XF8006220 0x000F03FF 0x000003FF | |||
mask_write 0XF8006224 0x000F03FF 0x000003FF | |||
mask_write 0XF80062A8 0x00000FF7 0x00000000 | |||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 | |||
mask_write 0XF80062B0 0x003FFFFF 0x00005125 | |||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 | |||
mask_poll 0XF8000B74 0x00002000 | |||
mask_write 0XF8006000 0x0001FFFF 0x00000081 | |||
mask_poll 0XF8006054 0x00000007 | |||
} | |||
proc ps7_mio_init_data_1_0 {} { | |||
mwr -force 0XF8000008 0x0000DF0D | |||
mask_write 0XF8000B40 0x00000FFF 0x00000600 | |||
mask_write 0XF8000B44 0x00000FFF 0x00000600 | |||
mask_write 0XF8000B48 0x00000FFF 0x00000672 | |||
mask_write 0XF8000B4C 0x00000FFF 0x00000672 | |||
mask_write 0XF8000B50 0x00000FFF 0x00000674 | |||
mask_write 0XF8000B54 0x00000FFF 0x00000674 | |||
mask_write 0XF8000B58 0x00000FFF 0x00000600 | |||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C | |||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C | |||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C | |||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C | |||
mask_write 0XF8000B6C 0x000073FF 0x00000260 | |||
mask_write 0XF8000B70 0x00000021 0x00000021 | |||
mask_write 0XF8000B70 0x00000021 0x00000020 | |||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823 | |||
mask_write 0XF8000700 0x00003FFF 0x00001600 | |||
mask_write 0XF8000704 0x00003FFF 0x00001600 | |||
mask_write 0XF8000708 0x00003FFF 0x00000600 | |||
mask_write 0XF800070C 0x00003FFF 0x00000600 | |||
mask_write 0XF8000710 0x00003FFF 0x00000600 | |||
mask_write 0XF8000714 0x00003FFF 0x00000600 | |||
mask_write 0XF8000718 0x00003FFF 0x00000600 | |||
mask_write 0XF800071C 0x00003FFF 0x00000600 | |||
mask_write 0XF8000720 0x00003FFF 0x00000600 | |||
mask_write 0XF8000724 0x00003FFF 0x00001600 | |||
mask_write 0XF8000728 0x00003FFF 0x00001600 | |||
mask_write 0XF800072C 0x00003FFF 0x00001600 | |||
mask_write 0XF8000730 0x00003FFF 0x00001600 | |||
mask_write 0XF8000734 0x00003FFF 0x00001600 | |||
mask_write 0XF8000738 0x00003FFF 0x00001600 | |||
mask_write 0XF800073C 0x00003FFF 0x00001600 | |||
mask_write 0XF8000740 0x00003FFF 0x00001200 | |||
mask_write 0XF8000744 0x00003FFF 0x00001200 | |||
mask_write 0XF8000748 0x00003FFF 0x00001200 | |||
mask_write 0XF800074C 0x00003FFF 0x00001200 | |||
mask_write 0XF8000750 0x00003FFF 0x00001200 | |||
mask_write 0XF8000754 0x00003FFF 0x00001200 | |||
mask_write 0XF8000758 0x00003FFF 0x00001200 | |||
mask_write 0XF800075C 0x00003FFF 0x00001200 | |||
mask_write 0XF8000760 0x00003FFF 0x00001200 | |||
mask_write 0XF8000764 0x00003FFF 0x00001200 | |||
mask_write 0XF8000768 0x00003FFF 0x00001200 | |||
mask_write 0XF800076C 0x00003FFF 0x00001200 | |||
mask_write 0XF8000770 0x00003FFF 0x00001200 | |||
mask_write 0XF8000774 0x00003FFF 0x00001200 | |||
mask_write 0XF8000778 0x00003FFF 0x00001200 | |||
mask_write 0XF800077C 0x00003FFF 0x00001200 | |||
mask_write 0XF8000780 0x00003FFF 0x00001200 | |||
mask_write 0XF8000784 0x00003FFF 0x00001200 | |||
mask_write 0XF8000788 0x00003FFF 0x00001200 | |||
mask_write 0XF800078C 0x00003FFF 0x00001200 | |||
mask_write 0XF8000790 0x00003FFF 0x00001200 | |||
mask_write 0XF8000794 0x00003FFF 0x00001200 | |||
mask_write 0XF8000798 0x00003FFF 0x00001200 | |||
mask_write 0XF800079C 0x00003FFF 0x00001200 | |||
mask_write 0XF80007A0 0x00003FFF 0x00001280 | |||
mask_write 0XF80007A4 0x00003FFF 0x00001280 | |||
mask_write 0XF80007A8 0x00003FFF 0x00001280 | |||
mask_write 0XF80007AC 0x00003FFF 0x00001280 | |||
mask_write 0XF80007B0 0x00003FFF 0x00001280 | |||
mask_write 0XF80007B4 0x00003FFF 0x00001280 | |||
mask_write 0XF80007B8 0x00003FFF 0x00001200 | |||
mask_write 0XF80007BC 0x00003FFF 0x00001200 | |||
mask_write 0XF80007C0 0x00003FFF 0x000012E0 | |||
mask_write 0XF80007C4 0x00003FFF 0x000012E1 | |||
mask_write 0XF80007C8 0x00003FFF 0x00001200 | |||
mask_write 0XF80007CC 0x00003FFF 0x00001200 | |||
mask_write 0XF80007D0 0x00003FFF 0x00001200 | |||
mask_write 0XF80007D4 0x00003FFF 0x00001200 | |||
mask_write 0XF8000830 0x003F003F 0x00380037 | |||
mwr -force 0XF8000004 0x0000767B | |||
} | |||
proc ps7_peripherals_init_data_1_0 {} { | |||
mwr -force 0XF8000008 0x0000DF0D | |||
mask_write 0XF8000B48 0x00000180 0x00000180 | |||
mask_write 0XF8000B4C 0x00000180 0x00000180 | |||
mask_write 0XF8000B50 0x00000180 0x00000180 | |||
mask_write 0XF8000B54 0x00000180 0x00000180 | |||
mwr -force 0XF8000004 0x0000767B | |||
mask_write 0XE0001034 0x000000FF 0x00000006 | |||
mask_write 0XE0001018 0x0000FFFF 0x0000007C | |||
mask_write 0XE0001000 0x000001FF 0x00000017 | |||
mask_write 0XE0001004 0x00000FFF 0x00000020 | |||
mask_write 0XE000D000 0x00080000 0x00080000 | |||
mask_write 0XF8007000 0x20000000 0x00000000 | |||
mask_write 0XE000A204 0xFFFFFFFF 0x00000004 | |||
mask_write 0XE000A000 0xFFFFFFFF 0xFFFB0004 | |||
mask_write 0XE000A208 0xFFFFFFFF 0x00000004 | |||
mask_write 0XE000A000 0xFFFFFFFF 0xFFFB0000 | |||
mask_delay 0XF8F00200 1 | |||
mask_write 0XE000A000 0xFFFFFFFF 0xFFFB0004 | |||
} | |||
proc ps7_post_config_1_0 {} { | |||
mwr -force 0XF8000008 0x0000DF0D | |||
mask_write 0XF8000900 0x0000000F 0x0000000F | |||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000 | |||
mwr -force 0XF8000004 0x0000767B | |||
} | |||
proc ps7_debug_1_0 {} { | |||
mwr -force 0XF8898FB0 0xC5ACCE55 | |||
mwr -force 0XF8899FB0 0xC5ACCE55 | |||
mwr -force 0XF8809FB0 0xC5ACCE55 | |||
} | |||
set PCW_SILICON_VER_1_0 "0x0" | |||
set PCW_SILICON_VER_2_0 "0x1" | |||
set PCW_SILICON_VER_3_0 "0x2" | |||
set APU_FREQ 666666666 | |||
proc mask_poll { addr mask } { | |||
set count 1 | |||
set curval "0x[string range [mrd $addr] end-8 end]" | |||
set maskedval [expr {$curval & $mask}] | |||
while { $maskedval == 0 } { | |||
set curval "0x[string range [mrd $addr] end-8 end]" | |||
set maskedval [expr {$curval & $mask}] | |||
set count [ expr { $count + 1 } ] | |||
if { $count == 100000000 } { | |||
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" | |||
break | |||
} | |||
} | |||
} | |||
proc mask_delay { addr val } { | |||
set delay [ get_number_of_cycles_for_delay $val ] | |||
perf_reset_and_start_timer | |||
set curval "0x[string range [mrd $addr] end-8 end]" | |||
set maskedval [expr {$curval < $delay}] | |||
while { $maskedval == 1 } { | |||
set curval "0x[string range [mrd $addr] end-8 end]" | |||
set maskedval [expr {$curval < $delay}] | |||
} | |||
perf_reset_clock | |||
} | |||
proc ps_version { } { | |||
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" | |||
set mask_sil_ver "0x[expr {$si_ver >> 28}]" | |||
return $mask_sil_ver; | |||
} | |||
proc ps7_post_config {} { | |||
set saved_mode [configparams force-mem-accesses] | |||
configparams force-mem-accesses 1 | |||
variable PCW_SILICON_VER_1_0 | |||
variable PCW_SILICON_VER_2_0 | |||
variable PCW_SILICON_VER_3_0 | |||
set sil_ver [ps_version] | |||
if { $sil_ver == $PCW_SILICON_VER_1_0} { | |||
ps7_post_config_1_0 | |||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { | |||
ps7_post_config_2_0 | |||
} else { | |||
ps7_post_config_3_0 | |||
} | |||
configparams force-mem-accesses $saved_mode | |||
} | |||
proc ps7_debug {} { | |||
variable PCW_SILICON_VER_1_0 | |||
variable PCW_SILICON_VER_2_0 | |||
variable PCW_SILICON_VER_3_0 | |||
set sil_ver [ps_version] | |||
if { $sil_ver == $PCW_SILICON_VER_1_0} { | |||
ps7_debug_1_0 | |||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { | |||
ps7_debug_2_0 | |||
} else { | |||
ps7_debug_3_0 | |||
} | |||
} | |||
proc ps7_init {} { | |||
variable PCW_SILICON_VER_1_0 | |||
variable PCW_SILICON_VER_2_0 | |||
variable PCW_SILICON_VER_3_0 | |||
set sil_ver [ps_version] | |||
if { $sil_ver == $PCW_SILICON_VER_1_0} { | |||
ps7_mio_init_data_1_0 | |||
ps7_pll_init_data_1_0 | |||
ps7_clock_init_data_1_0 | |||
ps7_ddr_init_data_1_0 | |||
ps7_peripherals_init_data_1_0 | |||
#puts "PCW Silicon Version : 1.0" | |||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { | |||
ps7_mio_init_data_2_0 | |||
ps7_pll_init_data_2_0 | |||
ps7_clock_init_data_2_0 | |||
ps7_ddr_init_data_2_0 | |||
ps7_peripherals_init_data_2_0 | |||
#puts "PCW Silicon Version : 2.0" | |||
} else { | |||
ps7_mio_init_data_3_0 | |||
ps7_pll_init_data_3_0 | |||
ps7_clock_init_data_3_0 | |||
ps7_ddr_init_data_3_0 | |||
ps7_peripherals_init_data_3_0 | |||
#puts "PCW Silicon Version : 3.0" | |||
} | |||
} | |||
# For delay calculation using global timer | |||
# start timer | |||
proc perf_start_clock { } { | |||
#writing SCU_GLOBAL_TIMER_CONTROL register | |||
mask_write 0xF8F00208 0x00000109 0x00000009 | |||
} | |||
# stop timer and reset timer count regs | |||
proc perf_reset_clock { } { | |||
perf_disable_clock | |||
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 | |||
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 | |||
} | |||
# Compute mask for given delay in miliseconds | |||
proc get_number_of_cycles_for_delay { delay } { | |||
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) | |||
variable APU_FREQ | |||
return [ expr ($delay * $APU_FREQ /(2 * 1000))] | |||
} | |||
# stop timer | |||
proc perf_disable_clock {} { | |||
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 | |||
} | |||
proc perf_reset_and_start_timer {} { | |||
perf_reset_clock | |||
perf_start_clock | |||
} | |||
@@ -0,0 +1,131 @@ | |||
/****************************************************************************** | |||
* | |||
* Copyright (C) 2018 Xilinx, Inc. All rights reserved. | |||
* | |||
* This program is free software; you can redistribute it and/or modify | |||
* it under the terms of the GNU General Public License as published by | |||
* the Free Software Foundation; either version 2 of the License, or | |||
* (at your option) any later version. | |||
* | |||
* This program is distributed in the hope that it will be useful, | |||
* but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
* GNU General Public License for more details. | |||
* | |||
* You should have received a copy of the GNU General Public License along | |||
* with this program; if not, see <http://www.gnu.org/licenses/> | |||
* | |||
* | |||
******************************************************************************/ | |||
/****************************************************************************/ | |||
/** | |||
* | |||
* @file ps7_init_gpl.h | |||
* | |||
* This file can be included in FSBL code | |||
* to get prototype of ps7_init() function | |||
* and error codes | |||
* | |||
*****************************************************************************/ | |||
#ifdef __cplusplus | |||
extern "C" { | |||
#endif | |||
//typedef unsigned int u32; | |||
/** do we need to make this name more unique ? **/ | |||
//extern u32 ps7_init_data[]; | |||
extern unsigned long * ps7_ddr_init_data; | |||
extern unsigned long * ps7_mio_init_data; | |||
extern unsigned long * ps7_pll_init_data; | |||
extern unsigned long * ps7_clock_init_data; | |||
extern unsigned long * ps7_peripherals_init_data; | |||
#define OPCODE_EXIT 0U | |||
#define OPCODE_CLEAR 1U | |||
#define OPCODE_WRITE 2U | |||
#define OPCODE_MASKWRITE 3U | |||
#define OPCODE_MASKPOLL 4U | |||
#define OPCODE_MASKDELAY 5U | |||
#define NEW_PS7_ERR_CODE 1 | |||
/* Encode number of arguments in last nibble */ | |||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) | |||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr | |||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val | |||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val | |||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask | |||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask | |||
/* Returns codes of PS7_Init */ | |||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C | |||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now | |||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out | |||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init | |||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit | |||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init | |||
/* Silicon Versions */ | |||
#define PCW_SILICON_VERSION_1 0 | |||
#define PCW_SILICON_VERSION_2 1 | |||
#define PCW_SILICON_VERSION_3 2 | |||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ | |||
#define PS7_POST_CONFIG | |||
/* Freq of all peripherals */ | |||
#define APU_FREQ 666666687 | |||
#define DDR_FREQ 533333374 | |||
#define DCI_FREQ 10158730 | |||
#define QSPI_FREQ 10000000 | |||
#define SMC_FREQ 10000000 | |||
#define ENET0_FREQ 10000000 | |||
#define ENET1_FREQ 10000000 | |||
#define USB0_FREQ 60000000 | |||
#define USB1_FREQ 60000000 | |||
#define SDIO_FREQ 50000000 | |||
#define UART_FREQ 100000000 | |||
#define SPI_FREQ 10000000 | |||
#define I2C_FREQ 111111115 | |||
#define WDT_FREQ 111111115 | |||
#define TTC_FREQ 50000000 | |||
#define CAN_FREQ 10000000 | |||
#define PCAP_FREQ 200000000 | |||
#define TPIU_FREQ 200000000 | |||
#define FPGA0_FREQ 75000000 | |||
#define FPGA1_FREQ 10000000 | |||
#define FPGA2_FREQ 10000000 | |||
#define FPGA3_FREQ 10000000 | |||
/* For delay calculation using global registers*/ | |||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 | |||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 | |||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 | |||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 | |||
int ps7_config( unsigned long*); | |||
int ps7_init(); | |||
int ps7_post_config(); | |||
int ps7_debug(); | |||
char* getPS7MessageInfo(unsigned key); | |||
void perf_start_clock(void); | |||
void perf_disable_clock(void); | |||
void perf_reset_clock(void); | |||
void perf_reset_and_start_timer(); | |||
int get_number_of_cycles_for_delay(unsigned int delay); | |||
#ifdef __cplusplus | |||
} | |||
#endif | |||
@@ -0,0 +1,240 @@ | |||
//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. | |||
//-------------------------------------------------------------------------------- | |||
//Tool Version: Vivado v.2018.3 (lin64) Build 2405991 Thu Dec 6 23:36:41 MST 2018 | |||
//Date : Tue Jan 8 15:24:37 2019 | |||
//Host : doom running 64-bit Debian GNU/Linux buster/sid | |||
//Command : generate_target zz9000_ps_wrapper.bd | |||
//Design : zz9000_ps_wrapper | |||
//Purpose : IP block netlist | |||
//-------------------------------------------------------------------------------- | |||
`timescale 1 ps / 1 ps | |||
module zz9000_ps_wrapper | |||
(DDR_addr, | |||
DDR_ba, | |||
DDR_cas_n, | |||
DDR_ck_n, | |||
DDR_ck_p, | |||
DDR_cke, | |||
DDR_cs_n, | |||
DDR_dm, | |||
DDR_dq, | |||
DDR_dqs_n, | |||
DDR_dqs_p, | |||
DDR_odt, | |||
DDR_ras_n, | |||
DDR_reset_n, | |||
DDR_we_n, | |||
FIXED_IO_ddr_vrn, | |||
FIXED_IO_ddr_vrp, | |||
FIXED_IO_mio, | |||
FIXED_IO_ps_clk, | |||
FIXED_IO_ps_porb, | |||
FIXED_IO_ps_srstb, | |||
HDMI_INTN, | |||
I2C0_scl_io, | |||
I2C0_sda_io, | |||
VGA_B, | |||
VGA_DE, | |||
VGA_G, | |||
VGA_HS, | |||
VGA_PCLK, | |||
VGA_R, | |||
VGA_VS, | |||
ZORRO_ADDR, | |||
ZORRO_ADDRDIR, | |||
ZORRO_DATA, | |||
ZORRO_DATADIR, | |||
ZORRO_DOE, | |||
ZORRO_E7M, | |||
ZORRO_NCCS, | |||
ZORRO_NCFGIN, | |||
ZORRO_NCFGOUT, | |||
ZORRO_NCINH, | |||
ZORRO_NDS0, | |||
ZORRO_NDS1, | |||
ZORRO_NDTACK, | |||
ZORRO_NFCS, | |||
ZORRO_NIORST, | |||
ZORRO_NLDS, | |||
ZORRO_NMTCR, | |||
ZORRO_NSLAVE, | |||
ZORRO_NUDS, | |||
ZORRO_READ); | |||
inout [14:0]DDR_addr; | |||
inout [2:0]DDR_ba; | |||
inout DDR_cas_n; | |||
inout DDR_ck_n; | |||
inout DDR_ck_p; | |||
inout DDR_cke; | |||
inout DDR_cs_n; | |||
inout [3:0]DDR_dm; | |||
inout [31:0]DDR_dq; | |||
inout [3:0]DDR_dqs_n; | |||
inout [3:0]DDR_dqs_p; | |||
inout DDR_odt; | |||
inout DDR_ras_n; | |||
inout DDR_reset_n; | |||
inout DDR_we_n; | |||
inout FIXED_IO_ddr_vrn; | |||
inout FIXED_IO_ddr_vrp; | |||
inout [53:0]FIXED_IO_mio; | |||
inout FIXED_IO_ps_clk; | |||
inout FIXED_IO_ps_porb; | |||
inout FIXED_IO_ps_srstb; | |||
inout HDMI_INTN; | |||
inout I2C0_scl_io; | |||
inout I2C0_sda_io; | |||
output [4:0]VGA_B; | |||
output VGA_DE; | |||
output [5:0]VGA_G; | |||
output VGA_HS; | |||
output VGA_PCLK; | |||
output [4:0]VGA_R; | |||
output VGA_VS; | |||
inout [22:0]ZORRO_ADDR; | |||
output ZORRO_ADDRDIR; | |||
inout [15:0]ZORRO_DATA; | |||
output ZORRO_DATADIR; | |||
input ZORRO_DOE; | |||
input ZORRO_E7M; | |||
input ZORRO_NCCS; | |||
input ZORRO_NCFGIN; | |||
output ZORRO_NCFGOUT; | |||
output ZORRO_NCINH; | |||
input ZORRO_NDS0; | |||
input ZORRO_NDS1; | |||
output ZORRO_NDTACK; | |||
input ZORRO_NFCS; | |||
input ZORRO_NIORST; | |||
input ZORRO_NLDS; | |||
input ZORRO_NMTCR; | |||
output ZORRO_NSLAVE; | |||
input ZORRO_NUDS; | |||
input ZORRO_READ; | |||
wire [14:0]DDR_addr; | |||
wire [2:0]DDR_ba; | |||
wire DDR_cas_n; | |||
wire DDR_ck_n; | |||
wire DDR_ck_p; | |||
wire DDR_cke; | |||
wire DDR_cs_n; | |||
wire [3:0]DDR_dm; | |||
wire [31:0]DDR_dq; | |||
wire [3:0]DDR_dqs_n; | |||
wire [3:0]DDR_dqs_p; | |||
wire DDR_odt; | |||
wire DDR_ras_n; | |||
wire DDR_reset_n; | |||
wire DDR_we_n; | |||
wire FIXED_IO_ddr_vrn; | |||
wire FIXED_IO_ddr_vrp; | |||
wire [53:0]FIXED_IO_mio; | |||
wire FIXED_IO_ps_clk; | |||
wire FIXED_IO_ps_porb; | |||
wire FIXED_IO_ps_srstb; | |||
wire HDMI_INTN; | |||
wire I2C0_scl_i; | |||
wire I2C0_scl_io; | |||
wire I2C0_scl_o; | |||
wire I2C0_scl_t; | |||
wire I2C0_sda_i; | |||
wire I2C0_sda_io; | |||
wire I2C0_sda_o; | |||
wire I2C0_sda_t; | |||
wire [4:0]VGA_B; | |||
wire VGA_DE; | |||
wire [5:0]VGA_G; | |||
wire VGA_HS; | |||
wire VGA_PCLK; | |||
wire [4:0]VGA_R; | |||
wire VGA_VS; | |||
wire [22:0]ZORRO_ADDR; | |||
wire ZORRO_ADDRDIR; | |||
wire [15:0]ZORRO_DATA; | |||
wire ZORRO_DATADIR; | |||
wire ZORRO_DOE; | |||
wire ZORRO_E7M; | |||
wire ZORRO_NCCS; | |||
wire ZORRO_NCFGIN; | |||
wire ZORRO_NCFGOUT; | |||
wire ZORRO_NCINH; | |||
wire ZORRO_NDS0; | |||
wire ZORRO_NDS1; | |||
wire ZORRO_NDTACK; | |||
wire ZORRO_NFCS; | |||
wire ZORRO_NIORST; | |||
wire ZORRO_NLDS; | |||
wire ZORRO_NMTCR; | |||
wire ZORRO_NSLAVE; | |||
wire ZORRO_NUDS; | |||
wire ZORRO_READ; | |||
IOBUF I2C0_scl_iobuf | |||
(.I(I2C0_scl_o), | |||
.IO(I2C0_scl_io), | |||
.O(I2C0_scl_i), | |||
.T(I2C0_scl_t)); | |||
IOBUF I2C0_sda_iobuf | |||
(.I(I2C0_sda_o), | |||
.IO(I2C0_sda_io), | |||
.O(I2C0_sda_i), | |||
.T(I2C0_sda_t)); | |||
zz9000_ps zz9000_ps_i | |||
(.DDR_addr(DDR_addr), | |||
.DDR_ba(DDR_ba), | |||
.DDR_cas_n(DDR_cas_n), | |||
.DDR_ck_n(DDR_ck_n), | |||
.DDR_ck_p(DDR_ck_p), | |||
.DDR_cke(DDR_cke), | |||
.DDR_cs_n(DDR_cs_n), | |||
.DDR_dm(DDR_dm), | |||
.DDR_dq(DDR_dq), | |||
.DDR_dqs_n(DDR_dqs_n), | |||
.DDR_dqs_p(DDR_dqs_p), | |||
.DDR_odt(DDR_odt), | |||
.DDR_ras_n(DDR_ras_n), | |||
.DDR_reset_n(DDR_reset_n), | |||
.DDR_we_n(DDR_we_n), | |||
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn), | |||
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp), | |||
.FIXED_IO_mio(FIXED_IO_mio), | |||
.FIXED_IO_ps_clk(FIXED_IO_ps_clk), | |||
.FIXED_IO_ps_porb(FIXED_IO_ps_porb), | |||
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb), | |||
.HDMI_INTN(HDMI_INTN), | |||
.I2C0_scl_i(I2C0_scl_i), | |||
.I2C0_scl_o(I2C0_scl_o), | |||
.I2C0_scl_t(I2C0_scl_t), | |||
.I2C0_sda_i(I2C0_sda_i), | |||
.I2C0_sda_o(I2C0_sda_o), | |||
.I2C0_sda_t(I2C0_sda_t), | |||
.VGA_B(VGA_B), | |||
.VGA_DE(VGA_DE), | |||
.VGA_G(VGA_G), | |||
.VGA_HS(VGA_HS), | |||
.VGA_PCLK(VGA_PCLK), | |||
.VGA_R(VGA_R), | |||
.VGA_VS(VGA_VS), | |||
.ZORRO_ADDR(ZORRO_ADDR), | |||
.ZORRO_ADDRDIR(ZORRO_ADDRDIR), | |||
.ZORRO_DATA(ZORRO_DATA), | |||
.ZORRO_DATADIR(ZORRO_DATADIR), | |||
.ZORRO_DOE(ZORRO_DOE), | |||
.ZORRO_E7M(ZORRO_E7M), | |||
.ZORRO_NCCS(ZORRO_NCCS), | |||
.ZORRO_NCFGIN(ZORRO_NCFGIN), | |||
.ZORRO_NCFGOUT(ZORRO_NCFGOUT), | |||
.ZORRO_NCINH(ZORRO_NCINH), | |||
.ZORRO_NDS0(ZORRO_NDS0), | |||
.ZORRO_NDS1(ZORRO_NDS1), | |||
.ZORRO_NDTACK(ZORRO_NDTACK), | |||
.ZORRO_NFCS(ZORRO_NFCS), | |||
.ZORRO_NIORST(ZORRO_NIORST), | |||
.ZORRO_NLDS(ZORRO_NLDS), | |||
.ZORRO_NMTCR(ZORRO_NMTCR), | |||
.ZORRO_NSLAVE(ZORRO_NSLAVE), | |||
.ZORRO_NUDS(ZORRO_NUDS), | |||
.ZORRO_READ(ZORRO_READ)); | |||
endmodule |
@@ -0,0 +1,141 @@ | |||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?><!-- | |||
################################################################################ | |||
# | |||
# MYiR Z-turn Board Definition File | |||
# | |||
# Sergiusz 'q3k' Bazaลski <q3k@q3k.org> | |||
# Steffen 'stv0g' Vogel <stv0g@0l.de> | |||
# | |||
################################################################################--> | |||
<board name="mys-7z020" schema_version="2.1" vendor="myir.com" display_name="Z-turn Board (MYS-7Z020-C)" url="http://www.myirtech.com/list.asp?id=502" preset_file="preset.xml"> | |||
<images> | |||
<image name="zturn_board.jpg" display_name="Z-turn Board" sub_type="board"> | |||
<description>Z-turn Board top image</description> | |||
</image> | |||
</images> | |||
<description>The Z-turn board is a cheap Zynq evaluation board from the Chinese company MYiR Technologies.</description> | |||
<file_version>2.1</file_version> | |||
<compatible_board_revisions> | |||
<revision id="0">4</revision> | |||
</compatible_board_revisions> | |||
<components> | |||
<component name="part0" display_name="Z-turn Board" type="fpga" part_name="xc7z020clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="http://www.myirtech.com/list.asp?id=502"> | |||
<description>FPGA part on the board</description> | |||
<interfaces> | |||
<interface name="ps7_fixedio" mode="master" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset" /> | |||
<interface name="rgb_led" mode="master" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="rgb_led_preset"> | |||
<preferred_ips> | |||
<preferred_ip name="axi_gpio" vendor="xilinx.com" library="ip" order="0" /> | |||
</preferred_ips> | |||
<port_maps> | |||
<port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="2" right="0"> | |||
<pin_maps> | |||
<pin_map port_index="0" component_pin="rgb_led_tri_o_0" /> | |||
<pin_map port_index="1" component_pin="rgb_led_tri_o_1" /> | |||
<pin_map port_index="2" component_pin="rgb_led_tri_o_2" /> | |||
</pin_maps> | |||
</port_map> | |||
</port_maps> | |||
</interface> | |||
<interface name="buzzer" mode="master" type="xilinx.com:interface:gpio_rtl:1.0" of_component="buzzer" preset_proc="buzzer_preset"> | |||
<preferred_ips> | |||
<preferred_ip name="axi_gpio" vendor="xilinx.com" library="ip" order="0" /> | |||
</preferred_ips> | |||
<port_maps> | |||
<port_map logical_port="TRI_O" physical_port="buzzer_tri_o" dir="out"> | |||
<pin_maps> | |||
<pin_map port_index="0" component_pin="buzzer_tri_o_0" /> | |||
</pin_maps> | |||
</port_map> | |||
</port_maps> | |||
</interface> | |||
<interface name="sws_4bits" mode="master" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_4bits" preset_proc="sws_4bits_preset"> | |||
<preferred_ips> | |||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0" /> | |||
</preferred_ips> | |||
<port_maps> | |||
<port_map logical_port="TRI_I" physical_port="sws_4bits_tri_i" dir="in" left="3" right="0"> | |||
<pin_maps> | |||
<pin_map port_index="0" component_pin="sws_4bits_tri_i_0" /> | |||
<pin_map port_index="1" component_pin="sws_4bits_tri_i_1" /> | |||
<pin_map port_index="2" component_pin="sws_4bits_tri_i_2" /> | |||
<pin_map port_index="3" component_pin="sws_4bits_tri_i_3" /> | |||
</pin_maps> | |||
</port_map> | |||
</port_maps> | |||
</interface> | |||
<interface mode="master" name="i2c0" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c0"> | |||
<description>I2C Interface for onboard G-rate and temperature sensors</description> | |||
<preferred_ips> | |||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0" /> | |||
</preferred_ips> | |||
<port_maps> | |||
<port_map logical_port="SDA_I" physical_port="i2c0_sda_i" dir="in"> | |||
<pin_maps> | |||
<pin_map port_index="0" component_pin="i2c0_sda_i" /> | |||
</pin_maps> | |||
</port_map> | |||
<port_map logical_port="SDA_O" physical_port="i2c0_sda_o" dir="out"> | |||
<pin_maps> | |||
<pin_map port_index="0" component_pin="i2c0_sda_i" /> | |||
</pin_maps> | |||
</port_map> | |||
<port_map logical_port="SDA_T" physical_port="i2c0_sda_t" dir="out"> | |||
<pin_maps> | |||
<pin_map port_index="0" component_pin="i2c0_sda_i" /> | |||
</pin_maps> | |||
</port_map> | |||
<port_map logical_port="SCL_I" physical_port="i2c0_scl_i" dir="in"> | |||
<pin_maps> | |||
<pin_map port_index="0" component_pin="i2c0_scl_i" /> | |||
</pin_maps> | |||
</port_map> | |||
<port_map logical_port="SCL_O" physical_port="i2c0_scl_o" dir="out"> | |||
<pin_maps> | |||
<pin_map port_index="0" component_pin="i2c0_scl_i" /> | |||
</pin_maps> | |||
</port_map> | |||
<port_map logical_port="SCL_T" physical_port="i2c0_scl_t" dir="out"> | |||
<pin_maps> | |||
<pin_map port_index="0" component_pin="i2c0_scl_i" /> | |||
</pin_maps> | |||
</port_map> | |||
</port_maps> | |||
</interface> | |||
</interfaces> | |||
</component> | |||
<component name="ps7_fixedio" display_name="PS7 fixed IO" type="chip" sub_type="fixed_io" major_group="" /> | |||
<component name="buzzer" display_name="Piezo Buzzer" type="chip" sub_type="led" major_group="General Purpose Input or Output"> | |||
<description>Piezo Buzzer on Board (Schematic: M1)</description> | |||
</component> | |||
<component name="rgb_led" display_name="RGB LED" type="chip" sub_type="led" major_group="General Purpose Input or Output"> | |||
<description>RGB LED, 2 to 0, Active Low (Schematic: D34)</description> | |||
</component> | |||
<component name="sws_4bits" display_name="DIP switches" type="chip" sub_type="switch" major_group="General Purpose Input or Output"> | |||
<description>DIP Switches, 3 to 0 (Schematic: U20)</description> | |||
</component> | |||
<component name="i2c0" display_name="IIC" type="chip" sub_type="mux" major_group="Miscellaneous"> | |||
<description>I2C Bus 0 wired to PL</description> | |||
</component> | |||
</components> | |||
<jtag_chains> | |||
<jtag_chain name="chain1"> | |||
<position name="0" component="part0" /> | |||
</jtag_chain> | |||
</jtag_chains> | |||
<connections> | |||
<connection name="part0_rgb_led" component1="part0" component2="rgb_led"> | |||
<connection_map name="part0_rgb_led_1" c1_st_index="4" c1_end_index="6" c2_st_index="0" c2_end_index="2" /> | |||
</connection> | |||
<connection name="part0_sws_4bits" component1="part0" component2="sws_4bits"> | |||
<connection_map name="part0_sws_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3" /> | |||
</connection> | |||
<connection name="part0_buzzer" component1="part0" component2="buzzer"> | |||
<connection_map name="part0_buzzer_1" c1_st_index="7" c1_end_index="7" c2_st_index="0" c2_end_index="0" /> | |||
</connection> | |||
<connection name="part0_i2c0" component1="part0" component2="i2c0"> | |||
<connection_map name="part0_i2c0_1" c1_st_index="8" c1_end_index="9" c2_st_index="0" c2_end_index="1" /> | |||
</connection> | |||
</connections> | |||
</board> |
@@ -0,0 +1,324 @@ | |||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?><!-- | |||
################################################################################ | |||
# | |||
# MYiR Z-turn Board IP Presets | |||
# | |||
# Sergiusz 'q3k' Bazaลski <q3k@q3k.org> | |||
# Steffen 'stv0g' Vogel <stv0g@0l.de> | |||
# | |||
################################################################################--> | |||
<ip_presets schema="1.0"> | |||
<ip_preset preset_proc_name="ps7_preset"> | |||
<ip vendor="xilinx.com" library="ip" name="processing_system7" version="*"> | |||
<user_parameters> | |||
<!--######################################################################## | |||
# PS Bank Voltage, Busses, Clocks | |||
########################################################################--> | |||
<user_parameter name="CONFIG.PCW_PRESET_BANK0_VOLTAGE" value="LVCMOS 3.3V" /> | |||
<user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 1.8V" /> | |||
<user_parameter name="CONFIG.PCW_PACKAGE_NAME" value="clg400" /> | |||
<user_parameter name="CONFIG.PCW_USE_M_AXI_GP0" value="1" /> | |||
<user_parameter name="CONFIG.PCW_USE_M_AXI_GP1" value="0" /> | |||
<user_parameter name="CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ" value="33.333333" /> | |||
<user_parameter name="CONFIG.PCW_ARMPLL_CTRL_FBDIV" value="40" /> | |||
<user_parameter name="CONFIG.PCW_APU_CLK_RATIO_ENABLE" value="6:2:1" /> | |||
<user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_CLKSRC" value="ARM PLL" /> | |||
<user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_CLKSRC" value="DDR PLL" /> | |||
<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC" value="IO PLL" /> | |||
<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC" value="ARM PLL" /> | |||
<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC" value="IO PLL" /> | |||
<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_CLKSRC" value="IO PLL" /> | |||
<user_parameter name="CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" value="CPU_1X" /> | |||
<user_parameter name="CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" value="CPU_1X" /> | |||
<user_parameter name="CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" value="CPU_1X" /> | |||
<user_parameter name="CONFIG.PCW_APU_PERIPHERAL_FREQMHZ" value="666.666666" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ" value="533.333333" /> | |||
<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ" value="1000 Mbps" /> | |||
<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ" value="100" /> | |||
<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ" value="200.000000" /> | |||
<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_FREQMHZ" value="100" /> | |||
<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ" value="60" /> | |||
<user_parameter name="CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" value="133.333333" /> | |||
<user_parameter name="CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" value="133.333333" /> | |||
<user_parameter name="CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" value="133.333333" /> | |||
<!--######################################################################## | |||
# Fabric Clocks - CLK0 enabled, CLK[3:1] disabled by default | |||
########################################################################--> | |||
<user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC" value="IO PLL" /> | |||
<user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC" value="IO PLL" /> | |||
<user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC" value="IO PLL" /> | |||
<user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC" value="IO PLL" /> | |||
<user_parameter name="CONFIG.PCW_FCLK_CLK0_BUF" value="true" /> | |||
<user_parameter name="CONFIG.PCW_FCLK_CLK1_BUF" value="true" /> | |||
<user_parameter name="CONFIG.PCW_FCLK_CLK2_BUF" value="false" /> | |||
<user_parameter name="CONFIG.PCW_FCLK_CLK3_BUF" value="false" /> | |||
<user_parameter name="CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ" value="100" /> | |||
<user_parameter name="CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ" value="50" /> | |||
<user_parameter name="CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ" value="50" /> | |||
<user_parameter name="CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ" value="50" /> | |||
<user_parameter name="CONFIG.PCW_EN_CLK0_PORT" value="1" /> | |||
<user_parameter name="CONFIG.PCW_EN_CLK1_PORT" value="1" /> | |||
<user_parameter name="CONFIG.PCW_EN_CLK2_PORT" value="0" /> | |||
<user_parameter name="CONFIG.PCW_EN_CLK3_PORT" value="0" /> | |||
<user_parameter name="CONFIG.PCW_EN_RST0_PORT" value="1" /> | |||
<user_parameter name="CONFIG.PCW_EN_RST1_PORT" value="0" /> | |||
<user_parameter name="CONFIG.PCW_EN_RST2_PORT" value="0" /> | |||
<user_parameter name="CONFIG.PCW_EN_RST3_PORT" value="0" /> | |||
<!--######################################################################## | |||
# DDR3 | |||
########################################################################--> | |||
<user_parameter name="CONFIG.PCW_EN_DDR" value="1" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41J256M16 RE-125" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY" value="4096 MBits" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_FAW" value="40.0" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RC" value="48.91" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CWL" value="6" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH" value="16 Bits" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN" value="35.0" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_SPEED_BIN" value="DDR3_1066F" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" value="0" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" value="0" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" value="0" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" value="0" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" value="0" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" value="0" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" value="0" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" value="0" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" value="0" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" value="0" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" value="0" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" value="0" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE" value="1" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" value="1" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE" value="1" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="0.229" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="0.250" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" value="0.121" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" value="0.146" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" value="0.271" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" value="0.259" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" value="0.219" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" value="0.207" /> | |||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF" value="0" /> | |||
<!--######################################################################## | |||
# Peripheral assignments | |||
########################################################################--> | |||
<user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO" value="MIO 1 .. 6" /> | |||
<user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 51" /> | |||
<user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_IO" value="MIO 8" /> | |||
<user_parameter name="CONFIG.PCW_UART0_UART0_IO" value="MIO 10 .. 11" /> | |||
<user_parameter name="CONFIG.PCW_I2C0_I2C0_IO" value="EMIO" /> | |||
<user_parameter name="CONFIG.PCW_I2C1_I2C1_IO" value="MIO 12 .. 13" /> | |||
<user_parameter name="CONFIG.PCW_CAN0_CAN0_IO" value="MIO 14 .. 15" /> | |||
<user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27" /> | |||
<user_parameter name="CONFIG.PCW_USB0_USB0_IO" value="MIO 28 .. 39" /> | |||
<user_parameter name="CONFIG.PCW_SD0_SD0_IO" value="MIO 40 .. 45" /> | |||
<user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 46" /> | |||
<user_parameter name="CONFIG.PCW_SD0_GRP_WP_IO" value="MIO 47" /> | |||
<user_parameter name="CONFIG.PCW_UART1_UART1_IO" value="MIO 48 .. 49" /> | |||
<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO" value="MIO 52 .. 53" /> | |||
<user_parameter name="CONFIG.PCW_TTC0_TTC0_IO" value="EMIO" /> | |||
<!--######################################################################## | |||
# Enable Peripherals | |||
########################################################################--> | |||
<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="1" /> | |||
<user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="1" /> | |||
<user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" value="1" /> | |||
<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1" /> | |||
<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1" /> | |||
<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1" /> | |||
<user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1" /> | |||
<user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1" /> | |||
<user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="1" /> | |||
<user_parameter name="CONFIG.PCW_CAN0_PERIPHERAL_ENABLE" value="1" /> | |||
<user_parameter name="CONFIG.PCW_I2C0_PERIPHERAL_ENABLE" value="1" /> | |||
<user_parameter name="CONFIG.PCW_I2C1_PERIPHERAL_ENABLE" value="1" /> | |||
<user_parameter name="CONFIG.PCW_UART0_PERIPHERAL_ENABLE" value="1" /> | |||
<user_parameter name="CONFIG.PCW_UART1_PERIPHERAL_ENABLE" value="1" /> | |||
<user_parameter name="CONFIG.PCW_GPIO_PERIPHERAL_ENABLE" value="1" /> | |||
<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1" /> | |||
<user_parameter name="CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE" value="0" /> | |||