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master
mntmn 9 months ago
parent
commit
0f80b5e582
100 changed files with 32899 additions and 0 deletions
  1. +351
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      CW_LPC11U24.hzp
  2. +26
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      License.txt
  3. +438
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      Makefile
  4. +68
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      README.md
  5. +87
    -0
      changelog.md
  6. +668
    -0
      cmsis/LPC11Uxx.h
  7. +760
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      cmsis/LPC13Uxx.h
  8. +381
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      cmsis/RTX_CM_lib.h
  9. +104
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      cmsis/RTX_hook.c
  10. +93
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      cmsis/arm_common_tables.h
  11. +85
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      cmsis/arm_const_structs.h
  12. +7306
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      cmsis/arm_math.h
  13. +805
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      cmsis/cmsis_os.h
  14. +682
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      cmsis/core_cm0.h
  15. +1627
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      cmsis/core_cm3.h
  16. +636
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      cmsis/core_cmFunc.h
  17. +688
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      cmsis/core_cmInstr.h
  18. BIN
      cmsis/libs/libRTX_CM0.a
  19. BIN
      cmsis/libs/libRTX_CM3.a
  20. BIN
      cmsis/libs/libarm_cortexM0l_math.a
  21. BIN
      cmsis/libs/libarm_cortexM3l_math.a
  22. +90
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      cmsis/lpc11u24.ld
  23. +90
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      cmsis/lpc11u37.ld
  24. +90
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      cmsis/lpc1347.ld
  25. +447
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      cmsis/math_helper.c
  26. +53
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      cmsis/math_helper.h
  27. +273
    -0
      cmsis/startup_lpc11u_gnumake.c
  28. +754
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      cmsis/startup_lpc11u_lpc13u_codered.c
  29. +316
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      cmsis/startup_lpc13u_gnumake.c
  30. +458
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      cmsis/system_LPC11Uxx.c
  31. +64
    -0
      cmsis/system_LPC11Uxx.h
  32. +437
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      cmsis/system_LPC13Uxx.c
  33. +64
    -0
      cmsis/system_LPC13Uxx.h
  34. +134
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      doc/README.md
  35. +1864
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      doc/doxygen/LPC1347_LPC11U37_CodeBase.doxyfile
  36. +1
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      doc/doxygen/output/readme.txt
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      doc/images/CodeRed_SwitchMCU_ASM_Target.PNG
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      doc/images/CodeRed_SwitchMCU_C_Includes.PNG
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      doc/images/CodeRed_SwitchMCU_C_Symbols.PNG
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      doc/images/CodeRed_SwitchMCU_Linker_Libs.PNG
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      doc/images/CodeRed_SwitchMCU_Linker_Target.PNG
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      doc/images/CodeRed_SwitchMCU_MCUSelection.PNG
  44. +0
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      doc/toolchain_crossworks.md
  45. +58
    -0
      doc/toolchain_lpcxpresso.md
  46. +128
    -0
      doc/toolchain_make.md
  47. +46
    -0
      src/README.md
  48. +174
    -0
      src/asserts.h
  49. +88
    -0
      src/binary.h
  50. +19
    -0
      src/boards/README.md
  51. +110
    -0
      src/boards/board.h
  52. +205
    -0
      src/boards/lpcnfc/board_lpcnfc.c
  53. +656
    -0
      src/boards/lpcnfc/board_lpcnfc.h
  54. +206
    -0
      src/boards/lpcstepper/board_lpcstepper.c
  55. +660
    -0
      src/boards/lpcstepper/board_lpcstepper.h
  56. +341
    -0
      src/boards/lpcxpresso1347/board_lpcxpresso1347.c
  57. +742
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      src/boards/lpcxpresso1347/board_lpcxpresso1347.h
  58. +213
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      src/boards/lpcxpresso1347/board_lpcxpresso1347_rtxconf.h
  59. +169
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      src/boards/reform2/board_reform2.c
  60. +742
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      src/boards/reform2/board_reform2.h
  61. +711
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      src/boards/rf1ghznode/board_rf1ghznode.c
  62. +738
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      src/boards/rf1ghznode/board_rf1ghznode.h
  63. +213
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      src/boards/rf1ghznode/board_rf1ghznode_rtxconf.h
  64. +302
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      src/boards/rf1ghzusb/board_rf1ghzusb.c
  65. +711
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      src/boards/rf1ghzusb/board_rf1ghzusb.h
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      src/boards/simulator/board_simulator.c
  67. +660
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      src/boards/simulator/board_simulator.h
  68. +62
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      src/cli/README.md
  69. +94
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      src/cli/ansi.h
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      src/cli/cli.c
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      src/cli/cli.h
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      src/cli/cli_tbl.h
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      src/cli/commands.c
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      src/cli/commands.h
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      src/cli/commands/cmd_chibi_addr.c
  76. +107
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      src/cli/commands/cmd_chibi_tx.c
  77. +85
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      src/cli/commands/cmd_dbg_memrd.c
  78. +74
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      src/cli/commands/cmd_eeprom_read.c
  79. +97
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      src/cli/commands/cmd_eeprom_write.c
  80. +139
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      src/cli/commands/cmd_i2c_read.c
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      src/cli/commands/cmd_i2c_scan.c
  82. +140
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      src/cli/commands/cmd_i2c_write.c
  83. +654
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      src/cli/commands/cmd_nfc_mfc_ndef.c
  84. +194
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      src/cli/commands/cmd_nfc_mifareclassic_memdump.c
  85. +324
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      src/cli/commands/cmd_nfc_mifareclassic_valueblock.c
  86. +141
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      src/cli/commands/cmd_nfc_mifareultralight_memdump.c
  87. +71
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      src/cli/commands/cmd_rtc_read.c
  88. +116
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      src/cli/commands/cmd_rtc_write.c
  89. +181
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      src/cli/commands/cmd_sd_dir.c
  90. +193
    -0
      src/cli/commands/cmd_sysinfo.c
  91. +300
    -0
      src/cli/commands/cmd_wifi.c
  92. +154
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      src/core/adc/adc.c
  93. +57
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      src/core/adc/adc.h
  94. +66
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      src/core/debug/debug.c
  95. +51
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      src/core/debug/debug.h
  96. +252
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      src/core/delay/delay.c
  97. +85
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      src/core/delay/delay.h
  98. +119
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      src/core/dwt/dwt.h
  99. +160
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      src/core/eeprom/eeprom.c
  100. +55
    -0
      src/core/eeprom/eeprom.h

+ 351
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CW_LPC11U24.hzp View File

@@ -0,0 +1,351 @@
<!DOCTYPE CrossStudio_Project_File>
<solution Name="LPC11U24_CodeBase" target="8" version="2">
<project Name="LPC11U24_CodeBase">
<configuration Name="Common" Target="LPC11U24/401" arm_architecture="v6M" arm_core_type="Cortex-M0" arm_gcc_target="arm-unknown-eabi" arm_interwork="No" arm_linker_heap_size="0" arm_linker_stack_size="2048" arm_simulator_memory_simulation_filename="$(TargetsDir)/LPC1000/LPC1000SimulatorMemory.dll" arm_simulator_memory_simulation_parameter="LPC11Uxx;0x8000;0x2000;0x0" arm_target_debug_interface_type="ADIv5" arm_target_interface_type="SWD" arm_target_loader_parameter="12000000" c_only_additional_options="-fms-extensions;-Wall;-std=gnu99" c_preprocessor_definitions="USE_PROCESS_STACK" c_user_include_directories="$(TargetsDir)/LPC1000/include" link_include_startup_code="No" linker_additional_files="$(TargetsDir)/LPC1000/lib/liblpc1000$(LibExt)$(LIB);$(ProjectDir)/cmsis/libs/libarm_cortexM0l_math$(LIB);$(ProjectDir)/cmsis/libs/libRTX_CM0$(LIB)" linker_memory_map_file="$(TargetsDir)/LPC1000/LPC11U24_401_MemoryMap.xml" linker_output_format="bin" oscillator_frequency="12MHz" project_directory="" project_type="Executable" property_groups_file_path="$(TargetsDir)/LPC1000/propertyGroups11Uxx.xml"/>
<configuration Name="Flash" Placement="Flash" arm_target_flash_loader_file_path="$(TargetsDir)/LPC1000/Release/Loader_lpc1100.elf" arm_target_flash_loader_type="LIBMEM RPC Loader" linker_patch_build_command="&quot;$(StudioDir)/bin/crossscript&quot; &quot;load(\&quot;$(TargetsDir)/LPC1000/LPC1000_LinkPatch.js\&quot;);patch(\&quot;$(TargetPath)\&quot;);&quot;" linker_section_placement_file="$(StudioDir)/targets/Cortex_M/flash_placement.xml" target_reset_script="FLASHReset()"/>
<configuration Name="RAM" Placement="RAM" linker_section_placement_file="$(StudioDir)/targets/Cortex_M/ram_placement.xml" target_reset_script="SRAMReset()"/>
<folder Name="Source Files" file_name="">
<configuration Name="Common" filter="c;cpp;cxx;cc;h;s;asm;inc"/>
<folder Name="core" file_name="">
<folder Name="gpio">
<file file_name="src/core/gpio/gpio.c"/>
</folder>
<folder Name="uart">
<file file_name="src/core/uart/uart.c">
<configuration Name="THUMB Flash Release" build_exclude_from_build="No"/>
</file>
<file file_name="src/core/uart/uart_buf.c">
<configuration Name="THUMB Flash Release" build_exclude_from_build="No"/>
</file>
</folder>
<folder Name="i2c">
<file file_name="src/core/i2c/i2c.c">
<configuration Name="THUMB Flash Release" build_exclude_from_build="No"/>
</file>
</folder>
<folder Name="ssp0">
<file file_name="src/core/ssp0/ssp0.c">
<configuration Name="THUMB Flash Release" build_exclude_from_build="No"/>
</file>
</folder>
<folder Name="ssp1">
<file file_name="src/core/ssp1/ssp1.c"/>
</folder>
<folder Name="eeprom">
<file file_name="src/core/eeprom/eeprom.c"/>
</folder>
<folder Name="pmu">
<file file_name="src/core/pmu/pmu.c"/>
</folder>
<folder Name="adc" file_name="">
<file file_name="src/core/adc/adc.c"/>
</folder>
<folder Name="usb" file_name="">
<file file_name="src/core/usb/descriptors.c"/>
<file file_name="src/core/usb/usb_cdc.c"/>
<file file_name="src/core/usb/usb_hid.c"/>
<file file_name="src/core/usb/usbd.c"/>
<file file_name="src/core/usb/usb_msc.c"/>
<file file_name="src/core/usb/usb_custom_class.c"/>
</folder>
<folder Name="fifo" file_name="">
<file file_name="src/core/fifo/fifo.c"/>
</folder>
<folder Name="iap" file_name="">
<file file_name="src/core/iap/iap.c"/>
</folder>
<folder Name="timer32" file_name="">
<file file_name="src/core/timer32/timer32.c"/>
</folder>
<folder Name="timer16" file_name="">
<file file_name="src/core/timer16/timer16.c"/>
</folder>
<folder Name="delay" file_name="">
<file file_name="src/core/delay/delay.c"/>
</folder>
<folder Name="debug" file_name="">
<file file_name="src/core/debug/debug.c"/>
</folder>
</folder>
<folder Name="drivers">
<folder Name="displays">
<file file_name="src/drivers/displays/smallfonts.c"/>
<folder Name="bitmap">
<folder Name="ssd1306">
<file file_name="src/drivers/displays/bitmap/ssd1306/ssd1306_i2c.c"/>
</folder>
</folder>
<folder Name="graphic">
<file file_name="src/drivers/displays/graphic/aafonts.c"/>
<file file_name="src/drivers/displays/graphic/colors.c"/>
<file file_name="src/drivers/displays/graphic/drawing.c"/>
<file file_name="src/drivers/displays/graphic/fonts.c"/>
<folder Name="fonts">
<file file_name="src/drivers/displays/graphic/fonts/dejavusans9.c"/>
<file file_name="src/drivers/displays/graphic/fonts/dejavusansbold9.c"/>
<file file_name="src/drivers/displays/graphic/fonts/dejavusanscondensed9.c"/>
<file file_name="src/drivers/displays/graphic/fonts/dejavusansmono8.c"/>
<file file_name="src/drivers/displays/graphic/fonts/dejavusansmonobold8.c"/>
<file file_name="src/drivers/displays/graphic/fonts/veramono9.c"/>
<file file_name="src/drivers/displays/graphic/fonts/veramono11.c"/>
<file file_name="src/drivers/displays/graphic/fonts/veramonobold9.c"/>
<file file_name="src/drivers/displays/graphic/fonts/veramonobold11.c"/>
</folder>
<folder Name="aafonts">
<folder Name="aa2">
<file file_name="src/drivers/displays/graphic/aafonts/aa2/DejaVuSansCondensed14_AA2.c"/>
<file file_name="src/drivers/displays/graphic/aafonts/aa2/DejaVuSansCondensedBold14_AA2.c"/>
<file file_name="src/drivers/displays/graphic/aafonts/aa2/DejaVuSansMono10_AA2.c"/>
<file file_name="src/drivers/displays/graphic/aafonts/aa2/DejaVuSansMono13_AA2.c"/>
<file file_name="src/drivers/displays/graphic/aafonts/aa2/DejaVuSansMono14_AA2.c"/>
<file file_name="src/drivers/displays/graphic/aafonts/aa2/FontCalibri18_AA2.c"/>
<file file_name="src/drivers/displays/graphic/aafonts/aa2/FontCalibriBold18_AA2.c"/>
<file file_name="src/drivers/displays/graphic/aafonts/aa2/FontCalibriItalic18_AA2.c"/>
<file file_name="src/drivers/displays/graphic/aafonts/aa2/FontFranklinGothicBold99_Numbers_AA2.c"/>
</folder>
<folder Name="aa4">
<file file_name="src/drivers/displays/graphic/aafonts/aa4/FontCalibri18_AA4.c"/>
</folder>
</folder>
<folder Name="hw">
<file file_name="src/drivers/displays/graphic/hw/hx8340b.c">
<configuration Name="THUMB Flash Release" build_exclude_from_build="No"/>
<configuration Name="THUMB Flash Debug" build_exclude_from_build="No"/>
</file>
<file file_name="src/drivers/displays/graphic/hw/hx8347g.c">
<configuration Name="THUMB Flash Release" build_exclude_from_build="Yes"/>
<configuration Name="THUMB Flash Debug" build_exclude_from_build="Yes"/>
</file>
</folder>
<file file_name="src/drivers/displays/graphic/lcd.h"/>
</folder>
<folder Name="segment">
<folder Name="ht16k33">
<file file_name="src/drivers/displays/segment/ht16k33/ht16k33.c"/>
</folder>
</folder>
</folder>
<folder Name="bitbanging">
<folder Name="swspi">
<file file_name="src/drivers/bitbanging/swspi/swspi.c">
<configuration Name="THUMB Flash Release" build_exclude_from_build="No"/>
</file>
</folder>
</folder>
<folder Name="rf">
<folder Name="802.15.4">
<folder Name="chibi" file_name="">
<file file_name="src/drivers/rf/802.15.4/chibi/chb.c"/>
<file file_name="src/drivers/rf/802.15.4/chibi/chb_buf.c"/>
<file file_name="src/drivers/rf/802.15.4/chibi/chb_drvr.c"/>
<file file_name="src/drivers/rf/802.15.4/chibi/chb_eeprom.c"/>
<file file_name="src/drivers/rf/802.15.4/chibi/chb_spi.c"/>
<file file_name="src/drivers/rf/802.15.4/chibi/messages.c"/>
</folder>
</folder>
<folder Name="nfc">
<folder Name="pn532">
<folder Name="helpers" file_name="">
<file file_name="src/drivers/rf/nfc/pn532/helpers/pn532_mifare_classic.c"/>
<file file_name="src/drivers/rf/nfc/pn532/helpers/pn532_mifare_ultralight.c"/>
<file file_name="src/drivers/rf/nfc/pn532/helpers/pn532_gpio.c"/>
<file file_name="src/drivers/rf/nfc/pn532/helpers/pn532_config.c"/>
<file file_name="src/drivers/rf/nfc/pn532/helpers/pn532_ndef.c"/>
<file file_name="src/drivers/rf/nfc/pn532/helpers/pn532_ndef_cards.c"/>
</folder>
<file file_name="src/drivers/rf/nfc/pn532/pn532.c"/>
<file file_name="src/drivers/rf/nfc/pn532/pn532_bus_i2c.c"/>
<file file_name="src/drivers/rf/nfc/pn532/pn532_bus_uart.c"/>
<folder Name="mem_allocator" file_name="">
<file file_name="src/drivers/rf/nfc/pn532/mem_allocator/bget.c"/>
<file file_name="src/drivers/rf/nfc/pn532/mem_allocator/pn532_mem.c"/>
</folder>
</folder>
</folder>
<folder Name="wifi">
<folder Name="cc3000" file_name="">
<folder Name="hostdriver" file_name="">
<file file_name="src/drivers/rf/wifi/cc3000/hostdriver/cc3000_common.c"/>
<file file_name="src/drivers/rf/wifi/cc3000/hostdriver/evnt_handler.c"/>
<file file_name="src/drivers/rf/wifi/cc3000/hostdriver/hci.c"/>
<file file_name="src/drivers/rf/wifi/cc3000/hostdriver/netapp.c"/>
<file file_name="src/drivers/rf/wifi/cc3000/hostdriver/nvmem.c"/>
<file file_name="src/drivers/rf/wifi/cc3000/hostdriver/security.c"/>
<file file_name="src/drivers/rf/wifi/cc3000/hostdriver/socket.c"/>
<file file_name="src/drivers/rf/wifi/cc3000/hostdriver/wlan.c"/>
</folder>
<file file_name="src/drivers/rf/wifi/cc3000/spi.c"/>
<file file_name="src/drivers/rf/wifi/cc3000/wifi.c"/>
</folder>
</folder>
</folder>
<folder Name="storage">
<folder Name="fatfs">
<file file_name="src/drivers/storage/fatfs/ccsbcs.c">
<configuration Name="THUMB Flash Release" build_exclude_from_build="Yes"/>
<configuration Name="THUMB Flash Debug" build_exclude_from_build="Yes"/>
</file>
<file file_name="src/drivers/storage/fatfs/ff.c"/>
<file file_name="src/drivers/storage/fatfs/mmc.c"/>
<file file_name="src/drivers/storage/fatfs/ffconf.h"/>
<file file_name="src/drivers/storage/fatfs/diskio.h"/>
</folder>
<file file_name="src/drivers/storage/logger.c"/>
</folder>
<folder Name="sensors" file_name="">
<folder Name="accelerometers" file_name="">
<file file_name="src/drivers/sensors/accelerometers/lis3dh.c"/>
<file file_name="src/drivers/sensors/accelerometers/adxl345.c"/>
<file file_name="src/drivers/sensors/accelerometers/lsm303accel.c"/>
<file file_name="src/drivers/sensors/accelerometers/accelerometers.c"/>
</folder>
<folder Name="gyroscopes" file_name="">
<file file_name="src/drivers/sensors/gyroscopes/l3gd20.c"/>
</folder>
<folder Name="light" file_name="">
<file file_name="src/drivers/sensors/light/tsl2561.c"/>
</folder>
<folder Name="pressure" file_name="">
<file file_name="src/drivers/sensors/pressure/mpl115a2.c"/>
<file file_name="src/drivers/sensors/pressure/bmp085.c"/>
<file file_name="src/drivers/sensors/pressure/pressure.c"/>
</folder>
<folder Name="temperature" file_name="">
<file file_name="src/drivers/sensors/temperature/lm75b.c"/>
</folder>
<folder Name="magnetometers" file_name="">
<file file_name="src/drivers/sensors/magnetometers/lsm303mag.c"/>
<file file_name="src/drivers/sensors/magnetometers/magnetometers.c"/>
</folder>
<file file_name="src/drivers/sensors/sensors.c"/>
<file file_name="src/drivers/sensors/sensorpoll.c"/>
</folder>
<folder Name="rtc">
<file file_name="src/drivers/rtc/rtc.c"/>
<folder Name="pcf2129">
<file file_name="src/drivers/rtc/pcf2129/pcf2129.c"/>
</folder>
</folder>
<folder Name="pwm">
<folder Name="pca9685">
<file file_name="src/drivers/pwm/pca9685/pca9685.c"/>
</folder>
</folder>
<folder Name="filters" file_name="">
<folder Name="iir" file_name="">
<file file_name="src/drivers/filters/iir/iir_f.c"/>
<file file_name="src/drivers/filters/iir/iir_i.c"/>
</folder>
<folder Name="ma" file_name="">
<file file_name="src/drivers/filters/ma/sma_f.c"/>
<file file_name="src/drivers/filters/ma/sma_i.c"/>
<file file_name="src/drivers/filters/ma/sma_u16.c"/>
<file file_name="src/drivers/filters/ma/wma_f.c"/>
<file file_name="src/drivers/filters/ma/wma_i.c"/>
<file file_name="src/drivers/filters/ma/wma_u16.c"/>
</folder>
<file file_name="src/drivers/filters/ringbuffer.h"/>
</folder>
<file file_name="src/drivers/timespan.c"/>
<folder Name="motor">
<folder Name="stepper" file_name="">
<file file_name="src/drivers/motor/stepper/stepper.c"/>
</folder>
</folder>
</folder>
<folder Name="cli">
<folder Name="commands" file_name="">
<file file_name="src/cli/commands/cmd_sysinfo.c"/>
<file file_name="src/cli/commands/cmd_sd_dir.c"/>
<file file_name="src/cli/commands/cmd_i2c_scan.c"/>
<file file_name="src/cli/commands/cmd_nfc_mifareclassic_memdump.c"/>
<file file_name="src/cli/commands/cmd_nfc_mifareultralight_memdump.c"/>
<file file_name="src/cli/commands/cmd_nfc_mifareclassic_valueblock.c"/>
<file file_name="src/cli/commands/cmd_i2c_read.c"/>
<file file_name="src/cli/commands/cmd_i2c_write.c"/>
<file file_name="src/cli/commands/cmd_dbg_memrd.c"/>
<file file_name="src/cli/commands/cmd_chibi_addr.c"/>
<file file_name="src/cli/commands/cmd_chibi_tx.c"/>
<file file_name="src/cli/commands/cmd_eeprom_read.c"/>
<file file_name="src/cli/commands/cmd_eeprom_write.c"/>
<file file_name="src/cli/commands/cmd_rtc_read.c"/>
<file file_name="src/cli/commands/cmd_rtc_write.c"/>
<file file_name="src/cli/commands/cmd_nfc_mfc_ndef.c"/>
<file file_name="src/cli/commands/cmd_wifi.c"/>
</folder>
<file file_name="src/cli/cli_tbl.h"/>
<file file_name="src/cli/commands.c"/>
<file file_name="src/cli/ansi.h"/>
<file file_name="src/cli/cli.c"/>
</folder>
<file file_name="src/projectconfig.h"/>
<file file_name="src/errors.h"/>
<file file_name="src/sysdefs.h"/>
<folder Name="localisation" file_name="">
<file file_name="src/localisation/localisation.c"/>
<file file_name="src/localisation/locale_en.dat"/>
<file file_name="src/localisation/locale_fr.dat"/>
</folder>
<folder Name="boards" file_name="">
<folder Name="lpcnfc" file_name="">
<file file_name="src/boards/lpcnfc/board_lpcnfc.c"/>
<file file_name="src/boards/lpcnfc/board_lpcnfc.h"/>
</folder>
<folder Name="lpcxpresso1347" file_name="">
<file file_name="src/boards/lpcxpresso1347/board_lpcxpresso1347.c"/>
<file file_name="src/boards/lpcxpresso1347/board_lpcxpresso1347.h"/>
</folder>
<folder Name="rf1ghzusb" file_name="">
<file file_name="src/boards/rf1ghzusb/board_rf1ghzusb.c"/>
<file file_name="src/boards/rf1ghzusb/board_rf1ghzusb.h"/>
</folder>
<folder Name="rf1ghznode" file_name="">
<file file_name="src/boards/rf1ghznode/board_rf1ghznode.c"/>
<file file_name="src/boards/rf1ghznode/board_rf1ghznode.h"/>
</folder>
<folder Name="lpcstepper" file_name="">
<file file_name="src/boards/lpcstepper/board_lpcstepper.c"/>
<file file_name="src/boards/lpcstepper/board_lpcstepper.h"/>
</folder>
<folder Name="simulator" file_name="">
<file file_name="src/boards/simulator/board_simulator.c"/>
<file file_name="src/boards/simulator/board_simulator.h"/>
</folder>
</folder>
<file file_name="src/printf-retarget.c"/>
<file file_name="src/asserts.h"/>
<file file_name="src/log.h"/>
<file file_name="src/binary.h"/>
<folder Name="protocol" file_name="">
<file file_name="src/protocol/protocol.c"/>
<folder Name="commands" file_name="">
<file file_name="src/protocol/commands/protocol_cmd_led.c"/>
<file file_name="src/protocol/commands/protocol_cmd_sysinfo.c"/>
</folder>
<file file_name="src/protocol/prot_cmdtable.h"/>
</folder>
<file file_name="src/fixed.h"/>
</folder>
<folder Name="System Files">
<file file_name="$(StudioDir)/source/thumb_crt0.s"/>
<file file_name="$(TargetsDir)/LPC1000/LPC11Uxx_Startup.s"/>
<file file_name="$(TargetsDir)/LPC1000/LPC11Uxx_Target.js">
<configuration Name="Common" file_type="Reset Script"/>
</file>
</folder>
<folder Name="CMSIS Files" file_name="">
<file file_name="cmsis/LPC11Uxx.h"/>
<file file_name="cmsis/math_helper.c"/>
<file file_name="cmsis/system_LPC11Uxx.c"/>
<file file_name="cmsis/system_LPC11Uxx.h"/>
<file file_name="cmsis/RTX_hook.c"/>
</folder>
</project>
<configuration Name="THUMB Flash Debug" inherited_configurations="THUMB;Flash;Debug"/>
<configuration Name="THUMB" Platform="ARM" arm_instruction_set="THUMB" arm_library_instruction_set="THUMB" c_preprocessor_definitions="__THUMB" hidden="Yes"/>
<configuration Name="Flash" c_preprocessor_definitions="__FLASH_BUILD" hidden="Yes"/>
<configuration Name="Debug" c_preprocessor_definitions="DEBUG" gcc_debugging_level="Level 2" gcc_optimization_level="None" hidden="Yes"/>
<configuration Name="THUMB Flash Release" inherited_configurations="THUMB;Flash;Release"/>
<configuration Name="Release" c_preprocessor_definitions="NDEBUG;STARTUP_FROM_RESET" gcc_debugging_level="Level 1" gcc_optimization_level="Optimize For Size" hidden="Yes"/>
<configuration Name="Common" arm_gcc_target="arm-unknown-eabi" arm_linker_allow_multiple_definition="Yes" c_preprocessor_definitions="CFG_BRD_LPCXPRESSO_LPC1347;ARM_MATH_CM0" c_user_include_directories="$(ProjectDir)/cmsis/;$(ProjectDir)/src/;$(ProjectDir)/src/cli/" linker_printf_fp_enabled="Yes"/>
</solution>

+ 26
- 0
License.txt View File

@@ -0,0 +1,26 @@
Software License Agreement (BSD License)

Unless otherwise noted, Copyright (c) 2013 Kevin Townsend (microBuilder.eu)
All rights reserved.

Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the copyright holders nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+ 438
- 0
Makefile View File

@@ -0,0 +1,438 @@
##########################################################################
# User configuration and firmware specific object files
##########################################################################

FILENAME=firmware

# See projectconfig.h for a list of valid BOARD options!
BOARD=CFG_BRD_REFORM2

# Set TARGET to 'lpc11u' or 'lpc13u' depending on the target MCU
TARGET = lpc11u
ifeq (lpc11u,$(TARGET))
CORE = cortex-m0
LDSCRIPT = cmsis/lpc11u24.ld
# LDSCRIPT = cmsis/lpc11u37.ld
else
CORE = cortex-m3
LDSCRIPT = cmsis/lpc1347.ld
endif

# Set OPTIMIZATION to '0', '1', '2', '3' or 's'
OPTIMIZATION = s

##########################################################################
# Output directories
##########################################################################

BIN_PATH = bin
OBJ_PATH = bin/obj

##########################################################################
# Source Files
##########################################################################

VPATH = cmsis
ifeq (lpc11u,$(TARGET))
OBJS = $(OBJ_PATH)/startup_lpc11u_gnumake.o
OBJS += $(OBJ_PATH)/system_LPC11Uxx.o
else
OBJS = $(OBJ_PATH)/startup_lpc13u_gnumake.o
OBJS += $(OBJ_PATH)/system_LPC13Uxx.o
endif
OBJS += $(OBJ_PATH)/math_helper.o
OBJS += $(OBJ_PATH)/RTX_hook.o

VPATH += src
OBJS += $(OBJ_PATH)/printf-retarget.o

VPATH += src/boards/lpcnfc
OBJS += $(OBJ_PATH)/board_lpcnfc.o

VPATH += src/boards/reform2
OBJS += $(OBJ_PATH)/board_reform2.o

VPATH += src/boards/rf1ghzusb
OBJS += $(OBJ_PATH)/board_rf1ghzusb.o

VPATH += src/boards/rf1ghznode
OBJS += $(OBJ_PATH)/board_rf1ghznode.o

VPATH += src/cli
OBJS += $(OBJ_PATH)/cli.o
OBJS += $(OBJ_PATH)/commands.o

VPATH += src/cli/commands
OBJS += $(OBJ_PATH)/cmd_chibi_addr.o
OBJS += $(OBJ_PATH)/cmd_chibi_tx.o
OBJS += $(OBJ_PATH)/cmd_dbg_memrd.o
OBJS += $(OBJ_PATH)/cmd_eeprom_read.o
OBJS += $(OBJ_PATH)/cmd_eeprom_write.o
OBJS += $(OBJ_PATH)/cmd_i2c_read.o
OBJS += $(OBJ_PATH)/cmd_i2c_scan.o
OBJS += $(OBJ_PATH)/cmd_i2c_write.o
OBJS += $(OBJ_PATH)/cmd_nfc_mfc_ndef.o
OBJS += $(OBJ_PATH)/cmd_nfc_mifareclassic_memdump.o
OBJS += $(OBJ_PATH)/cmd_nfc_mifareclassic_valueblock.o
OBJS += $(OBJ_PATH)/cmd_nfc_mifareultralight_memdump.o
OBJS += $(OBJ_PATH)/cmd_rtc_read.o
OBJS += $(OBJ_PATH)/cmd_rtc_write.o
OBJS += $(OBJ_PATH)/cmd_sd_dir.o
OBJS += $(OBJ_PATH)/cmd_sysinfo.o
OBJS += $(OBJ_PATH)/cmd_wifi.o

VPATH += src/core/adc
OBJS += $(OBJ_PATH)/adc.o

VPATH += src/core/delay
OBJS += $(OBJ_PATH)/delay.o

VPATH += src/core/debug
OBJS += $(OBJ_PATH)/debug.o

VPATH += src/core/eeprom
OBJS += $(OBJ_PATH)/eeprom.o

VPATH += src/core/fifo
OBJS += $(OBJ_PATH)/fifo.o

VPATH += src/core/gpio
OBJS += $(OBJ_PATH)/gpio.o

VPATH += src/core/i2c
OBJS += $(OBJ_PATH)/i2c.o

VPATH += src/core/iap
OBJS += $(OBJ_PATH)/iap.o

VPATH += src/core/libc
OBJS += $(OBJ_PATH)/stdio.o
OBJS += $(OBJ_PATH)/string.o

VPATH += src/core/pmu
OBJS += $(OBJ_PATH)/pmu.o

VPATH += src/core/ssp0
OBJS += $(OBJ_PATH)/ssp0.o

VPATH += src/core/ssp1
OBJS += $(OBJ_PATH)/ssp1.o

VPATH += src/core/timer16
OBJS += $(OBJ_PATH)/timer16.o

VPATH += src/core/timer32
OBJS += $(OBJ_PATH)/timer32.o

VPATH += src/core/uart
OBJS += $(OBJ_PATH)/uart.o
OBJS += $(OBJ_PATH)/uart_buf.o

VPATH += src/core/usb
OBJS += $(OBJ_PATH)/descriptors.o
OBJS += $(OBJ_PATH)/usb_cdc.o
OBJS += $(OBJ_PATH)/usb_custom_class.o
OBJS += $(OBJ_PATH)/usb_hid.o
OBJS += $(OBJ_PATH)/usb_msc.o
OBJS += $(OBJ_PATH)/usbd.o

VPATH += src/drivers
OBJS += $(OBJ_PATH)/timespan.o

VPATH += src/drivers/displays
OBJS += $(OBJ_PATH)/smallfonts.o

VPATH += src/drivers/displays/bitmap/ssd1306
OBJS += $(OBJ_PATH)/ssd1306_i2c.o

VPATH += src/drivers/displays/graphic
OBJS += $(OBJ_PATH)/aafonts.o
OBJS += $(OBJ_PATH)/colors.o
OBJS += $(OBJ_PATH)/drawing.o
OBJS += $(OBJ_PATH)/fonts.o
OBJS += $(OBJ_PATH)/theme.o

VPATH += src/drivers/displays/graphic/aafonts/aa2
OBJS += $(OBJ_PATH)/DejaVuSansCondensed14_AA2.o
OBJS += $(OBJ_PATH)/DejaVuSansCondensedBold14_AA2.o
OBJS += $(OBJ_PATH)/DejaVuSansMono10_AA2.o
OBJS += $(OBJ_PATH)/DejaVuSansMono13_AA2.o
OBJS += $(OBJ_PATH)/DejaVuSansMono14_AA2.o
OBJS += $(OBJ_PATH)/FontCalibri18_AA2.o
OBJS += $(OBJ_PATH)/FontCalibriBold18_AA2.o
OBJS += $(OBJ_PATH)/FontCalibriItalic18_AA2.o
OBJS += $(OBJ_PATH)/FontFranklinGothicBold99_Numbers_AA2.o

VPATH += src/drivers/displays/graphic/aafonts/aa4
OBJS += $(OBJ_PATH)/FontCalibri18_AA4.o

VPATH += src/drivers/displays/graphic/fonts
OBJS += $(OBJ_PATH)/dejavusans9.o
OBJS += $(OBJ_PATH)/dejavusansbold9.o
OBJS += $(OBJ_PATH)/dejavusanscondensed9.o
OBJS += $(OBJ_PATH)/dejavusansmono8.o
OBJS += $(OBJ_PATH)/dejavusansmonobold8.o
OBJS += $(OBJ_PATH)/veramono9.o
OBJS += $(OBJ_PATH)/veramono11.o
OBJS += $(OBJ_PATH)/veramonobold9.o
OBJS += $(OBJ_PATH)/veramonobold11.o
OBJS += $(OBJ_PATH)/verdana9.o
OBJS += $(OBJ_PATH)/verdana14.o
OBJS += $(OBJ_PATH)/verdanabold14.o

VPATH += src/drivers/displays/graphic/hw
OBJS += $(OBJ_PATH)/hx8340b.o
# OBJS += $(OBJ_PATH)/hx8347g.o

VPATH += src/drivers/displays/segment/ht16k33
OBJS += $(OBJ_PATH)/ht16k33.o

VPATH += src/drivers/filters/iir
OBJS += $(OBJ_PATH)/iir_f.o
OBJS += $(OBJ_PATH)/iir_i.o
OBJS += $(OBJ_PATH)/iir_u16.o

VPATH += src/drivers/filters/ma
OBJS += $(OBJ_PATH)/sma_f.o
OBJS += $(OBJ_PATH)/sma_i.o
OBJS += $(OBJ_PATH)/sma_u16.o
OBJS += $(OBJ_PATH)/wma_f.o
OBJS += $(OBJ_PATH)/wma_i.o
OBJS += $(OBJ_PATH)/wma_u16.o

VPATH += src/drivers/motor/stepper
OBJS += $(OBJ_PATH)/stepper.o

VPATH += src/drivers/pwm/pca9685
OBJS += $(OBJ_PATH)/pca9685.o

VPATH += src/drivers/rf/802.15.4/chibi
OBJS += $(OBJ_PATH)/chb.o
OBJS += $(OBJ_PATH)/chb_buf.o
OBJS += $(OBJ_PATH)/chb_drvr.o
OBJS += $(OBJ_PATH)/chb_eeprom.o
OBJS += $(OBJ_PATH)/chb_spi.o
OBJS += $(OBJ_PATH)/messages.o

VPATH += src/drivers/rf/nfc/pn532
OBJS += $(OBJ_PATH)/pn532.o
OBJS += $(OBJ_PATH)/pn532_bus_i2c.o
OBJS += $(OBJ_PATH)/pn532_bus_uart.o

VPATH += src/drivers/rf/nfc/pn532/helpers
OBJS += $(OBJ_PATH)/pn532_config.o
OBJS += $(OBJ_PATH)/pn532_gpio.o
OBJS += $(OBJ_PATH)/pn532_mifare_classic.o
OBJS += $(OBJ_PATH)/pn532_mifare_ultralight.o
OBJS += $(OBJ_PATH)/pn532_ndef.o
OBJS += $(OBJ_PATH)/pn532_ndef_cards.o

VPATH += src/drivers/rf/wifi/cc3000
OBJS += $(OBJ_PATH)/spi.o
OBJS += $(OBJ_PATH)/wifi.o

VPATH += src/drivers/rf/wifi/cc3000/hostdriver
OBJS += $(OBJ_PATH)/cc3000_common.o
OBJS += $(OBJ_PATH)/evnt_handler.o
OBJS += $(OBJ_PATH)/hci.o
OBJS += $(OBJ_PATH)/netapp.o
OBJS += $(OBJ_PATH)/nvmem.o
OBJS += $(OBJ_PATH)/security.o
OBJS += $(OBJ_PATH)/socket.o
OBJS += $(OBJ_PATH)/wlan.o

VPATH += src/drivers/rf/nfc/pn532/mem_allocator
OBJS += $(OBJ_PATH)/bget.o
OBJS += $(OBJ_PATH)/pn532_mem.o

VPATH += src/drivers/rtc
OBJS += $(OBJ_PATH)/rtc.o

VPATH += src/drivers/rtc/pcf2129
OBJS += $(OBJ_PATH)/pcf2129.o

VPATH += src/drivers/sensors
OBJS += $(OBJ_PATH)/sensors.o
OBJS += $(OBJ_PATH)/sensorpoll.o

VPATH += src/drivers/sensors/accelerometers
OBJS += $(OBJ_PATH)/accelerometers.o
OBJS += $(OBJ_PATH)/adxl345.o
OBJS += $(OBJ_PATH)/lis3dh.o
OBJS += $(OBJ_PATH)/lsm303accel.o

VPATH += src/drivers/sensors/gyroscopes
OBJS += $(OBJ_PATH)/l3gd20.o

VPATH += src/drivers/sensors/light
OBJS += $(OBJ_PATH)/tsl2561.o

VPATH += src/drivers/sensors/magnetometers
OBJS += $(OBJ_PATH)/magnetometers.o
OBJS += $(OBJ_PATH)/lsm303mag.o

VPATH += src/drivers/sensors/pressure
OBJS += $(OBJ_PATH)/pressure.o
OBJS += $(OBJ_PATH)/bmp085.o
OBJS += $(OBJ_PATH)/mpl115a2.o

VPATH += src/drivers/sensors/temperature
OBJS += $(OBJ_PATH)/lm75b.o

VPATH += src/drivers/storage
OBJS += $(OBJ_PATH)/logger.o

VPATH += src/drivers/storage/fatfs
OBJS += $(OBJ_PATH)/ff.o
OBJS += $(OBJ_PATH)/mmc.o

VPATH += src/localisation
OBJS += $(OBJ_PATH)/localisation.o

VPATH += src/protocol
OBJS += $(OBJ_PATH)/protocol.o

VPATH += src/protocol/commands
OBJS += $(OBJ_PATH)/protocol_cmd_led.o
OBJS += $(OBJ_PATH)/protocol_cmd_sysinfo.o

##########################################################################
# Include paths
##########################################################################

ROOT_PATH = src
INCLUDE_PATHS = -I$(ROOT_PATH) -Icmsis

##########################################################################
# GNU GCC compiler prefix
##########################################################################

# Use the default toolchain (based on the PATH variable, etc.)
CROSS_COMPILE ?= arm-none-eabi-

# OR ... use a toolchain at a specific location
# CROSS_COMPILE = C:/code_red/RedSuiteNXP_5.0.12_1048/redsuite/tools/bin/arm-none-eabi-
# CROSS_COMPILE = C:/arm/gnu4.7.2012.q4/bin/arm-none-eabi-

AS = $(CROSS_COMPILE)gcc
CC = $(CROSS_COMPILE)gcc
LD = $(CROSS_COMPILE)gcc
SIZE = $(CROSS_COMPILE)size
OBJCOPY = $(CROSS_COMPILE)objcopy
OBJDUMP = $(CROSS_COMPILE)objdump
OUTFILE = $(BIN_PATH)/$(FILENAME)
LPCRC ?= tools/lpcrc/lpcrc
REMOVE = rm -f
MOUNT_POINT ?= /media/CRP DISABLD

##########################################################################
# Compiler settings, parameters and flags
##########################################################################

# Compiler Options
GCFLAGS = -c
GCFLAGS += -std=gnu99
GCFLAGS += -g
GCFLAGS += -O$(OPTIMIZATION)
GCFLAGS += $(INCLUDE_PATHS)
GCFLAGS += -Wall
GCFLAGS += -mthumb
GCFLAGS += -ffunction-sections
GCFLAGS += -fdata-sections
GCFLAGS += -fmessage-length=0
GCFLAGS += -fno-builtin
GCFLAGS += -mcpu=$(CORE)
GCFLAGS += -DTARGET=$(TARGET)
GCFLAGS += -D$(BOARD)
# CMSIS DSP Flags
ifeq (lpc11u,$(TARGET))
GCFLAGS += -DARM_MATH_CM0
else
GCFLAGS += -DARM_MATH_CM3
endif
# For use with the GCC ARM Embedded toolchain
# GCFLAGS += --specs=nano.specs
# For use with the LPCXpresso toolchain
# GCFLAGS += -D__REDLIB__ -D__CODE_RED

# Assembler Options
ASFLAGS = -c
ASFLAGS += -g
ASFLAGS += -O$(OPTIMIZATION)
ASFLAGS += $(INCLUDE_PATHS)
ASFLAGS += -Wall
ASFLAGS += -mthumb
ASFLAGS += -ffunction-sections
ASFLAGS += -fdata-sections
ASFLAGS += -fmessage-length=0
ASFLAGS += -mcpu=$(CORE)
ASFLAGS += -D__ASSEMBLY__
ASFLAGS += -x assembler-with-cpp

# Linker Options
LDFLAGS = -nostartfiles
LDFLAGS += -mcpu=$(CORE)
LDFLAGS += -mthumb
LDFLAGS += -O$(OPTIMIZATION)
LDFLAGS += -Wl,--gc-sections
LDFLAGS += -T $(LDSCRIPT)
LDFLAGS += -Xlinker -Map=bin/firmware.map
# CMSIS Libraries
LDFLAGS += -L./cmsis/libs
ifeq (lpc11u,$(TARGET))
LDLIBS = -larm_cortexM0l_math -lRTX_CM0
else
LDLIBS = -larm_cortexM3l_math -lRTX_CM3
endif
# External Libraries
LDLIBS += -lm
# The following libraries are required with the LPCXpresso toolchain
# LDLIBS += -lcr_c -lcr_eabihelpers

OCFLAGS = --strip-unneeded

##########################################################################
# Rules
##########################################################################

all: firmware

$(OBJ_PATH)/%.o : %.c
@mkdir -p $(dir $@)
-@echo "COMPILING $(@F)"
@$(CC) $(GCFLAGS) -o $@ $<

$(OBJ_PATH)/%.o : %.s
@mkdir -p $(dir $@)
-@echo "ASSEMBLING $(@F)"
@$(AS) $(ASFLAGS) -o $@ $<

firmware: $(OBJS) $(SYS_OBJS)
@mkdir -p $(BIN_PATH)
-@echo ""
-@echo "LINKING $(OUTFILE).elf ($(CORE) -O$(OPTIMIZATION) $(BOARD))"
@$(LD) $(LDFLAGS) -o $(OUTFILE).elf $(LDLIBS) $(OBJS) $(LDLIBS)
-@echo ""
@$(SIZE) $(OUTFILE).elf
-@echo ""
-@echo "Generating $(OUTFILE).hex"
@$(OBJCOPY) $(OCFLAGS) -O ihex $(OUTFILE).elf $(OUTFILE).hex
-@echo "Generating $(OUTFILE).bin"
@$(OBJCOPY) $(OCFLAGS) -O binary $(OUTFILE).elf $(OUTFILE).bin
-@echo ""
@$(LPCRC) $(OUTFILE).bin

flash: firmware
-@echo ""
-@echo "Flashing device ..."
-@[ -e "$(MOUNT_POINT)/firmware.bin" ] && dd if=bin/firmware.bin of="$(MOUNT_POINT)/firmware.bin" conv=nocreat,notrunc && umount "$(MOUNT_POINT)" || echo "Error, no device?!"

lpcrc:
-@echo ""
-@echo "Building lpcrc (checksum tool) ..."
@make -C tools/lpcrc
clean:
@$(REMOVE) $(OBJS) $(OUTFILE).elf $(OUTFILE).bin $(OUTFILE).hex

#########################################################################

+ 68
- 0
README.md View File

@@ -0,0 +1,68 @@
# LPC11U/LPC13U Code Base #

This code base is an attempt at providing a reasonably well-organized, open-source starting point for projects based on the LPC11Uxx and LPC13Uxx family of MCUs.

## Key Features ##

It includes the following key features, which can be easily enabled or disabled via a single board-specific config file:

- [USB CDC, HID and MSC support](https://github.com/microbuilder/LPC11U_LPC13U_Codebase/tree/master/src/core/usb), including HID Keyboard and HID Mouse emulation, with any combination of devices possible up to the number of end points available on the MCU
- Easy to extend [command-line interface](https://github.com/microbuilder/LPC11U_LPC13U_Codebase/tree/master/src/cli) (CLI) with USB CDC and UART support
- [Sensor abstraction layer](https://github.com/microbuilder/LPC11U_LPC13U_Codebase/tree/master/src/drivers/sensors) where all sensors return a common descriptor and data type using standardized SI units
- Basic [localisation support](https://github.com/microbuilder/LPC11U_LPC13U_Codebase/tree/master/src/localisation), allowing multiple languages to be used in the same application
- Graphics sub-system including support for multiple font types (bitmap or anti-aliased), basic drawing functions, and a simple HW abstraction mechanism
- FAT16/32 file system support for SD cards including the option to use long names (via FatFS)
- Numerous wireless stacks, including NFC (based on the PN532) and 802.15.4 (based on the AT86RF212).
- A basic [unit testing framework](https://github.com/microbuilder/LPC11U_LPC13U_Codebase/tree/master/tests_host) suitable for embedded systems (Unity)

## Supported MCUs ##
This code base is designed to work transparently with the following MCUs, allowing you to select the MCU with the right price/performance/size ratio for your project without having to rewrite any underlying code:

- **LPC1347** - ARM Cortex M3, 72MHz, 64KB Flash, 8+2+2KB SRAM, 4KB EEPROM
- **LPC11U37** - ARM Cortex M0, 50MHz, 128KB Flash, 8+2KB SRAM, 4KB EEPROM
- **LPC11U24** - ARM Cortex M0, 50MHa, 32KB Flash, 8+2KB SRAM, 4KB EEPROM

## Multiple Board Support ##

In an attempt to make the code base relevant in a variety of situations, there is a basic [board abstraction layer](https://github.com/microbuilder/LPC11U_LPC13U_Codebase/tree/master/src/boards), and all config settings are board-specific.

The target board in indicated in the shared **projectconfig.h** file, which in turn references the board-specific config and initialization code in the **'boards/'** subfolder.

## Supported IDEs/Toolchains ##

The code base contains a few dependencies on GCC extensions (notably in the localisation system), and has not been tested with any non-GCC toolchain.

At the moment the following IDEs are supported by the code base, and this list may be extended in the future:

**GCC/Makefile ('Makefile')**

The codebase includes startup code, linker scripts and a makefile to build this codebase with the cross-platform, open-source GNU/GCC toolset. This gives you the most control over how your project is built, and allows you to build your project on any platform with support for GCC and make (*NIX, Mac OSX, Windows, etc.). [(more)](doc/toolchain_make.md)

**LPCXpresso / Code Red IDE (.cproject/.project)**

LPCXpresso is a free of charge Eclipse-based IDE based around GCC. It's based on Code Red's commercial Red Suite IDE, but is provided free of charge by NXP Semiconductors with a debug limit up to 128Kb (you can, however, compile projects larger than this), which is within the limits of all of the chips supported by this code base.

Inexpensive LPCXpresso development boards are available with integrated SWD debuggers that can be seperated from the MCU part of the board and used to debug any supported MCU or device. [(more)](doc/toolchain_lpcxpresso.md)

**Crossworks for ARM (CW\_*.hzp)**

Project files are also provided for Rowley Associate's popular Crossworks for ARM IDE, which is GCC based, includes an optimised standard C library, and supports a large variety of HW debuggers (including the popular J-Link from Segger). [(more)](doc/toolchain_crossworks.md)

## Current Development Status ##

This code base is still in active development, and there are almost certainly a number of improvements that can be made to it, bugs that will need to be worked out, and pieces of code that could be better organized or rewritten entirely.

The current localisation system is quite unsatisfactory, for example, but the decision was made to keep in in the code base in the hopes that other people will propose improvements to it, as well as to other parts of this code base.

Until an initial public release is made (version 1.0), the code base should be considered unstable and some reorganisation will almost certainly continue to take place in different parts of the code.

The current code has a good overall structure, but there are still many parts that can be streamlined or reorganized (for example, reworking the UART buffer to use src/core/fifo.c instead of the older buffer from a previous code base).

## How Can I Help? ##

Quite a bit of time, effort and money has gone into producing this open source code base in the sole hope that it will make things easier for other people to get started with this well-rounded MCU family. If you find the code base useful as is, the best thanks you can give is to contribute something useful back to it, and improve the current code base so that other people can learn from your efforts as well.

## License ##

Where possible, all code is provided under a BSD style license, but each file is individually licensed and you should ensure that you fully understand the license terms and limitations of any files you use in your project.

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# LPC11U/LPC13U Code Base - Revision History #

Major changes in the LPC11U/LPC13U code base by code base version number.

## 0.9.1 [12 July 2013] ##

- Fixed .bss placement in USB SRAM in linker scripts! (oops!)

## 0.9.0 [12 July 2013] ##

- delay.c interrupt priority changed to be one higher than the lowest level so that other interrupts can potentially be configured to use delay by setting them to the lowest level
- sensorpoll.c added to poll sensor data at fixed intervals using 16-bit timer 1 (though care needs to be taken using this!)
- Disabled both generic interrupt handlers in timer16.c since they are both potentially used elsewhere
- magnetometer.c, accelerometer.c and pressure.c generic helper functions added in the sensor abstraction layer
- Added debug.c to help with debugging in the field
- Merged CMSIS-RTOS (RTX) updates from RTX branch ... basic test works on M3 and M0, but further testing needed
- Added basic USB custom class support (fast bulk transfers)
- USB HID now shares the same API as USB custom class calls to make it easier to switch
- Various improvements to the simple binary protocol
- Removed unity tests (/tests) to make room for ceedling native tests (/tests_host)
- Removed Keil project files since it's too much of a headache to maintain
- Reorganised errors.h (certains numeric values were changed)
- Updated board config files for USB/Protocol additions
- Added CFG\_ENABLE\_TIMER32 to disable TIMER32 (interrupt handlers use a lot of flash/SRAM)
- CC3000 support added (experimental, see note below!)
- Added sysinfo command to the simple binary protocol
- Fixed a bug in iap.c (truncated serial numbers)
- **BREAKING CHANGE**: Moved all /src/drivers/rf code to technology-specific folders ('nfc', 'wifi', etc.)
- **KNOWN ISSUE**: There's a truckload of issues with the CC3000 API from TI! It can't currently be built using the makefile, and is CW only at the moment. Be sure to disable CFG_CC3000 in our board config file until these issues can all be resolved!
- **KNOWN ISSUE**: CFG\_USB\_CUSTOM\_CLASS can not be combined with any HID classes, and you must use one or the other. This seems to be an issue with the ROM drivers and memory managed, and placing the USB memory buffer in the main 8KB block (instead of the 2KB USB SRAM block) avoids this issue, but since the buffer needs to be aligned on a 2048 byte boundary this leads to a huge waste of memory. Investigation ongoing, but for now avoid combining CFG\_USB\_CUSTOM\_CLASS and any HID class(es).

## 0.8.6 [14 June 2013] ##

- Added core/timer16
- Added core/delay (abstraction layer to use systick or timer16[0] for 1ms delays)
- Removed core/systick and changed all systick* calls to delay* (for RTOS compatability)
- Added flow control to uart.c
- Added faster simple moving average filter (drivers/filters/ma/sma\_*), removed old versions
- Added weighted moving average filter (/drivers/filters/ma/wma\_*)
- Renamed CMSIS startup_* files to be clearer
- Added drivers/storage/logger.c to log data to an SD card or a local file (local file is Crossworks only)
- Updated adc.c for differences between LPC11U and LPC1347
- Moved low power and 10-bit ADC mode settings to board config file
- Added custom M3 RTX library (canned M3 RTX lib from ARM generated hardfault)
- Added %f (float), %e (scientific notation) and %E (engineering notation) printf support in stdio.c (Pito)
- **KNOWN ISSUE**: CDC still sometimes fails with heavy traffic ... active debugging in progress
- **KNOWN ISSUE**: RTX tested under LPCXpresso, but not working under CW since startup code needs to be modified so license issues need to be resolved with Rowley

## 0.8.5 [21 May 2013] ##

- Updated CMSIS to v3.20
- Renamed Crossworks project files to CW_*
- Renamed Keil project files to Keil_*
- Added stepper support to board config files
- Changed the clock setup in core/adc
- Added basic TCS34725 driver
- First attempt at a simple binary protocol (CFG_PROTOCOL, /src/protocol)
- Added CFG\_BRD\_SIMULATOR as a board option (mostly for unit tests)
- Fixed negative value bug in timespanCreate
- Renamed /src/drivers/statistics to /src/drivers/filters
- Added some basic Python scripts to test the IIR filter
- Updated LPCXpresso project files to use /cmsis (no more external dependencies)
- Added int32_t iir filter and matching python scripts
- Changed usb HID generic callbacks to be more general
- Replaced 'USB\_HID\_GenericReportOut\_t' and 'USB\_HID\_GenericReportIn\_t' signatures with '(uint8\_t report[] and uint32\_t length)'
- Affected functions are 'usb\_hid\_generic\_recv\_isr', 'usb\_hid\_generic\_report\_request\_isr', and 'usb\_hid\_generic\_send'
- Added CMSIS DSP library to the makefile, LPCXpresso and Crossworks project files
- Added RTX library for CMSIS-RTOS (currently untested)
- Removed all use of GPIOSetBitValue and GPIOSetDir (wasteful fluff)
- Added simple moving average filter and python tester
- Improved fifo_t to support any object size (previously uint8_t only)
- Added ceedling support (experimental)

## 0.8.1 [23 April 2013] ##

- 'main' entry point moved to board-specific files ('src/boards/*')
- Removed main.c from src root
- LPCXpresso/Red Suite project files now default to the LPC1347
- Moved messages.c to drivers/rf/chibi
- Removed some unnecessary files
- Added binary.h to simplify binary access across toolchains (removed '0b' references)
- Added 'get_fattime' to board files (get timestamp for FAT32 and SD cards)
- Moved board selection from projectconfig.h to the make file and IDE project properties

## 0.8.0 [2 April 2013] ##

- First public release

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/****************************************************************************************************//**
* @file LPC11Uxx.h
*
*
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
* default LPC11Uxx Device Series
*
* @version V0.1
* @date 21. March 2011
*
* @note Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45
*
* from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1,
* created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40
*
*******************************************************************************************************/



/** @addtogroup NXP
* @{
*/

/** @addtogroup LPC11Uxx
* @{
*/

#ifndef __LPC11UXX_H__
#define __LPC11UXX_H__

#ifdef __cplusplus
extern "C" {
#endif


#if defined ( __CC_ARM )
#pragma anon_unions
#endif

/* Interrupt Number Definition */

typedef enum {
// ------------------------- Cortex-M0 Processor Exceptions Numbers -----------------------------
Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
SysTick_IRQn = -1, /*!< 15 System Tick Timer */
// --------------------------- LPC11Uxx Specific Interrupt Numbers ------------------------------
FLEX_INT0_IRQn = 0, /*!< All I/O pins can be routed to below 8 interrupts. */
FLEX_INT1_IRQn = 1,
FLEX_INT2_IRQn = 2,
FLEX_INT3_IRQn = 3,
FLEX_INT4_IRQn = 4,
FLEX_INT5_IRQn = 5,
FLEX_INT6_IRQn = 6,
FLEX_INT7_IRQn = 7,
GINT0_IRQn = 8, /*!< Grouped Interrupt 0 */
GINT1_IRQn = 9, /*!< Grouped Interrupt 1 */
Reserved0_IRQn = 10, /*!< Reserved Interrupt */
Reserved1_IRQn = 11,
Reserved2_IRQn = 12,
Reserved3_IRQn = 13,
SSP1_IRQn = 14, /*!< SSP1 Interrupt */
I2C_IRQn = 15, /*!< I2C Interrupt */
TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
SSP0_IRQn = 20, /*!< SSP0 Interrupt */
UART_IRQn = 21, /*!< UART Interrupt */
USB_IRQn = 22, /*!< USB IRQ Interrupt */
USB_FIQn = 23, /*!< USB FIQ Interrupt */
ADC_IRQn = 24, /*!< A/D Converter Interrupt */
WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */
FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */
Reserved4_IRQn = 28, /*!< Reserved Interrupt */
Reserved5_IRQn = 29, /*!< Reserved Interrupt */
USBWakeup_IRQn = 30, /*!< USB wakeup Interrupt */
Reserved6_IRQn = 31, /*!< Reserved Interrupt */
} IRQn_Type;


/** @addtogroup Configuration_of_CMSIS
* @{
*/

/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */

#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/** @} */ /* End of group Configuration_of_CMSIS */

#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
#include "system_LPC11Uxx.h" /*!< LPC11Uxx System */

/** @addtogroup Device_Peripheral_Registers
* @{
*/


// ------------------------------------------------------------------------------------------------
// ----- I2C -----
// ------------------------------------------------------------------------------------------------


/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (I2C)
*/

typedef struct { /*!< (@ 0x40000000) I2C Structure */
__IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register */
__I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register */
__IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. */
__IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0 */
__IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */
__IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */
__IO uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register*/
__IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register*/
__IO uint32_t ADR1; /*!< (@ 0x40000020) I2C Slave Address Register 1*/
__IO uint32_t ADR2; /*!< (@ 0x40000024) I2C Slave Address Register 2*/
__IO uint32_t ADR3; /*!< (@ 0x40000028) I2C Slave Address Register 3*/
__I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register */
union{
__IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register */
struct{
__IO uint32_t MASK0;
__IO uint32_t MASK1;
__IO uint32_t MASK2;
__IO uint32_t MASK3;
};
};
} LPC_I2C_Type;


// ------------------------------------------------------------------------------------------------
// ----- WWDT -----
// ------------------------------------------------------------------------------------------------


/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3 (WWDT)
*/

typedef struct { /*!< (@ 0x40004000) WWDT Structure */
__IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register*/
__IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register */
__IO uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register */
__I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register */
__IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
__IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
__IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
} LPC_WWDT_Type;


// ------------------------------------------------------------------------------------------------
// ----- USART -----
// ------------------------------------------------------------------------------------------------


/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART)
*/

typedef struct { /*!< (@ 0x40008000) USART Structure */
union {
__IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
__O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
__I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
};
union {
__IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
__IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
};
union {
__O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
__I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
};
__IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
__IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
__I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
__I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
__IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
__IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
__IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
__IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
__IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
__IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
__I uint32_t RESERVED0[3];
__IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
__I uint32_t RESERVED1;
__IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
__IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
__IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
__IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
__IO uint32_t SYNCCTRL;
} LPC_USART_Type;


// ------------------------------------------------------------------------------------------------
// ----- Timer -----
// ------------------------------------------------------------------------------------------------


/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3
*/

typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
__IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register */
__IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register */
__IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter */
__IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register */
__IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter */
__IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register */
union {
__IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register */
struct{
__IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
__IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
__IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
__IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
};
};
__IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register */
union{
__I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register */
struct{
__I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
__I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
__I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
__I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
};
};
__IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register */
__I uint32_t RESERVED0[12];
__IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register */
__IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register */
} LPC_CTxxBx_Type;



// ------------------------------------------------------------------------------------------------
// ----- ADC -----
// ------------------------------------------------------------------------------------------------


/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC)
*/

typedef struct { /*!< (@ 0x4001C000) ADC Structure */
__IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register */
__IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register */
__I uint32_t RESERVED0[1];
__IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */
union{
__I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
struct{
__IO uint32_t DR0; /*!< (@ 0x40020010) A/D Channel Data Register 0*/
__IO uint32_t DR1; /*!< (@ 0x40020014) A/D Channel Data Register 1*/
__IO uint32_t DR2; /*!< (@ 0x40020018) A/D Channel Data Register 2*/
__IO uint32_t DR3; /*!< (@ 0x4002001C) A/D Channel Data Register 3*/
__IO uint32_t DR4; /*!< (@ 0x40020020) A/D Channel Data Register 4*/
__IO uint32_t DR5; /*!< (@ 0x40020024) A/D Channel Data Register 5*/
__IO uint32_t DR6; /*!< (@ 0x40020028) A/D Channel Data Register 6*/
__IO uint32_t DR7; /*!< (@ 0x4002002C) A/D Channel Data Register 7*/
};
};
__I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. */
} LPC_ADC_Type;


// ------------------------------------------------------------------------------------------------
// ----- PMU -----
// ------------------------------------------------------------------------------------------------


/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3 (PMU)
*/

typedef struct { /*!< (@ 0x40038000) PMU Structure */
__IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
union{
__IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
struct{
__IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
__IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
__IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
__IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
};
};
} LPC_PMU_Type;


// ------------------------------------------------------------------------------------------------
// ----- FLASHCTRL -----
// ------------------------------------------------------------------------------------------------


/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 (FLASHCTRL)
*/

typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
__I uint32_t RESERVED0[4];
__IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
__I uint32_t RESERVED1[3];
__IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
__IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
__I uint32_t RESERVED2[1];
__I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
__I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
__I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
__I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
__I uint32_t RESERVED3[1001];
__I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
__I uint32_t RESERVED4[1];
__IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
} LPC_FLASHCTRL_Type;


// ------------------------------------------------------------------------------------------------
// ----- SSP0/1 -----
// ------------------------------------------------------------------------------------------------


/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0)
*/

typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
__IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
__IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
__IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
__I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
__IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
__IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
__I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
__I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
__IO uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
} LPC_SSPx_Type;



// ------------------------------------------------------------------------------------------------
// ----- IOCONFIG -----
// ------------------------------------------------------------------------------------------------


/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
*/

typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
__IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
__IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
__IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
__IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
__IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
__IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
__IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
__IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
__IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */
__IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */
__IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
__IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
__IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
__IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
__IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
__IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
__IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
__IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
__IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
__IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
__IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
__IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
__IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
__IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
__IO uint32_t PIO1_0; /*!< Offset: 0x060 */
__IO uint32_t PIO1_1;
__IO uint32_t PIO1_2;
__IO uint32_t PIO1_3;
__IO uint32_t PIO1_4; /*!< Offset: 0x070 */
__IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
__IO uint32_t PIO1_6;
__IO uint32_t PIO1_7;
__IO uint32_t PIO1_8; /*!< Offset: 0x080 */
__IO uint32_t PIO1_9;
__IO uint32_t PIO1_10;
__IO uint32_t PIO1_11;
__IO uint32_t PIO1_12; /*!< Offset: 0x090 */
__IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */
__IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */
__IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
__IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
__IO uint32_t PIO1_17;
__IO uint32_t PIO1_18;
__IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
__IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
__IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
__IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
__IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
__IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
__IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
__IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
__IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
__IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
__IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
__IO uint32_t PIO1_30;
__IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
} LPC_IOCON_Type;


// ------------------------------------------------------------------------------------------------
// ----- SYSCON -----
// ------------------------------------------------------------------------------------------------


/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3 (SYSCON)
*/

typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
__IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
__IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
__IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
__I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
__IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
__I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
__I uint32_t RESERVED0[2];
__IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
__IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
__I uint32_t RESERVED1[2];
__IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
__I uint32_t RESERVED2[3];
__IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
__IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */
__IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
__IO uint32_t USBPLLCLKUEN; /*!< (@ 0x4004804C) USB PLL clock source update enable */
__I uint32_t RESERVED3[8];
__IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
__IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */
__IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
__I uint32_t RESERVED4[1];
__IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
__I uint32_t RESERVED5[4];
__IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
__IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
__IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
__I uint32_t RESERVED6[8];
__IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
__IO uint32_t USBCLKUEN; /*!< (@ 0x400480C4) USB clock source update enable */
__IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
__I uint32_t RESERVED7[5];
__IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
__IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */
__IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
__I uint32_t RESERVED8[5];
__I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
__I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
__I uint32_t RESERVED9[18];
__IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
__IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
__I uint32_t RESERVED10[6];
__IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay */
__IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
__IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
__IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
__I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
__I uint32_t RESERVED11[25];
__IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
__I uint32_t RESERVED12[3];
__IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
__I uint32_t RESERVED13[6];
__IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
__IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
__IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
__I uint32_t RESERVED14[110];
__I uint32_t DEVICE_ID; /*!< (@ 0x400483F4) Device ID */
} LPC_SYSCON_Type;


// ------------------------------------------------------------------------------------------------
// ----- GPIO_PIN_INT -----
// ------------------------------------------------------------------------------------------------


/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PIN_INT)
*/

typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
__IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
__IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
__IO uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
__IO uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
__IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
__IO uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
__IO uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
__IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
__IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
__IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
} LPC_GPIO_PIN_INT_Type;


// ------------------------------------------------------------------------------------------------
// ----- GPIO_GROUP_INT0/1 -----
// ------------------------------------------------------------------------------------------------


/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_GROUP_INT0)
*/

typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
__IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
__I uint32_t RESERVED0[7];
__IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
__I uint32_t RESERVED1[6];
__IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
} LPC_GPIO_GROUP_INTx_Type;



// ------------------------------------------------------------------------------------------------
// ----- USB -----
// ------------------------------------------------------------------------------------------------


/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (USB)
*/

typedef struct { /*!< (@ 0x40080000) USB Structure */
__IO uint32_t DEVCMDSTAT; /*!< (@ 0x40080000) USB Device Command/Status register */
__IO uint32_t INFO; /*!< (@ 0x40080004) USB Info register */
__IO uint32_t EPLISTSTART; /*!< (@ 0x40080008) USB EP Command/Status List start address */
__IO uint32_t DATABUFSTART; /*!< (@ 0x4008000C) USB Data buffer start address */
__IO uint32_t LPM; /*!< (@ 0x40080010) Link Power Management register */
__IO uint32_t EPSKIP; /*!< (@ 0x40080014) USB Endpoint skip */
__IO uint32_t EPINUSE; /*!< (@ 0x40080018) USB Endpoint Buffer in use */
__IO uint32_t EPBUFCFG; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */
__IO uint32_t INTSTAT; /*!< (@ 0x40080020) USB interrupt status register */
__IO uint32_t INTEN; /*!< (@ 0x40080024) USB interrupt enable register */
__IO uint32_t INTSETSTAT; /*!< (@ 0x40080028) USB set interrupt status register */
__IO uint32_t INTROUTING; /*!< (@ 0x4008002C) USB interrupt routing register */
__I uint32_t RESERVED0[1];
__I uint32_t EPTOGGLE; /*!< (@ 0x40080034) USB Endpoint toggle register */
} LPC_USB_Type;


// ------------------------------------------------------------------------------------------------
// ----- GPIO_PORT -----
// ------------------------------------------------------------------------------------------------


/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
*/

typedef struct {
union {
struct {
__IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
__IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
};
__IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
};
__I uint32_t RESERVED0[1008];
union {
struct {
__IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
__IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
};
__IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
};
uint32_t RESERVED1[960];
__IO uint32_t DIR[2]; /* 0x2000 */
uint32_t RESERVED2[30];
__IO uint32_t MASK[2]; /* 0x2080 */
uint32_t RESERVED3[30];
__IO uint32_t PIN[2]; /* 0x2100 */
uint32_t RESERVED4[30];
__IO uint32_t MPIN[2]; /* 0x2180 */
uint32_t RESERVED5[30];
__IO uint32_t SET[2]; /* 0x2200 */
uint32_t RESERVED6[30];
__O uint32_t CLR[2]; /* 0x2280 */
uint32_t RESERVED7[30];
__O uint32_t NOT[2]; /* 0x2300 */
} LPC_GPIO_Type;


#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif


// ------------------------------------------------------------------------------------------------
// ----- Peripheral memory map -----
// ------------------------------------------------------------------------------------------------

#define LPC_I2C_BASE (0x40000000)
#define LPC_WWDT_BASE (0x40004000)
#define LPC_USART_BASE (0x40008000)
#define LPC_CT16B0_BASE (0x4000C000)
#define LPC_CT16B1_BASE (0x40010000)
#define LPC_CT32B0_BASE (0x40014000)
#define LPC_CT32B1_BASE (0x40018000)
#define LPC_ADC_BASE (0x4001C000)
#define LPC_PMU_BASE (0x40038000)
#define LPC_FLASHCTRL_BASE (0x4003C000)
#define LPC_SSP0_BASE (0x40040000)
#define LPC_SSP1_BASE (0x40058000)
#define LPC_IOCON_BASE (0x40044000)
#define LPC_SYSCON_BASE (0x40048000)
#define LPC_GPIO_PIN_INT_BASE (0x4004C000)
#define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
#define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
#define LPC_USB_BASE (0x40080000)
#define LPC_GPIO_BASE (0x50000000)


// ------------------------------------------------------------------------------------------------
// ----- Peripheral declaration -----
// ------------------------------------------------------------------------------------------------

#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
#define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
#define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
#define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
#define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
#define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
#define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
#define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE)
#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE)
#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)


/** @} */ /* End of group Device_Peripheral_Registers */
/** @} */ /* End of group (null) */
/** @} */ /* End of group LPC11Uxx */

#ifdef __cplusplus
}
#endif


#endif // __LPC11UXX_H__

+ 760
- 0
cmsis/LPC13Uxx.h View File

@@ -0,0 +1,760 @@

/****************************************************************************************************//**
* @file LPC13Uxx.h
*
*
*
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
* default LPC13Uxx Device Series
*
* @version V0.1
* @date 18. Jan 2012
*
* @note Generated with SFDGen V2.6 Build 4f on Tuesday, 17.01.2012 13:39:52
*
* from CMSIS SVD File 'LPC13uxx_svd_v0.1.xml' Version 0.1,
* created on Thurs, 01.19.2012 15:13:15, last modified on Thurs, 01.19.2012 15:53:09
*
*******************************************************************************************************/

/** @addtogroup NXP
* @{
*/

/** @addtogroup LPC13Uxx
* @{
*/

#ifndef __LPC13UXX_H__
#define __LPC13UXX_H__

#ifdef __cplusplus
extern "C" {
#endif


#if defined ( __CC_ARM )
#pragma anon_unions
#endif

/* Interrupt Number Definition */

typedef enum {
// ------------------------- Cortex-M3 Processor Exceptions Numbers -----------------------------
Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
SysTick_IRQn = -1, /*!< 15 System Tick Timer */
// ---------------------------- LPC13Uxx Specific Interrupt Numbers --------------------------------
PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
GINT0_IRQn = 8, /*!< 8 GINT0 */
GINT1_IRQn = 9, /*!< 9 GINT1 */
Reserved0_IRQn = 10, /*!< 10 Reserved Interrupt */
Reserved1_IRQn = 11, /*!< 11 Reserved Interrupt */
RIT_IRQn = 12, /*!< 12 Repetitive Interrupt Timer */
Reserved2_IRQn = 13, /*!< 13 Reserved Interrupt */
SSP1_IRQn = 14, /*!< 14 SSP1 */
I2C_IRQn = 15, /*!< 15 I2C */
CT16B0_IRQn = 16, /*!< 16 CT16B0 */
CT16B1_IRQn = 17, /*!< 17 CT16B1 */
CT32B0_IRQn = 18, /*!< 18 CT32B0 */
CT32B1_IRQn = 19, /*!< 19 CT32B1 */
SSP0_IRQn = 20, /*!< 20 SSP0 */
USART_IRQn = 21, /*!< 21 USART */
USB_IRQ_IRQn = 22, /*!< 22 USB_IRQ */
USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
ADC_IRQn = 24, /*!< 24 ADC */
WDT_IRQn = 25, /*!< 25 WDT */
BOD_IRQn = 26, /*!< 26 BOD */
FMC_IRQn = 27, /*!< 27 FMC */
Reserved3_IRQn = 28, /*!< 28 Reserved Interrupt */
Reserved4_IRQn = 29, /*!< 29 Reserved Interrupt */
USBWAKEUP_IRQn = 30, /*!< 30 USBWAKEUP */
Reserved5_IRQn = 31, /*!< 31 Reserved Interrupt */
} IRQn_Type;


/** @addtogroup Configuration_of_CMSIS
* @{
*/

/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M3 Processor and Core Peripherals */

#define __CM3_REV 0x0000 /*!< Cortex-M3 Core Revision */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/** @} */ /* End of group Configuration_of_CMSIS */

#include <core_cm3.h> /*!< Cortex-M3 processor and core peripherals */
#include "system_LPC13Uxx.h" /*!< LPC13Uxx System */

/** @addtogroup Device_Peripheral_Registers
* @{
*/


// ------------------------------------------------------------------------------------------------
// ----- I2C -----
// ------------------------------------------------------------------------------------------------



typedef struct { /*!< (@ 0x40000000) I2C Structure */
__IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
__I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
__IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
__IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
__IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
__IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
__O uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
__IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register. */
union{
__IO uint32_t ADR[3]; /*!< (@ 0x40000020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
struct{
__IO uint32_t ADR1;
__IO uint32_t ADR2;
__IO uint32_t ADR3;
};
};
__I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
union{
__IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). */
struct{
__IO uint32_t MASK0;
__IO uint32_t MASK1;
__IO uint32_t MASK2;
__IO uint32_t MASK3;
};
};
} LPC_I2C_Type;


// ------------------------------------------------------------------------------------------------
// ----- WWDT -----
// ------------------------------------------------------------------------------------------------


typedef struct { /*!< (@ 0x40004000) WWDT Structure */
__IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
__IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register. This 24-bit register determines the time-out value. */
__O uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
__I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
__IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
__IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
__IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
} LPC_WWDT_Type;


// ------------------------------------------------------------------------------------------------
// ----- USART -----
// ------------------------------------------------------------------------------------------------


typedef struct { /*!< (@ 0x40008000) USART Structure */
union {
__IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
__O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
__I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
};
union {
__IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
__IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
};
union {
__O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
__I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
};
__IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
__IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
__I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
__I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
__IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
__IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
__IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
__IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
__IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
__IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
__I uint32_t RESERVED0[3];
__IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
__I uint32_t RESERVED1;
__IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
__IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
__IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
__IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
__IO uint32_t SYNCCTRL; /*!< (@ 0x40008058) Synchronous mode control register. */
} LPC_USART_Type;


// ------------------------------------------------------------------------------------------------
// ----- CT16B0 -----
// ------------------------------------------------------------------------------------------------

typedef struct { /*!< (@ 0x4000C000) CT16B0 Structure */
__IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
__IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
__IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
__IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
__IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
__IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
union {
__IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
struct{
__IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
__IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
__IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
__IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
};
};
__IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
union{
__I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
struct{
__I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
__I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
__I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
__I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
};
};
__IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
__I uint32_t RESERVED0[12];
__IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
__IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
} LPC_CT16B0_Type;


// ------------------------------------------------------------------------------------------------
// ----- CT16B1 -----
// ------------------------------------------------------------------------------------------------

typedef struct { /*!< (@ 0x40010000) CT16B1 Structure */
__IO uint32_t IR; /*!< (@ 0x40010000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
__IO uint32_t TCR; /*!< (@ 0x40010004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
__IO uint32_t TC; /*!< (@ 0x40010008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
__IO uint32_t PR; /*!< (@ 0x4001000C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
__IO uint32_t PC; /*!< (@ 0x40010010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
__IO uint32_t MCR; /*!< (@ 0x40010014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
union {
__IO uint32_t MR[4]; /*!< (@ 0x40010018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
struct{
__IO uint32_t MR0; /*!< (@ 0x40010018) Match Register. MR0 */
__IO uint32_t MR1; /*!< (@ 0x4001001C) Match Register. MR1 */
__IO uint32_t MR2; /*!< (@ 0x40010020) Match Register. MR2 */
__IO uint32_t MR3; /*!< (@ 0x40010024) Match Register. MR3 */
};
};
__IO uint32_t CCR; /*!< (@ 0x40010028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
union{
__I uint32_t CR[4]; /*!< (@ 0x4001002C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
struct{
__I uint32_t CR0; /*!< (@ 0x4001002C) Capture Register. CR 0 */
__I uint32_t CR1; /*!< (@ 0x40010030) Capture Register. CR 1 */
__I uint32_t CR2; /*!< (@ 0x40010034) Capture Register. CR 2 */
__I uint32_t CR3; /*!< (@ 0x40010038) Capture Register. CR 3 */
};
};
__IO uint32_t EMR; /*!< (@ 0x4001003C) External Match Register. The EMR controls the match function and the external match pins */
__I uint32_t RESERVED0[12];
__IO uint32_t CTCR; /*!< (@ 0x40010070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
__IO uint32_t PWMC; /*!< (@ 0x40010074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
} LPC_CT16B1_Type;


// ------------------------------------------------------------------------------------------------
// ----- CT32B0 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
__IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
__IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
__IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
__IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
__IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
__IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
union {
__IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
struct{
__IO uint32_t MR0; /*!< (@ 0x40014018) Match Register. MR0 */
__IO uint32_t MR1; /*!< (@ 0x4001401C) Match Register. MR1 */
__IO uint32_t MR2; /*!< (@ 0x40014020) Match Register. MR2 */
__IO uint32_t MR3; /*!< (@ 0x40014024) Match Register. MR3 */
};
};
__IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
union{
__I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
struct{
__I uint32_t CR0; /*!< (@ 0x4001402C) Capture Register. CR 0 */
__I uint32_t CR1; /*!< (@ 0x40014030) Capture Register. CR 1 */
__I uint32_t CR2; /*!< (@ 0x40014034) Capture Register. CR 2 */
__I uint32_t CR3; /*!< (@ 0x40014038) Capture Register. CR 3 */
};
};
__IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
__I uint32_t RESERVED0[12];
__IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
__IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
} LPC_CT32B0_Type;