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  1. /****************************************************************************************************//**
  2. * @file LPC11Uxx.h
  3. *
  4. *
  5. * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
  6. * default LPC11Uxx Device Series
  7. *
  8. * @version V0.1
  9. * @date 21. March 2011
  10. *
  11. * @note Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45
  12. *
  13. * from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1,
  14. * created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40
  15. *
  16. *******************************************************************************************************/
  17. /** @addtogroup NXP
  18. * @{
  19. */
  20. /** @addtogroup LPC11Uxx
  21. * @{
  22. */
  23. #ifndef __LPC11UXX_H__
  24. #define __LPC11UXX_H__
  25. #ifdef __cplusplus
  26. extern "C" {
  27. #endif
  28. #if defined ( __CC_ARM )
  29. #pragma anon_unions
  30. #endif
  31. /* Interrupt Number Definition */
  32. typedef enum {
  33. // ------------------------- Cortex-M0 Processor Exceptions Numbers -----------------------------
  34. Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
  35. NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
  36. HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
  37. SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
  38. DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
  39. PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
  40. SysTick_IRQn = -1, /*!< 15 System Tick Timer */
  41. // --------------------------- LPC11Uxx Specific Interrupt Numbers ------------------------------
  42. FLEX_INT0_IRQn = 0, /*!< All I/O pins can be routed to below 8 interrupts. */
  43. FLEX_INT1_IRQn = 1,
  44. FLEX_INT2_IRQn = 2,
  45. FLEX_INT3_IRQn = 3,
  46. FLEX_INT4_IRQn = 4,
  47. FLEX_INT5_IRQn = 5,
  48. FLEX_INT6_IRQn = 6,
  49. FLEX_INT7_IRQn = 7,
  50. GINT0_IRQn = 8, /*!< Grouped Interrupt 0 */
  51. GINT1_IRQn = 9, /*!< Grouped Interrupt 1 */
  52. Reserved0_IRQn = 10, /*!< Reserved Interrupt */
  53. Reserved1_IRQn = 11,
  54. Reserved2_IRQn = 12,
  55. Reserved3_IRQn = 13,
  56. SSP1_IRQn = 14, /*!< SSP1 Interrupt */
  57. I2C_IRQn = 15, /*!< I2C Interrupt */
  58. TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
  59. TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
  60. TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
  61. TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
  62. SSP0_IRQn = 20, /*!< SSP0 Interrupt */
  63. UART_IRQn = 21, /*!< UART Interrupt */
  64. USB_IRQn = 22, /*!< USB IRQ Interrupt */
  65. USB_FIQn = 23, /*!< USB FIQ Interrupt */
  66. ADC_IRQn = 24, /*!< A/D Converter Interrupt */
  67. WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
  68. BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */
  69. FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */
  70. Reserved4_IRQn = 28, /*!< Reserved Interrupt */
  71. Reserved5_IRQn = 29, /*!< Reserved Interrupt */
  72. USBWakeup_IRQn = 30, /*!< USB wakeup Interrupt */
  73. Reserved6_IRQn = 31, /*!< Reserved Interrupt */
  74. } IRQn_Type;
  75. /** @addtogroup Configuration_of_CMSIS
  76. * @{
  77. */
  78. /* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */
  79. #define __MPU_PRESENT 0 /*!< MPU present or not */
  80. #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
  81. #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
  82. /** @} */ /* End of group Configuration_of_CMSIS */
  83. #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
  84. #include "system_LPC11Uxx.h" /*!< LPC11Uxx System */
  85. /** @addtogroup Device_Peripheral_Registers
  86. * @{
  87. */
  88. // ------------------------------------------------------------------------------------------------
  89. // ----- I2C -----
  90. // ------------------------------------------------------------------------------------------------
  91. /**
  92. * @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (I2C)
  93. */
  94. typedef struct { /*!< (@ 0x40000000) I2C Structure */
  95. __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register */
  96. __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register */
  97. __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. */
  98. __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0 */
  99. __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */
  100. __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */
  101. __IO uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register*/
  102. __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register*/
  103. __IO uint32_t ADR1; /*!< (@ 0x40000020) I2C Slave Address Register 1*/
  104. __IO uint32_t ADR2; /*!< (@ 0x40000024) I2C Slave Address Register 2*/
  105. __IO uint32_t ADR3; /*!< (@ 0x40000028) I2C Slave Address Register 3*/
  106. __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register */
  107. union{
  108. __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register */
  109. struct{
  110. __IO uint32_t MASK0;
  111. __IO uint32_t MASK1;
  112. __IO uint32_t MASK2;
  113. __IO uint32_t MASK3;
  114. };
  115. };
  116. } LPC_I2C_Type;
  117. // ------------------------------------------------------------------------------------------------
  118. // ----- WWDT -----
  119. // ------------------------------------------------------------------------------------------------
  120. /**
  121. * @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3 (WWDT)
  122. */
  123. typedef struct { /*!< (@ 0x40004000) WWDT Structure */
  124. __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register*/
  125. __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register */
  126. __IO uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register */
  127. __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register */
  128. __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
  129. __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
  130. __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
  131. } LPC_WWDT_Type;
  132. // ------------------------------------------------------------------------------------------------
  133. // ----- USART -----
  134. // ------------------------------------------------------------------------------------------------
  135. /**
  136. * @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART)
  137. */
  138. typedef struct { /*!< (@ 0x40008000) USART Structure */
  139. union {
  140. __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
  141. __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
  142. __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
  143. };
  144. union {
  145. __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
  146. __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
  147. };
  148. union {
  149. __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
  150. __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
  151. };
  152. __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
  153. __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
  154. __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
  155. __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
  156. __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
  157. __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
  158. __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
  159. __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
  160. __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
  161. __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
  162. __I uint32_t RESERVED0[3];
  163. __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
  164. __I uint32_t RESERVED1;
  165. __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
  166. __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
  167. __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
  168. __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
  169. __IO uint32_t SYNCCTRL;
  170. } LPC_USART_Type;
  171. // ------------------------------------------------------------------------------------------------
  172. // ----- Timer -----
  173. // ------------------------------------------------------------------------------------------------
  174. /**
  175. * @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3
  176. */
  177. typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
  178. __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register */
  179. __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register */
  180. __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter */
  181. __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register */
  182. __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter */
  183. __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register */
  184. union {
  185. __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register */
  186. struct{
  187. __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
  188. __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
  189. __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
  190. __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
  191. };
  192. };
  193. __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register */
  194. union{
  195. __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register */
  196. struct{
  197. __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
  198. __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
  199. __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
  200. __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
  201. };
  202. };
  203. __IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register */
  204. __I uint32_t RESERVED0[12];
  205. __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register */
  206. __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register */
  207. } LPC_CTxxBx_Type;
  208. // ------------------------------------------------------------------------------------------------
  209. // ----- ADC -----
  210. // ------------------------------------------------------------------------------------------------
  211. /**
  212. * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC)
  213. */
  214. typedef struct { /*!< (@ 0x4001C000) ADC Structure */
  215. __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register */
  216. __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register */
  217. __I uint32_t RESERVED0[1];
  218. __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */
  219. union{
  220. __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
  221. struct{
  222. __IO uint32_t DR0; /*!< (@ 0x40020010) A/D Channel Data Register 0*/
  223. __IO uint32_t DR1; /*!< (@ 0x40020014) A/D Channel Data Register 1*/
  224. __IO uint32_t DR2; /*!< (@ 0x40020018) A/D Channel Data Register 2*/
  225. __IO uint32_t DR3; /*!< (@ 0x4002001C) A/D Channel Data Register 3*/
  226. __IO uint32_t DR4; /*!< (@ 0x40020020) A/D Channel Data Register 4*/
  227. __IO uint32_t DR5; /*!< (@ 0x40020024) A/D Channel Data Register 5*/
  228. __IO uint32_t DR6; /*!< (@ 0x40020028) A/D Channel Data Register 6*/
  229. __IO uint32_t DR7; /*!< (@ 0x4002002C) A/D Channel Data Register 7*/
  230. };
  231. };
  232. __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. */
  233. } LPC_ADC_Type;
  234. // ------------------------------------------------------------------------------------------------
  235. // ----- PMU -----
  236. // ------------------------------------------------------------------------------------------------
  237. /**
  238. * @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3 (PMU)
  239. */
  240. typedef struct { /*!< (@ 0x40038000) PMU Structure */
  241. __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
  242. union{
  243. __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
  244. struct{
  245. __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
  246. __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
  247. __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
  248. __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
  249. };
  250. };
  251. } LPC_PMU_Type;
  252. // ------------------------------------------------------------------------------------------------
  253. // ----- FLASHCTRL -----
  254. // ------------------------------------------------------------------------------------------------
  255. /**
  256. * @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 (FLASHCTRL)
  257. */
  258. typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
  259. __I uint32_t RESERVED0[4];
  260. __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
  261. __I uint32_t RESERVED1[3];
  262. __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
  263. __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
  264. __I uint32_t RESERVED2[1];
  265. __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
  266. __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
  267. __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
  268. __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
  269. __I uint32_t RESERVED3[1001];
  270. __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
  271. __I uint32_t RESERVED4[1];
  272. __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
  273. } LPC_FLASHCTRL_Type;
  274. // ------------------------------------------------------------------------------------------------
  275. // ----- SSP0/1 -----
  276. // ------------------------------------------------------------------------------------------------
  277. /**
  278. * @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0)
  279. */
  280. typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
  281. __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
  282. __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
  283. __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
  284. __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
  285. __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
  286. __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
  287. __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
  288. __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
  289. __IO uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
  290. } LPC_SSPx_Type;
  291. // ------------------------------------------------------------------------------------------------
  292. // ----- IOCONFIG -----
  293. // ------------------------------------------------------------------------------------------------
  294. /**
  295. * @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
  296. */
  297. typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
  298. __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
  299. __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
  300. __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
  301. __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
  302. __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
  303. __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
  304. __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
  305. __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
  306. __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */
  307. __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */
  308. __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
  309. __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
  310. __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
  311. __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
  312. __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
  313. __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
  314. __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
  315. __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
  316. __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
  317. __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
  318. __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
  319. __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
  320. __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
  321. __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
  322. __IO uint32_t PIO1_0; /*!< Offset: 0x060 */
  323. __IO uint32_t PIO1_1;
  324. __IO uint32_t PIO1_2;
  325. __IO uint32_t PIO1_3;
  326. __IO uint32_t PIO1_4; /*!< Offset: 0x070 */
  327. __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
  328. __IO uint32_t PIO1_6;
  329. __IO uint32_t PIO1_7;
  330. __IO uint32_t PIO1_8; /*!< Offset: 0x080 */
  331. __IO uint32_t PIO1_9;
  332. __IO uint32_t PIO1_10;
  333. __IO uint32_t PIO1_11;
  334. __IO uint32_t PIO1_12; /*!< Offset: 0x090 */
  335. __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */
  336. __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */
  337. __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
  338. __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
  339. __IO uint32_t PIO1_17;
  340. __IO uint32_t PIO1_18;
  341. __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
  342. __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
  343. __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
  344. __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
  345. __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
  346. __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
  347. __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
  348. __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
  349. __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
  350. __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
  351. __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
  352. __IO uint32_t PIO1_30;
  353. __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
  354. } LPC_IOCON_Type;
  355. // ------------------------------------------------------------------------------------------------
  356. // ----- SYSCON -----
  357. // ------------------------------------------------------------------------------------------------
  358. /**
  359. * @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3 (SYSCON)
  360. */
  361. typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
  362. __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
  363. __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
  364. __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
  365. __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
  366. __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
  367. __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
  368. __I uint32_t RESERVED0[2];
  369. __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
  370. __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
  371. __I uint32_t RESERVED1[2];
  372. __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
  373. __I uint32_t RESERVED2[3];
  374. __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
  375. __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */
  376. __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
  377. __IO uint32_t USBPLLCLKUEN; /*!< (@ 0x4004804C) USB PLL clock source update enable */
  378. __I uint32_t RESERVED3[8];
  379. __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
  380. __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */
  381. __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
  382. __I uint32_t RESERVED4[1];
  383. __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
  384. __I uint32_t RESERVED5[4];
  385. __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
  386. __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
  387. __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
  388. __I uint32_t RESERVED6[8];
  389. __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
  390. __IO uint32_t USBCLKUEN; /*!< (@ 0x400480C4) USB clock source update enable */
  391. __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
  392. __I uint32_t RESERVED7[5];
  393. __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
  394. __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */
  395. __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
  396. __I uint32_t RESERVED8[5];
  397. __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
  398. __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
  399. __I uint32_t RESERVED9[18];
  400. __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
  401. __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
  402. __I uint32_t RESERVED10[6];
  403. __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay */
  404. __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
  405. __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
  406. __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
  407. __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
  408. __I uint32_t RESERVED11[25];
  409. __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
  410. __I uint32_t RESERVED12[3];
  411. __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
  412. __I uint32_t RESERVED13[6];
  413. __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
  414. __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
  415. __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
  416. __I uint32_t RESERVED14[110];
  417. __I uint32_t DEVICE_ID; /*!< (@ 0x400483F4) Device ID */
  418. } LPC_SYSCON_Type;
  419. // ------------------------------------------------------------------------------------------------
  420. // ----- GPIO_PIN_INT -----
  421. // ------------------------------------------------------------------------------------------------
  422. /**
  423. * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PIN_INT)
  424. */
  425. typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
  426. __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
  427. __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
  428. __IO uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
  429. __IO uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
  430. __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
  431. __IO uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
  432. __IO uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
  433. __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
  434. __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
  435. __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
  436. } LPC_GPIO_PIN_INT_Type;
  437. // ------------------------------------------------------------------------------------------------
  438. // ----- GPIO_GROUP_INT0/1 -----
  439. // ------------------------------------------------------------------------------------------------
  440. /**
  441. * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_GROUP_INT0)
  442. */
  443. typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
  444. __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
  445. __I uint32_t RESERVED0[7];
  446. __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
  447. __I uint32_t RESERVED1[6];
  448. __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
  449. } LPC_GPIO_GROUP_INTx_Type;
  450. // ------------------------------------------------------------------------------------------------
  451. // ----- USB -----
  452. // ------------------------------------------------------------------------------------------------
  453. /**
  454. * @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (USB)
  455. */
  456. typedef struct { /*!< (@ 0x40080000) USB Structure */
  457. __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40080000) USB Device Command/Status register */
  458. __IO uint32_t INFO; /*!< (@ 0x40080004) USB Info register */
  459. __IO uint32_t EPLISTSTART; /*!< (@ 0x40080008) USB EP Command/Status List start address */
  460. __IO uint32_t DATABUFSTART; /*!< (@ 0x4008000C) USB Data buffer start address */
  461. __IO uint32_t LPM; /*!< (@ 0x40080010) Link Power Management register */
  462. __IO uint32_t EPSKIP; /*!< (@ 0x40080014) USB Endpoint skip */
  463. __IO uint32_t EPINUSE; /*!< (@ 0x40080018) USB Endpoint Buffer in use */
  464. __IO uint32_t EPBUFCFG; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */
  465. __IO uint32_t INTSTAT; /*!< (@ 0x40080020) USB interrupt status register */
  466. __IO uint32_t INTEN; /*!< (@ 0x40080024) USB interrupt enable register */
  467. __IO uint32_t INTSETSTAT; /*!< (@ 0x40080028) USB set interrupt status register */
  468. __IO uint32_t INTROUTING; /*!< (@ 0x4008002C) USB interrupt routing register */
  469. __I uint32_t RESERVED0[1];
  470. __I uint32_t EPTOGGLE; /*!< (@ 0x40080034) USB Endpoint toggle register */
  471. } LPC_USB_Type;
  472. // ------------------------------------------------------------------------------------------------
  473. // ----- GPIO_PORT -----
  474. // ------------------------------------------------------------------------------------------------
  475. /**
  476. * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
  477. */
  478. typedef struct {
  479. union {
  480. struct {
  481. __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
  482. __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
  483. };
  484. __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
  485. };
  486. __I uint32_t RESERVED0[1008];
  487. union {
  488. struct {
  489. __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
  490. __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
  491. };
  492. __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
  493. };
  494. uint32_t RESERVED1[960];
  495. __IO uint32_t DIR[2]; /* 0x2000 */
  496. uint32_t RESERVED2[30];
  497. __IO uint32_t MASK[2]; /* 0x2080 */
  498. uint32_t RESERVED3[30];
  499. __IO uint32_t PIN[2]; /* 0x2100 */
  500. uint32_t RESERVED4[30];
  501. __IO uint32_t MPIN[2]; /* 0x2180 */
  502. uint32_t RESERVED5[30];
  503. __IO uint32_t SET[2]; /* 0x2200 */
  504. uint32_t RESERVED6[30];
  505. __O uint32_t CLR[2]; /* 0x2280 */
  506. uint32_t RESERVED7[30];
  507. __O uint32_t NOT[2]; /* 0x2300 */
  508. } LPC_GPIO_Type;
  509. #if defined ( __CC_ARM )
  510. #pragma no_anon_unions
  511. #endif
  512. // ------------------------------------------------------------------------------------------------
  513. // ----- Peripheral memory map -----
  514. // ------------------------------------------------------------------------------------------------
  515. #define LPC_I2C_BASE (0x40000000)
  516. #define LPC_WWDT_BASE (0x40004000)
  517. #define LPC_USART_BASE (0x40008000)
  518. #define LPC_CT16B0_BASE (0x4000C000)
  519. #define LPC_CT16B1_BASE (0x40010000)
  520. #define LPC_CT32B0_BASE (0x40014000)
  521. #define LPC_CT32B1_BASE (0x40018000)
  522. #define LPC_ADC_BASE (0x4001C000)
  523. #define LPC_PMU_BASE (0x40038000)
  524. #define LPC_FLASHCTRL_BASE (0x4003C000)
  525. #define LPC_SSP0_BASE (0x40040000)
  526. #define LPC_SSP1_BASE (0x40058000)
  527. #define LPC_IOCON_BASE (0x40044000)
  528. #define LPC_SYSCON_BASE (0x40048000)
  529. #define LPC_GPIO_PIN_INT_BASE (0x4004C000)
  530. #define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
  531. #define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
  532. #define LPC_USB_BASE (0x40080000)
  533. #define LPC_GPIO_BASE (0x50000000)
  534. // ------------------------------------------------------------------------------------------------
  535. // ----- Peripheral declaration -----
  536. // ------------------------------------------------------------------------------------------------
  537. #define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
  538. #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
  539. #define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
  540. #define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
  541. #define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
  542. #define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
  543. #define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
  544. #define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
  545. #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
  546. #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
  547. #define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
  548. #define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
  549. #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
  550. #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
  551. #define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
  552. #define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE)
  553. #define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE)
  554. #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
  555. #define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
  556. /** @} */ /* End of group Device_Peripheral_Registers */
  557. /** @} */ /* End of group (null) */
  558. /** @} */ /* End of group LPC11Uxx */
  559. #ifdef __cplusplus
  560. }
  561. #endif
  562. #endif // __LPC11UXX_H__