MNT Reform: Open Source Portable Computer https://mntre.com/reform
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  1. #include <util/twi.h>
  2. #include <avr/io.h>
  3. #include <stdlib.h>
  4. #include <avr/interrupt.h>
  5. #include <util/twi.h>
  6. #include <stdbool.h>
  7. #include "i2c.h"
  8. // Limits the amount of we wait for any one i2c transaction.
  9. // Since were running SCL line 100kHz (=> 10μs/bit), and each transactions is
  10. // 9 bits, a single transaction will take around 90μs to complete.
  11. //
  12. // (F_CPU/SCL_CLOCK) => # of μC cycles to transfer a bit
  13. // poll loop takes at least 8 clock cycles to execute
  14. #define I2C_LOOP_TIMEOUT (9+1)*(F_CPU/SCL_CLOCK)/8
  15. #define BUFFER_POS_INC() (slave_buffer_pos = (slave_buffer_pos+1)%SLAVE_BUFFER_SIZE)
  16. volatile uint8_t i2c_slave_buffer[SLAVE_BUFFER_SIZE];
  17. static volatile uint8_t slave_buffer_pos;
  18. static volatile bool slave_has_register_set = false;
  19. // Wait for an i2c operation to finish
  20. inline static
  21. void i2c_delay(void) {
  22. uint16_t lim = 0;
  23. while(!(TWCR & (1<<TWINT)) && lim < I2C_LOOP_TIMEOUT)
  24. lim++;
  25. // easier way, but will wait slightly longer
  26. // _delay_us(100);
  27. }
  28. // Setup twi to run at 100kHz or 400kHz (see ./i2c.h SCL_CLOCK)
  29. void i2c_master_init(void) {
  30. // no prescaler
  31. TWSR = 0;
  32. // Set TWI clock frequency to SCL_CLOCK. Need TWBR>10.
  33. // Check datasheets for more info.
  34. TWBR = ((F_CPU/SCL_CLOCK)-16)/2;
  35. }
  36. // Start a transaction with the given i2c slave address. The direction of the
  37. // transfer is set with I2C_READ and I2C_WRITE.
  38. // returns: 0 => success
  39. // 1 => error
  40. uint8_t i2c_master_start(uint8_t address) {
  41. TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWSTA);
  42. i2c_delay();
  43. // check that we started successfully
  44. if ( (TW_STATUS != TW_START) && (TW_STATUS != TW_REP_START))
  45. return 1;
  46. TWDR = address;
  47. TWCR = (1<<TWINT) | (1<<TWEN);
  48. i2c_delay();
  49. if ( (TW_STATUS != TW_MT_SLA_ACK) && (TW_STATUS != TW_MR_SLA_ACK) )
  50. return 1; // slave did not acknowledge
  51. else
  52. return 0; // success
  53. }
  54. // Finish the i2c transaction.
  55. void i2c_master_stop(void) {
  56. TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWSTO);
  57. uint16_t lim = 0;
  58. while(!(TWCR & (1<<TWSTO)) && lim < I2C_LOOP_TIMEOUT)
  59. lim++;
  60. }
  61. // Write one byte to the i2c slave.
  62. // returns 0 => slave ACK
  63. // 1 => slave NACK
  64. uint8_t i2c_master_write(uint8_t data) {
  65. TWDR = data;
  66. TWCR = (1<<TWINT) | (1<<TWEN);
  67. i2c_delay();
  68. // check if the slave acknowledged us
  69. return (TW_STATUS == TW_MT_DATA_ACK) ? 0 : 1;
  70. }
  71. // Read one byte from the i2c slave. If ack=1 the slave is acknowledged,
  72. // if ack=0 the acknowledge bit is not set.
  73. // returns: byte read from i2c device
  74. uint8_t i2c_master_read(int ack) {
  75. TWCR = (1<<TWINT) | (1<<TWEN) | (ack<<TWEA);
  76. i2c_delay();
  77. return TWDR;
  78. }
  79. void i2c_reset_state(void) {
  80. TWCR = 0;
  81. }
  82. void i2c_slave_init(uint8_t address) {
  83. TWAR = address << 0; // slave i2c address
  84. // TWEN - twi enable
  85. // TWEA - enable address acknowledgement
  86. // TWINT - twi interrupt flag
  87. // TWIE - enable the twi interrupt
  88. TWCR = (1<<TWIE) | (1<<TWEA) | (1<<TWINT) | (1<<TWEN);
  89. }
  90. ISR(TWI_vect);
  91. ISR(TWI_vect) {
  92. uint8_t ack = 1;
  93. switch(TW_STATUS) {
  94. case TW_SR_SLA_ACK:
  95. // this device has been addressed as a slave receiver
  96. slave_has_register_set = false;
  97. break;
  98. case TW_SR_DATA_ACK:
  99. // this device has received data as a slave receiver
  100. // The first byte that we receive in this transaction sets the location
  101. // of the read/write location of the slaves memory that it exposes over
  102. // i2c. After that, bytes will be written at slave_buffer_pos, incrementing
  103. // slave_buffer_pos after each write.
  104. if(!slave_has_register_set) {
  105. slave_buffer_pos = TWDR;
  106. // don't acknowledge the master if this memory loctaion is out of bounds
  107. if ( slave_buffer_pos >= SLAVE_BUFFER_SIZE ) {
  108. ack = 0;
  109. slave_buffer_pos = 0;
  110. }
  111. slave_has_register_set = true;
  112. } else {
  113. i2c_slave_buffer[slave_buffer_pos] = TWDR;
  114. BUFFER_POS_INC();
  115. }
  116. break;
  117. case TW_ST_SLA_ACK:
  118. case TW_ST_DATA_ACK:
  119. // master has addressed this device as a slave transmitter and is
  120. // requesting data.
  121. TWDR = i2c_slave_buffer[slave_buffer_pos];
  122. BUFFER_POS_INC();
  123. break;
  124. case TW_BUS_ERROR: // something went wrong, reset twi state
  125. TWCR = 0;
  126. default:
  127. break;
  128. }
  129. // Reset everything, so we are ready for the next TWI interrupt
  130. TWCR |= (1<<TWIE) | (1<<TWINT) | (ack<<TWEA) | (1<<TWEN);
  131. }