Browse Source

WIP: reform2 motherboard: rough placement

reform2-clsom
mntmn 1 year ago
parent
commit
7412294a1a
9 changed files with 11373 additions and 8715 deletions
  1. +5
    -4
      reform2-motherboard/reform2-motherboard/reform2-display.sch
  2. +2
    -2
      reform2-motherboard/reform2-motherboard/reform2-hdmi.sch
  3. +216
    -419
      reform2-motherboard/reform2-motherboard/reform2-motherboard-cache.lib
  4. +10666
    -7355
      reform2-motherboard/reform2-motherboard/reform2-motherboard.kicad_pcb
  5. +264
    -901
      reform2-motherboard/reform2-motherboard/reform2-motherboard.sch
  6. +0
    -24
      reform2-motherboard/reform2-motherboard/reform2-pcie.sch
  7. +2
    -2
      reform2-motherboard/reform2-motherboard/reform2-power.sch
  8. +2
    -8
      reform2-motherboard/reform2-motherboard/reform2-usb.sch
  9. +216
    -0
      reform2-motherboard/reform2-motherboard/reform2.lib

+ 5
- 4
reform2-motherboard/reform2-motherboard/reform2-display.sch View File

@@ -217,12 +217,9 @@ F 3 "" H 1350 1150 50 0001 C CNN
1 0 0 -1
$EndComp
Wire Wire Line
3350 1400 3350 1600
Wire Wire Line
3350 1600 3450 1600
Wire Wire Line
4050 1600 4050 1800
Connection ~ 3350 1600
Wire Wire Line
3350 1600 3350 1800
Wire Wire Line
@@ -544,7 +541,6 @@ Wire Wire Line
1350 1500 1350 1400
Wire Wire Line
3350 1400 2950 1400
Connection ~ 3350 1400
Connection ~ 1350 1400
Connection ~ 1750 1400
Wire Wire Line
@@ -1249,4 +1245,9 @@ F 3 "" H 2350 4600 50 0001 C CNN
1 2350 4600
1 0 0 -1
$EndComp
Wire Wire Line
3350 1200 3750 1200
Wire Wire Line
3750 1200 3750 1600
Connection ~ 3350 1200
$EndSCHEMATC

+ 2
- 2
reform2-motherboard/reform2-motherboard/reform2-hdmi.sch View File

@@ -46,10 +46,10 @@ HDMI_D0-
Text GLabel 2650 2200 0 50 Input ~ 0
HDMI_D0+
$Comp
L reform2:CM2020-00TR U?1
L reform2:CM2020-00TR U22
U 1 1 5D124B0E
P 4800 5100
F 0 "U?1" H 4800 6467 50 0000 C CNN
F 0 "U22" H 4800 6467 50 0000 C CNN
F 1 "CM2020-00TR" H 4800 6376 50 0000 C CNN
F 2 "footprints:TSSOP50P640X120-38N" H 4350 2950 50 0001 L BNN
F 3 "" H 4800 5100 50 0001 L BNN


+ 216
- 419
reform2-motherboard/reform2-motherboard/reform2-motherboard-cache.lib View File

@@ -2170,6 +2170,222 @@ X 4 4 200 50 100 L 40 40 0 0 P
ENDDRAW
ENDDEF
#
# reform2_CL-SOM-iMX8
#
DEF reform2_CL-SOM-iMX8 U 0 40 Y Y 1 F N
F0 "U" -50 5050 50 H V C CNN
F1 "reform2_CL-SOM-iMX8" 0 4950 50 H V C CNN
F2 "footprints:TE_2-2013289-1" -350 2700 50 H I C CNN
F3 "" -350 2700 50 H I C CNN
DRAW
S -850 4850 700 -5450 0 1 0 f
X GND 1 -950 4750 100 R 50 50 1 1 W
X VSYS 10 800 4350 100 L 50 50 1 1 O
X QSPI_A_SS1_B 100 800 -150 100 L 50 50 1 1 O
X CSI_P1_DP2 101 -950 -150 100 R 50 50 1 1 O
X QSPI_A_DQS 102 800 -250 100 L 50 50 1 1 O
X CSI_P1_DN2 103 -950 -250 100 R 50 50 1 1 O
X QSPI_A_SCLK 104 800 -350 100 L 50 50 1 1 O
X GND 105 -950 -350 100 R 50 50 1 1 O
X SAI1_RX_SYNC 106 800 -450 100 L 50 50 1 1 O
X CSI_P1_CKP 107 -950 -450 100 R 50 50 1 1 O
X SAI1_MCLK 108 800 -550 100 L 50 50 1 1 O
X CSI_P1_CKN 109 -950 -550 100 R 50 50 1 1 O
X ECSPI1_MOSI 11 -950 4250 100 R 50 50 1 1 W
X SAI1_TX_SYNC 110 800 -650 100 L 50 50 1 1 O
X UART3_TX 111 -950 -650 100 R 50 50 1 1 O
X SAI1_TX_BCLK 112 800 -750 100 L 50 50 1 1 O
X CSI_P1_DN3 113 -950 -750 100 R 50 50 1 1 O
X VSYS 114 800 -850 100 L 50 50 1 1 O
X CSI_P1_DP3 115 -950 -850 100 R 50 50 1 1 O
X SAI1_TX_DATA[0] 116 800 -950 100 L 50 50 1 1 O
X UART3_RX 117 -950 -950 100 R 50 50 1 1 O
X SAI1_TX_DATA[1] 118 800 -1050 100 L 50 50 1 1 O
X PCIE1_REF_CLKP 119 -950 -1050 100 R 50 50 1 1 O
X ETH1_MDI1N 12 800 4250 100 L 50 50 1 1 O
X SAI1_TX_DATA[2] 120 800 -1150 100 L 50 50 1 1 O
X PCIE1_REF_CLKN 121 -950 -1150 100 R 50 50 1 1 O
X SAI1_TX_DATA[3] 122 800 -1250 100 L 50 50 1 1 O
X GND 123 -950 -1250 100 R 50 50 1 1 O
X GPIO3_IO[16] 124 800 -1350 100 L 50 50 1 1 O
X PCIE1_TXN_P 125 -950 -1350 100 R 50 50 1 1 O
X SAI1_TX_DATA[3] 126 800 -1450 100 L 50 50 1 1 O
X PCIE1_TXN_N 127 -950 -1450 100 R 50 50 1 1 O
X SAI1_TX_DATA[4] 128 800 -1550 100 L 50 50 1 1 O
X ENET1_MDC 129 -950 -1550 100 R 50 50 1 1 O
X ECSPI1_SCLK 13 -950 4150 100 R 50 50 1 1 W
X SAI1_TX_DATA[7] 130 800 -1650 100 L 50 50 1 1 O
X PCIE1_RXN_P 131 -950 -1650 100 R 50 50 1 1 O
X VSYS 132 800 -1750 100 L 50 50 1 1 O
X PCIE1_RXN_N 133 -950 -1750 100 R 50 50 1 1 O
X SAI1_RX_DATA[0] 134 800 -1850 100 L 50 50 1 1 O
X ENET1_MDIO 135 -950 -1850 100 R 50 50 1 1 O
X SAI1_RX_DATA[1] 136 800 -1950 100 L 50 50 1 1 O
X SAI1_RX_DATA[4] 137 -950 -1950 100 R 50 50 1 1 O
X SAI1_RX_DATA[2] 138 800 -2050 100 L 50 50 1 1 O
X SAI1_RX_DATA[5] 139 -950 -2050 100 R 50 50 1 1 O
X SAI1_TX_DATA[5] 139 -950 -2250 100 R 50 50 1 1 O
X ETH1_MDI1P 14 800 4150 100 L 50 50 1 1 O
X SAI1_RX_DATA[3] 140 800 -2150 100 L 50 50 1 1 O
X GND 141 -950 -2350 100 R 50 50 1 1 O
X GND 141 -950 -2150 100 R 50 50 1 1 O
X SAI1_TX_BCLK 142 800 -2250 100 L 50 50 1 1 O
X SAI1_TX_DATA[5] 143 -950 -2450 100 R 50 50 1 1 O
X SAI1_TX_DATA[0] 144 800 -2350 100 L 50 50 1 1 O
X SAI1_RX_DATA[6] 145 -950 -2550 100 R 50 50 1 1 O
X SAI1_TX_DATA[1] 146 800 -2450 100 L 50 50 1 1 O
X QSPI_B_SCLK 147 -950 -2650 100 R 50 50 1 1 O
X SAI1_TX_DATA[2] 148 800 -2550 100 L 50 50 1 1 O
X QSPI_B_DATA[3] 149 -950 -2750 100 R 50 50 1 1 O
X ECSPI1_MISO 15 -950 4050 100 R 50 50 1 1 W
X VSYS 150 800 -2650 100 L 50 50 1 1 O
X QSPI_B_DATA[2] 151 -950 -2850 100 R 50 50 1 1 O
X SAI1_RX_DATA[7] 152 800 -2750 100 L 50 50 1 1 O
X QSPI_B_DATA[1] 153 -950 -2950 100 R 50 50 1 1 O
X USDHC2_RESET_B 154 800 -2850 100 L 50 50 1 1 O
X QSPI_B_DATA[0] 155 -950 -3050 100 R 50 50 1 1 O
X USB2_VBUS_DET 156 800 -2950 100 L 50 50 1 1 O
X QSPI_B_DQS 157 -950 -3150 100 R 50 50 1 1 O
X USB2_RX_P 158 800 -3050 100 L 50 50 1 1 O
X GND 159 -950 -3250 100 R 50 50 1 1 O
X ETH1_LED1_SPD 16 800 4050 100 L 50 50 1 1 O
X USB2_RX_N 160 800 -3150 100 L 50 50 1 1 O
X LVDS1_TX3_P 161 -950 -3350 100 R 50 50 1 1 O
X SAI1_TX_DATA[6] 162 800 -3250 100 L 50 50 1 1 O
X LVDS1_TX3_N 163 -950 -3450 100 R 50 50 1 1 O
X USB2_TX_P 164 800 -3350 100 L 50 50 1 1 O
X ONOFF 165 -950 -3550 100 R 50 50 1 1 O
X USB2_TX_N 166 800 -3450 100 L 50 50 1 1 O
X PCIE2_RXN_N 167 -950 -3650 100 R 50 50 1 1 O
X VSYS 168 800 -3550 100 L 50 50 1 1 O
X PCIE2_RXN_P 169 -950 -3750 100 R 50 50 1 1 O
X ECSPI1_SS0 17 -950 3950 100 R 50 50 1 1 W
X USB2_DN 170 800 -3650 100 L 50 50 1 1 O
X COLD_RESET_IN 171 -950 -3850 100 R 50 50 1 1 O
X USB2_DP 172 800 -3750 100 L 50 50 1 1 O
X PCIE2_TXN_N 173 -950 -3950 100 R 50 50 1 1 O
X USB1_ID 174 800 -3850 100 L 50 50 1 1 O
X PCIE2_TXN_P 175 -950 -4050 100 R 50 50 1 1 O
X USB1_DP 176 800 -3950 100 L 50 50 1 1 O
X GND 177 -950 -4150 100 R 50 50 1 1 O
X USB1_DN 178 800 -4050 100 L 50 50 1 1 O
X PCIE2_REF_CLKN 179 -950 -4250 100 R 50 50 1 1 O
X ETH1_MDI2N 18 800 3950 100 L 50 50 1 1 O
X USB1_VBUS_DET 180 800 -4150 100 L 50 50 1 1 O
X PCIE2_REF_CLKP 181 -950 -4350 100 R 50 50 1 1 O
X USB1_RX_P 182 800 -4250 100 L 50 50 1 1 O
X VCC_RTC 183 -950 -4450 100 R 50 50 1 1 O
X USB1_RX_N 184 800 -4350 100 L 50 50 1 1 O
X ALT_BOOT 185 -950 -4550 100 R 50 50 1 1 O
X VSYS 186 800 -4450 100 L 50 50 1 1 O
X NC 187 -950 -4650 100 R 50 50 1 1 O
X USB1_TX_P 188 800 -4550 100 L 50 50 1 1 O
X EEPROM_WP 189 -950 -4750 100 R 50 50 1 1 O
X GND 19 -950 3850 100 R 50 50 1 1 W
X USB1_TX_N 190 800 -4650 100 L 50 50 1 1 O
X MICBIAS 191 -950 -4850 100 R 50 50 1 1 O
X SAI1_RX_BCLK 192 800 -4750 100 L 50 50 1 1 O
X MICIN 193 -950 -4950 100 R 50 50 1 1 O
X SAI1_TX_DATA[4] 194 800 -4850 100 L 50 50 1 1 O
X AUD_GND 195 -950 -5050 100 R 50 50 1 1 O
X PWM3_OUT 196 800 -4950 100 L 50 50 1 1 O
X SAI2_TX_BCLK 197 -950 -5150 100 R 50 50 1 1 O
X PWM2_OUT 198 800 -5050 100 L 50 50 1 1 O
X AVDD33_ETH 2 800 4750 100 L 50 50 1 1 O
X ETH1_MDI2P 20 800 3850 100 L 50 50 1 1 O
X PWM1_OUT 200 800 -5150 100 L 50 50 1 1 O
X SAI2_TX_SYNC 201 -950 -5250 100 R 50 50 1 1 O
X PMIC_ON_REQ 202 800 -5250 100 L 50 50 1 1 O
X SAI2_RX_DATA[0] 203 -950 -5350 100 R 50 50 1 1 O
X VSYS 204 800 -5350 100 L 50 50 1 1 O
X LVDS1_TX0_P 21 -950 3750 100 R 50 50 1 1 O
X ETH1_LED3 22 800 3750 100 L 50 50 1 1 O
X LVDS1_TX0_N 23 -950 3650 100 R 50 50 1 1 O
X ETH1_MDI3N 24 800 3650 100 L 50 50 1 1 O
X HDMI_DDC_SCL 25 -950 3550 100 R 50 50 1 1 O
X ETH1_MDI3P 26 800 3550 100 L 50 50 1 1 O
X HDMI_AUXN 27 -950 3450 100 R 50 50 1 1 O
X VSYS 28 800 3450 100 L 50 50 1 1 O
X HDMI_AUXP 29 -950 3350 100 R 50 50 1 1 O
X PCIE2_CLKREQ_B 3 -950 4650 100 R 50 50 1 1 W
X HDMI_CLKP 30 800 3350 100 L 50 50 1 1 O
X HDMI_DDC_SDA 31 -950 3250 100 R 50 50 1 1 O
X HDMI_CLKN 32 800 3250 100 L 50 50 1 1 O
X DSI_DP2 33 -950 3150 100 R 50 50 1 1 O
X HDMI_CEC 34 800 3150 100 L 50 50 1 1 O
X DSI_DN2 35 -950 3050 100 R 50 50 1 1 O
X HDMI_TXP0 36 800 3050 100 L 50 50 1 1 O
X GND 37 -950 2950 100 R 50 50 1 1 O
X HDMI_TXN0 38 800 2950 100 L 50 50 1 1 O
X DSI_DP0 39 -950 2850 100 R 50 50 1 1 O
X ETH1_LED_ACT 4 800 4650 100 L 50 50 1 1 O
X HDMI_HPD 40 800 2850 100 L 50 50 1 1 O
X DSI_DN0 41 -950 2750 100 R 50 50 1 1 O
X HDMI_TXP1 42 800 2750 100 L 50 50 1 1 O
X I2C3_SCL 43 -950 2650 100 R 50 50 1 1 O
X HDMI_TXN1 44 800 2650 100 L 50 50 1 1 O
X DSI_DP1 45 -950 2550 100 R 50 50 1 1 O
X VSYS 46 800 2550 100 L 50 50 1 1 O
X DSI_DN1 47 -950 2450 100 R 50 50 1 1 O
X HDMI_TXP2 48 800 2450 100 L 50 50 1 1 O
X I2C3_SDA 49 -950 2350 100 R 50 50 1 1 O
X PCIE1_CLKREQ_B 5 -950 4550 100 R 50 50 1 1 W
X HDMI_TXN2 50 800 2350 100 L 50 50 1 1 O
X DSI_DP3 51 -950 2250 100 R 50 50 1 1 O
X ENET1_MDC 52 800 2250 100 L 50 50 1 1 O
X DSI_DN3 53 -950 2150 100 R 50 50 1 1 O
X JTAG_MOD 54 800 2150 100 L 50 50 1 1 O
X GND 55 -950 2050 100 R 50 50 1 1 O
X JTAG_NTRST 56 800 2050 100 L 50 50 1 1 O
X DSI_CKN 57 -950 1950 100 R 50 50 1 1 O
X UART2_TX 58 800 1950 100 L 50 50 1 1 O
X DSI_CKP 59 -950 1850 100 R 50 50 1 1 O
X ETH1_MDI0N 6 800 4550 100 L 50 50 1 1 O
X GPIO3_IO[17] 60 800 1850 100 L 50 50 1 1 O
X USDHC2_CD_B 61 -950 1750 100 R 50 50 1 1 O
X GPIO1_IO[19] 62 800 1750 100 L 50 50 1 1 O
X VSYS 64 800 1650 100 L 50 50 1 1 O
X ECSPI3_MISO 65 -950 1650 100 R 50 50 1 1 O
X JTAG_TCK 66 800 1550 100 L 50 50 1 1 O
X USDHC2_WP 67 -950 1550 100 R 50 50 1 1 O
X JTAG_TMS 68 800 1450 100 L 50 50 1 1 O
X ECSPI3_SCLK 69 -950 1450 100 R 50 50 1 1 O
X QSPI_BSS0_B 7 -950 4450 100 R 50 50 1 1 W
X JTAG_TDI 70 800 1350 100 L 50 50 1 1 O
X GND 71 -950 1350 100 R 50 50 1 1 O
X JTAG_TDO 72 800 1250 100 L 50 50 1 1 O
X PCIE1_CLKREQ_B 73 -950 1250 100 R 50 50 1 1 O
X QSPI_A_DATA[0] 74 800 1150 100 L 50 50 1 1 O
X PCIE2_CLKREQ_B 75 -950 1150 100 R 50 50 1 1 O
X QSPI_A_DATA[1] 76 800 1050 100 L 50 50 1 1 O
X LVDS1_CLK_P 77 -950 1050 100 R 50 50 1 1 O
X VSYS 78 800 950 100 L 50 50 1 1 O
X LVDS1_CLK_N 79 -950 950 100 R 50 50 1 1 O
X ETH1_MDI0P 8 800 4450 100 L 50 50 1 1 O
X USDHC2_CLK 80 800 850 100 L 50 50 1 1 O
X GPIO3_IO[18] 81 -950 850 100 R 50 50 1 1 O
X USDHC2_CMD 82 800 750 100 L 50 50 1 1 O
X CSI_P1_DP0 83 -950 750 100 R 50 50 1 1 O
X USDHC2_DATA0 84 800 650 100 L 50 50 1 1 O
X CSI_P1_DN0 85 -950 650 100 R 50 50 1 1 O
X USDHC2_DATA1 86 800 550 100 L 50 50 1 1 O
X GND 87 -950 550 100 R 50 50 1 1 O
X USDHC2_DATA2 88 800 450 100 L 50 50 1 1 O
X CSI_P1_DP1 89 -950 450 100 R 50 50 1 1 O
X QSPI_B_SS1_B 9 -950 4350 100 R 50 50 1 1 W
X USDHC2_DATA3 90 800 350 100 L 50 50 1 1 O
X CSI_P1_DN1 91 -950 350 100 R 50 50 1 1 O
X QSPI_A_DATA[2] 92 800 250 100 L 50 50 1 1 O
X LVDS1_TX1_P 93 -950 250 100 R 50 50 1 1 O
X QSPI_A_DATA[3] 94 800 150 100 L 50 50 1 1 O
X LVDS1_TX1_N 95 -950 150 100 R 50 50 1 1 O
X VSYS 96 800 50 100 L 50 50 1 1 O
X LVDS1_TX2_P 97 -950 50 100 R 50 50 1 1 O
X QSPI_A_SS0_B 98 800 -50 100 L 50 50 1 1 O
X LVDS1_TX2_N 99 -950 -50 100 R 50 50 1 1 O
ENDDRAW
ENDDEF
#
# reform2_CM2020-00TR
#
DEF reform2_CM2020-00TR U? 0 40 Y Y 1 F N
@@ -2448,423 +2664,4 @@ X LHPOUT 9 550 -600 100 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# reform2_phycore-imx8m-alpha
#
DEF reform2_phycore-imx8m-alpha U 0 40 Y Y 1 F N
F0 "U" 0 0 50 H V C CNN
F1 "reform2_phycore-imx8m-alpha" 0 0 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
X ETH0_LED2_ACT A1 0 0 100 R 50 50 1 1 C
X ETH0_D A10 0 900 100 R 50 50 1 1 B
X MIPI_CSI1_D1_N A100 0 9900 100 R 50 50 1 1 I
X MIPI_CSI1_CLK_P A101 0 10000 100 R 50 50 1 1 O
X MIPI_CSI1_CLK_N A102 0 10100 100 R 50 50 1 1 O
X MIPI_CSI1_D2_P A103 0 10200 100 R 50 50 1 1 I
X MIPI_CSI1_D2_N A104 0 10300 100 R 50 50 1 1 I
X MIPI_CSI1_D3_P A105 0 10400 100 R 50 50 1 1 I
X MIPI_CSI1_D3_N A106 0 10500 100 R 50 50 1 1 I
X PCIE1_TXN_N A107 0 10600 100 R 50 50 1 1 O
X PCIE1_TXN_P A108 0 10700 100 R 50 50 1 1 O
X PCIE1_RXN_N A109 0 10800 100 R 50 50 1 1 I
X NVCC_SD2 A11 0 1000 100 R 50 50 1 1 w
X PCIE1_RXN_P A110 0 10900 100 R 50 50 1 1 I
X PCIE1_REF_PAD_CLK_N A111 0 11000 100 R 50 50 1 1 I
X PCIE1_REF_PAD_CLK_P A112 0 11100 100 R 50 50 1 1 I
X PCIE2_REF_PAD_CLK_N A113 0 11200 100 R 50 50 1 1 I
X PCIE2_REF_PAD_CLK_P A114 0 11300 100 R 50 50 1 1 I
X PCIE2_TXN_P A115 0 11400 100 R 50 50 1 1 O
X PCIE2_TXN_N A116 0 11500 100 R 50 50 1 1 O
X PCIE2_RXN_N A117 0 11600 100 R 50 50 1 1 I
X PCIE2_RXN_P A118 0 11700 100 R 50 50 1 1 I
X CLK2_P A119 0 11800 100 R 50 50 1 1 O
X SD2_RESET_B A12 0 1100 100 R 50 50 1 1 O
X CLK2_N A120 0 11900 100 R 50 50 1 1 O
X CLK1_P A121 0 12000 100 R 50 50 1 1 O
X CLK1_N A122 0 12100 100 R 50 50 1 1 O
X MIPI_DSI_D2_P A123 0 12200 100 R 50 50 1 1 O
X MIPI_DSI_D2_N A124 0 12300 100 R 50 50 1 1 O
X MIPI_DSI_D1_P A125 0 12400 100 R 50 50 1 1 O
X MIPI_DSI_D1_N A126 0 12500 100 R 50 50 1 1 O
X MIPI_DSI_CLK_P A127 0 12600 100 R 50 50 1 1 O
X MIPI_DSI_CLK_N A128 0 12700 100 R 50 50 1 1 O
X MIPI_DSI_D0_P A129 0 12800 100 R 50 50 1 1 O
X SD2_WP A13 0 1200 100 R 50 50 1 1 I
X MIPI_DSI_D0_N A130 0 12900 100 R 50 50 1 1 O
X MIPI_DSI_D3_P A131 0 13000 100 R 50 50 1 1 O
X MIPI_DSI_D3_N A132 0 13100 100 R 50 50 1 1 O
X SD2_CD_B A14 0 1300 100 R 50 50 1 1 I
X SD2_DATA1_EXT A15 0 1400 100 R 50 50 1 1 B
X SD2_DATA0_EXT A16 0 1500 100 R 50 50 1 1 B
X SD2_CLK_EXT A17 0 1600 100 R 50 50 1 1 O
X SD2_CMD_EXT A18 0 1700 100 R 50 50 1 1 O
X SD2_DATA3_EXT A19 0 1800 100 R 50 50 1 1 B
X ETH0_LED0_LINK A2 0 100 100 R 50 50 1 1 C
X SD2_DATA2_EXT A20 0 1900 100 R 50 50 1 1 B
X USB1_DP A21 0 2000 100 R 50 50 1 1 B
X USB1_DN A22 0 2100 100 R 50 50 1 1 B
X USB1_TX_P A23 0 2200 100 R 50 50 1 1 O
X USB1_TX_N A24 0 2300 100 R 50 50 1 1 O
X USB1_RX_P A25 0 2400 100 R 50 50 1 1 I
X USB1_RX_N A26 0 2500 100 R 50 50 1 1 I
X USB2_DP A27 0 2600 100 R 50 50 1 1 B
X USB2_DN A28 0 2700 100 R 50 50 1 1 B
X USB2_TX_P A29 0 2800 100 R 50 50 1 1 O
X ETH0_A+ A3 0 200 100 R 50 50 1 1 B
X USB2_TX_N A30 0 2900 100 R 50 50 1 1 O
X USB2_RX_P A31 0 3000 100 R 50 50 1 1 I
X USB2_RX_N A32 0 3100 100 R 50 50 1 1 I
X HDMI_AUX_N A33 0 3200 100 R 50 50 1 1 O
X HDMI_AUX_P A34 0 3300 100 R 50 50 1 1 O
X HDMI_TX_M_LN_3 A35 0 3400 100 R 50 50 1 1 O
X HDMI_TX_P_LN_3 A36 0 3500 100 R 50 50 1 1 O
X HDMI_TX_M_LN_0 A37 0 3600 100 R 50 50 1 1 O
X HDMI_TX_P_LN_0 A38 0 3700 100 R 50 50 1 1 O
X HDMI_TX_M_LN_1 A39 0 3800 100 R 50 50 1 1 O
X ETH0_A A4 0 300 100 R 50 50 1 1 B
X HDMI_TX_P_LN_1 A40 0 3900 100 R 50 50 1 1 O
X HDMI_TX_M_LN_2 A41 0 4000 100 R 50 50 1 1 O
X HDMI_TX_P_LN_2 A42 0 4100 100 R 50 50 1 1 O
X WLAN_EN A43 0 4200 100 R 50 50 1 1 I
X BT_EN A44 0 4300 100 R 50 50 1 1 I
X WIFI_HCI_UART_WAKEHOST_L A45 0 4400 100 R 50 50 1 1 I
X WIFI_WLAN_RF_KILL_L A46 0 4500 100 R 50 50 1 1 I
X WIFI_SELECT A47 0 4600 100 R 50 50 1 1 I
X WIFI_CLK_REQ A48 0 4700 100 R 50 50 1 1 I
X WIFI_CLK_REQ A49 0 4800 100 R 50 50 1 1 I
X ETH0_B+ A5 0 400 100 R 50 50 1 1 B
X NC A50 0 4900 100 R 50 50 1 1 N
X NC A51 0 5000 100 R 50 50 1 1 N
X NC A52 0 5100 100 R 50 50 1 1 N
X VDD_3V3 A53 0 5200 100 R 50 50 1 1 W
X VDD_3V3 A54 0 5300 100 R 50 50 1 1 W
X PMIC_nSDWN A55 0 5400 100 R 50 50 1 1 E
X PMIC_STBY_REQ A56 0 5500 100 R 50 50 1 1 I
X nPMIC_INT A57 0 5600 100 R 50 50 1 1 E
X ONOFF A58 0 5700 100 R 50 50 1 1 I
X BOOT_MODE0 A59 0 5800 100 R 50 50 1 1 I
X ETH0_B A6 0 500 100 R 50 50 1 1 B
X BOOT_MODE1 A60 0 5900 100 R 50 50 1 1 I
X POR_B A61 0 6000 100 R 50 50 1 1 B
X nRESET_IN A62 0 6100 100 R 50 50 1 1 I
X PMIC_ON_REQ A63 0 6200 100 R 50 50 1 1 I
X PGOOD_OD A64 0 6300 100 R 50 50 1 1 E
X VDD_IN_3V3 A65 0 6400 100 R 50 50 1 1 W
X VDD_IN_3V3 A66 0 6500 100 R 50 50 1 1 W
X VDD_IN_3V3 A67 0 6600 100 R 50 50 1 1 W
X VDD_IN_3V3 A68 0 6700 100 R 50 50 1 1 W
X MIPI_CSI2_D0_P A69 0 6800 100 R 50 50 1 1 I
X ETH0_C+ A7 0 600 100 R 50 50 1 1 B
X MIPI_CSI2_D0_N A70 0 6900 100 R 50 50 1 1 I
X MIPI_CSI2_D1_P A71 0 7000 100 R 50 50 1 1 I
X MIPI_CSI2_D1_N A72 0 7100 100 R 50 50 1 1 I
X MIPI_CSI2_CLK_P A73 0 7200 100 R 50 50 1 1 I
X MIPI_CSI2_CLK_N A74 0 7300 100 R 50 50 1 1 I
X MIPI_CSI2_D2_P A75 0 7400 100 R 50 50 1 1 I
X MIPI_CSI2_D2_N A76 0 7500 100 R 50 50 1 1 I
X MIPI_CSI2_D3_P A77 0 7600 100 R 50 50 1 1 I
X MIPI_CSI2_D3_N A78 0 7700 100 R 50 50 1 1 I
X JTAG_TCK A79 0 7800 100 R 50 50 1 1 I
X ETH0_C A8 0 700 100 R 50 50 1 1 B
X JTAG_TMS A80 0 7900 100 R 50 50 1 1 I
X JTAG_TDI A81 0 8000 100 R 50 50 1 1 I
X JTAG_TDO A82 0 8100 100 R 50 50 1 1 O
X JTAG_TRST_B A83 0 8200 100 R 50 50 1 1 I
X JTAG_MOD A84 0 8300 100 R 50 50 1 1 I
X ETH_JTAG_TMS A85 0 8400 100 R 50 50 1 1 I
X ETH_JTAG_TDO A86 0 8500 100 R 50 50 1 1 O
X ETH_JTAG_TDI A87 0 8600 100 R 50 50 1 1 I
X ETH_JTAG_CLK A88 0 8700 100 R 50 50 1 1 I
X I2C3_SCL A89 0 8800 100 R 50 50 1 1 O
X ETH0_D+ A9 0 800 100 R 50 50 1 1 B
X I2C3_SDA A90 0 8900 100 R 50 50 1 1 B
X VDD_1V8 A91 0 9000 100 R 50 50 1 1 w
X VDD_1V8 A92 0 9100 100 R 50 50 1 1 w
X I2C4_SCL A93 0 9200 100 R 50 50 1 1 O
X I2C4_SDA A94 0 9300 100 R 50 50 1 1 B
X I2C2_SCL A95 0 9400 100 R 50 50 1 1 O
X I2C2_SDA A96 0 9500 100 R 50 50 1 1 B
X MIPI_CSI1_D0_P A97 0 9600 100 R 50 50 1 1 I
X MIPI_CSI1_D0_N A98 0 9700 100 R 50 50 1 1 I
X MIPI_CSI1_D1_P A99 0 9800 100 R 50 50 1 1 I
X GND B1 2000 0 100 R 50 50 1 1 W
X GND B10 2000 900 100 R 50 50 1 1 W
X GND B11 2000 1000 100 R 50 50 1 1 W
X GND B12 2000 1100 100 R 50 50 1 1 W
X GND B13 2000 1200 100 R 50 50 1 1 W
X GND B14 2000 1300 100 R 50 50 1 1 W
X GND B15 2000 1400 100 R 50 50 1 1 W
X GND B16 2000 1500 100 R 50 50 1 1 W
X GND B17 2000 1600 100 R 50 50 1 1 W
X GND B18 2000 1700 100 R 50 50 1 1 W
X GND B19 2000 1800 100 R 50 50 1 1 W
X GND B2 2000 100 100 R 50 50 1 1 W
X GND B20 2000 1900 100 R 50 50 1 1 W
X GND B21 2000 2000 100 R 50 50 1 1 W
X GND B22 2000 2100 100 R 50 50 1 1 W
X GND B23 2000 2200 100 R 50 50 1 1 W
X GND B24 2000 2300 100 R 50 50 1 1 W
X GND B25 2000 2400 100 R 50 50 1 1 W
X GND B26 2000 2500 100 R 50 50 1 1 W
X GND B27 2000 2600 100 R 50 50 1 1 W
X GND B28 2000 2700 100 R 50 50 1 1 W
X GND B29 2000 2800 100 R 50 50 1 1 W
X GND B3 2000 200 100 R 50 50 1 1 W
X GND B30 2000 2900 100 R 50 50 1 1 W
X GND B31 2000 3000 100 R 50 50 1 1 W
X GND B32 2000 3100 100 R 50 50 1 1 W
X GND B33 2000 3200 100 R 50 50 1 1 W
X GND B34 2000 3300 100 R 50 50 1 1 W
X GND B35 2000 3400 100 R 50 50 1 1 W
X GND B36 2000 3500 100 R 50 50 1 1 W
X GND B37 2000 3600 100 R 50 50 1 1 W
X GND B38 2000 3700 100 R 50 50 1 1 W
X GND B39 2000 3800 100 R 50 50 1 1 W
X GND B4 2000 300 100 R 50 50 1 1 W
X GND B40 2000 3900 100 R 50 50 1 1 W
X GND B41 2000 4000 100 R 50 50 1 1 W
X GND B42 2000 4100 100 R 50 50 1 1 W
X GND B43 2000 4200 100 R 50 50 1 1 W
X GND B44 2000 4300 100 R 50 50 1 1 W
X GND B45 2000 4400 100 R 50 50 1 1 W
X GND B46 2000 4500 100 R 50 50 1 1 W
X GND B47 2000 4600 100 R 50 50 1 1 W
X GND B48 2000 4700 100 R 50 50 1 1 W
X GND B49 2000 4800 100 R 50 50 1 1 W
X GND B5 2000 400 100 R 50 50 1 1 W
X GND B50 2000 4900 100 R 50 50 1 1 W
X GND B51 2000 5000 100 R 50 50 1 1 W
X GND B52 2000 5100 100 R 50 50 1 1 W
X GND B53 2000 5200 100 R 50 50 1 1 W
X GND B54 2000 5300 100 R 50 50 1 1 W
X GND B55 2000 5400 100 R 50 50 1 1 W
X GND B56 2000 5500 100 R 50 50 1 1 W
X GND B57 2000 5600 100 R 50 50 1 1 W
X GND B58 2000 5700 100 R 50 50 1 1 W
X GND B59 2000 5800 100 R 50 50 1 1 W
X GND B6 2000 500 100 R 50 50 1 1 W
X GND B60 2000 5900 100 R 50 50 1 1 W
X GND B61 2000 6000 100 R 50 50 1 1 W
X GND B62 2000 6100 100 R 50 50 1 1 W
X GND B63 2000 6200 100 R 50 50 1 1 W
X GND B64 2000 6300 100 R 50 50 1 1 W
X GND B65 2000 6400 100 R 50 50 1 1 W
X GND B66 2000 6500 100 R 50 50 1 1 W
X GND B7 2000 600 100 R 50 50 1 1 W
X GND B8 2000 700 100 R 50 50 1 1 W
X GND B9 2000 800 100 R 50 50 1 1 W
X SAI5_RXD0 C1 4000 0 100 R 50 50 1 1 I
X SAI3_RXD C10 4000 900 100 R 50 50 1 1 I
X NAND_CE2_B C100 4000 9900 100 R 50 50 1 1 B
X NAND_ALE C101 4000 10000 100 R 50 50 1 1 B
X SPDIF_EXT_CLK C102 4000 10100 100 R 50 50 1 1 O
X SPDIF_TX C103 4000 10200 100 R 50 50 1 1 O
X SPDIF_RX C104 4000 10300 100 R 50 50 1 1 I
X SAI3_TXD C11 4000 1000 100 R 50 50 1 1 O
X SAI3_TXFS C12 4000 1100 100 R 50 50 1 1 O
X SAI3_TXC C13 4000 1200 100 R 50 50 1 1 O
X SAI3_MCLK C14 4000 1300 100 R 50 50 1 1 O
X USB1_ID C15 4000 1400 100 R 50 50 1 1 I
X USB1_VBUS C16 4000 1500 100 R 50 50 1 1 I
X GPIO1_IO12 C17 4000 1600 100 R 50 50 1 1 B
X GPIO1_IO13 C18 4000 1700 100 R 50 50 1 1 B
X NC C19 4000 1800 100 R 50 50 1 1 W
X SAI5_RXD1 C2 4000 100 100 R 50 50 1 1 I
X SAI2_RXC C20 4000 1900 100 R 50 50 1 1 I
X SAI2_RXFS C21 4000 2000 100 R 50 50 1 1 I
X SAI2_RXD0 C22 4000 2100 100 R 50 50 1 1 I
X SAI2_TXD0 C23 4000 2200 100 R 50 50 1 1 O
X SAI2_TXFS C24 4000 2300 100 R 50 50 1 1 O
X SAI2_TXC C25 4000 2400 100 R 50 50 1 1 O
X SAI2_MCLK C26 4000 2500 100 R 50 50 1 1 O
X USB2_ID C27 4000 2600 100 R 50 50 1 1 I
X USB2_VBUS C28 4000 2700 100 R 50 50 1 1 I
X GPIO1_IO14 C29 4000 2800 100 R 50 50 1 1 B
X SAI5_RXD2 C3 4000 200 100 R 50 50 1 1 I
X GPIO1_IO15 C30 4000 2900 100 R 50 50 1 1 B
X HDMI_DDC_SDA C31 4000 3000 100 R 50 50 1 1 B
X HDMI_DDC_SCL C32 4000 3100 100 R 50 50 1 1 O
X HDMI_CEC C33 4000 3200 100 R 50 50 1 1 B
X HDMI_HPD C34 4000 3300 100 R 50 50 1 1 I
X UART3_TXD C35 4000 3400 100 R 50 50 1 1 O
X UART3_RXD C36 4000 3500 100 R 50 50 1 1 I
X NC C37 4000 3600 100 R 50 50 1 1 W
X NC C38 4000 3700 100 R 50 50 1 1 W
X UART1_RXD C39 4000 3800 100 R 50 50 1 1 I
X SAI5_RXD3 C4 4000 300 100 R 50 50 1 1 I
X UART1_TXD C40 4000 3900 100 R 50 50 1 1 O
X GPIO1_IO08 C41 4000 4000 100 R 50 50 1 1 B
X GPIO1_IO09 C42 4000 4100 100 R 50 50 1 1 B
X GPIO1_IO10 C43 4000 4200 100 R 50 50 1 1 B
X GPIO1_IO11 C44 4000 4300 100 R 50 50 1 1 B
X I2C1_SCL C45 4000 4400 100 R 50 50 1 1 O
X I2C1_SDA C46 4000 4500 100 R 50 50 1 1 B
X NC C47 4000 4600 100 R 50 50 1 1 W
X NC C48 4000 4700 100 R 50 50 1 1 W
X SAI1_MCLK C49 4000 4800 100 R 50 50 1 1 O
X SAI5_RXC C5 4000 400 100 R 50 50 1 1 I
X SAI1_TXD7/BOOT_CFG[15] C50 4000 4900 100 R 50 50 1 1 O
X SAI1_TXD6/BOOT_CFG[14] C51 4000 5000 100 R 50 50 1 1 O
X SAI1_TXD5/BOOT_CFG[13] C52 4000 5100 100 R 50 50 1 1 O
X SAI1_TXD4/BOOT_CFG[12] C53 4000 5200 100 R 50 50 1 1 O
X SAI1_TXD3/BOOT_CFG[11] C54 4000 5300 100 R 50 50 1 1 O
X SAI1_TXD2/BOOT_CFG[10] C55 4000 5400 100 R 50 50 1 1 O
X SAI1_TXD1/BOOT_CFG[9] C56 4000 5500 100 R 50 50 1 1 O
X SAI1_TXD0/BOOT_CFG[8] C57 4000 5600 100 R 50 50 1 1 O
X SAI1_TXC C58 4000 5700 100 R 50 50 1 1 O
X SAI1_TXFS C59 4000 5800 100 R 50 50 1 1 O
X SAI5_MCLK C6 4000 500 100 R 50 50 1 1 O
X SAI1_RXD7/BOOT_CFG[7] C60 4000 5900 100 R 50 50 1 1 I
X SAI1_RXD6/BOOT_CFG[6] C61 4000 6000 100 R 50 50 1 1 I
X SAI1_RXD5/BOOT_CFG[5] C62 4000 6100 100 R 50 50 1 1 I
X SAI1_RXD4/BOOT_CFG[4] C63 4000 6200 100 R 50 50 1 1 I
X SAI1_RXD3/BOOT_CFG[3] C64 4000 6300 100 R 50 50 1 1 I
X SAI1_RXD2/BOOT_CFG[2] C65 4000 6400 100 R 50 50 1 1 I
X SAI1_RXD1/BOOT_CFG[1] C66 4000 6500 100 R 50 50 1 1 I
X SAI1_RXD0/BOOT_CFG[0] C67 4000 6600 100 R 50 50 1 1 I
X SAI1_RXC C68 4000 6700 100 R 50 50 1 1 I
X SAI1_RXFS C69 4000 6800 100 R 50 50 1 1 I
X SAI5_RXFS C7 4000 600 100 R 50 50 1 1 I
X NC C70 4000 6900 100 R 50 50 1 1 W
X ECSPI1_MOSI C71 4000 7000 100 R 50 50 1 1 O
X ECSPI1_MISO C72 4000 7100 100 R 50 50 1 1 I
X ECSPI1_SS0 C73 4000 7200 100 R 50 50 1 1 O
X ECSPI1_SCLK C74 4000 7300 100 R 50 50 1 1 O
X ECSPI2_MOSI C75 4000 7400 100 R 50 50 1 1 O
X ECSPI2_MISO C76 4000 7500 100 R 50 50 1 1 I
X ECSPI2_SS0 C77 4000 7600 100 R 50 50 1 1 O
X ECSPI2_SCLK C78 4000 7700 100 R 50 50 1 1 O
X GPIO1_IO01 C79 4000 7800 100 R 50 50 1 1 B
X SAI3_RXC C8 4000 700 100 R 50 50 1 1 I
X GPIO1_IO03/WIFI_SELECT C80 4000 7900 100 R 50 50 1 1 B
X GPIO1_IO04/SD2_VSELECT C81 4000 8000 100 R 50 50 1 1 B
X GPIO1_IO06 C82 4000 8100 100 R 50 50 1 1 B
X NAND_DATA00 C83 4000 8200 100 R 50 50 1 1 B
X NAND_DATA01 C84 4000 8300 100 R 50 50 1 1 B
X NAND_DATA02 C85 4000 8400 100 R 50 50 1 1 B
X NAND_DATA03 C86 4000 8500 100 R 50 50 1 1 B
X NAND_DATA04 C87 4000 8600 100 R 50 50 1 1 B
X NAND_DATA05 C88 4000 8700 100 R 50 50 1 1 B
X NAND_DATA06 C89 4000 8800 100 R 50 50 1 1 B
X SAI3_RXFS C9 4000 800 100 R 50 50 1 1 I
X NAND_DATA07 C90 4000 8900 100 R 50 50 1 1 B
X NAND_RE_B C91 4000 9000 100 R 50 50 1 1 B
X NAND_READY_B C92 4000 9100 100 R 50 50 1 1 B
X NAND_CE0_B C93 4000 9200 100 R 50 50 1 1 B
X NAND_CE1_B C94 4000 9300 100 R 50 50 1 1 B
X NAND_WE_B C95 4000 9400 100 R 50 50 1 1 B
X NAND_WP_B C96 4000 9500 100 R 50 50 1 1 B
X NAND_CE3_B C97 4000 9600 100 R 50 50 1 1 B
X NAND_CLE C98 4000 9700 100 R 50 50 1 1 B
X NAND_DQS C99 4000 9800 100 R 50 50 1 1 B
X GND D1 6000 0 100 R 50 50 1 1 W
X GND D10 6000 900 100 R 50 50 1 1 W
X GND D11 6000 1000 100 R 50 50 1 1 W
X GND D12 6000 1100 100 R 50 50 1 1 W
X GND D13 6000 1200 100 R 50 50 1 1 W
X GND D14 6000 1300 100 R 50 50 1 1 W
X GND D15 6000 1400 100 R 50 50 1 1 W
X GND D16 6000 1500 100 R 50 50 1 1 W
X GND D17 6000 1600 100 R 50 50 1 1 W
X GND D18 6000 1700 100 R 50 50 1 1 W
X GND D19 6000 1800 100 R 50 50 1 1 W
X GND D2 6000 100 100 R 50 50 1 1 W
X GND D20 6000 1900 100 R 50 50 1 1 W
X GND D21 6000 2000 100 R 50 50 1 1 W
X GND D22 6000 2100 100 R 50 50 1 1 W
X GND D23 6000 2200 100 R 50 50 1 1 W
X GND D24 6000 2300 100 R 50 50 1 1 W
X GND D25 6000 2400 100 R 50 50 1 1 W
X GND D26 6000 2500 100 R 50 50 1 1 W
X GND D27 6000 2600 100 R 50 50 1 1 W
X GND D28 6000 2700 100 R 50 50 1 1 W
X GND D29 6000 2800 100 R 50 50 1 1 W
X GND D3 6000 200 100 R 50 50 1 1 W
X GND D30 6000 2900 100 R 50 50 1 1 W
X GND D31 6000 3000 100 R 50 50 1 1 W
X GND D32 6000 3100 100 R 50 50 1 1 W
X GND D33 6000 3200 100 R 50 50 1 1 W
X GND D34 6000 3300 100 R 50 50 1 1 W
X GND D35 6000 3400 100 R 50 50 1 1 W
X GND D36 6000 3500 100 R 50 50 1 1 W
X GND D37 6000 3600 100 R 50 50 1 1 W
X GND D38 6000 3700 100 R 50 50 1 1 W
X GND D39 6000 3800 100 R 50 50 1 1 W
X GND D4 6000 300 100 R 50 50 1 1 W
X GND D40 6000 3900 100 R 50 50 1 1 W
X GND D41 6000 4000 100 R 50 50 1 1 W
X GND D42 6000 4100 100 R 50 50 1 1 W
X GND D43 6000 4200 100 R 50 50 1 1 W
X GND D44 6000 4300 100 R 50 50 1 1 W
X GND D45 6000 4400 100 R 50 50 1 1 W
X GND D46 6000 4500 100 R 50 50 1 1 W
X GND D47 6000 4600 100 R 50 50 1 1 W
X GND D48 6000 4700 100 R 50 50 1 1 W
X GND D49 6000 4800 100 R 50 50 1 1 W
X GND D5 6000 400 100 R 50 50 1 1 W
X GND D50 6000 4900 100 R 50 50 1 1 W
X GND D51 6000 5000 100 R 50 50 1 1 W
X GND D52 6000 5100 100 R 50 50 1 1 W
X GND D6 6000 500 100 R 50 50 1 1 W
X GND D7 6000 600 100 R 50 50 1 1 W
X GND D8 6000 700 100 R 50 50 1 1 W
X GND D9 6000 800 100 R 50 50 1 1 W
X UART4_RXD E1 8000 0 100 R 50 50 1 1 I
X NC E10 8000 900 100 R 50 50 1 1 N
X VDD_ARM_0V9 E11 8000 1000 100 R 50 50 1 1 N
X VDD_SNVS_0V9 E12 8000 1100 100 R 50 50 1 1 N
X NVCC_DRAM_1V1 E13 8000 1200 100 R 50 50 1 1 N
X VDD_PHY_1V8 E14 8000 1300 100 R 50 50 1 1 N
X VDD_PHY_0V9 E15 8000 1400 100 R 50 50 1 1 N
X VDD_SOC_0V9 E16 8000 1500 100 R 50 50 1 1 N
X VDD_DRAM_0V9 E17 8000 1600 100 R 50 50 1 1 N
X VDD_GPU_0V9 E18 8000 1700 100 R 50 50 1 1 N
X VBAT E19 8000 1800 100 R 50 50 1 1 W
X UART4_TXD E2 8000 100 100 R 50 50 1 1 O
X VBAT E20 8000 1900 100 R 50 50 1 1 W
X ENET0_RGMII_RXD2 E21 8000 2000 100 R 50 50 1 1 I
X ENET0_RGMII_RXD3 E22 8000 2100 100 R 50 50 1 1 I
X ENET0_RGMII_RXD0 E23 8000 2200 100 R 50 50 1 1 I
X ENET0_RGMII_RXD1 E24 8000 2300 100 R 50 50 1 1 I
X ENET0_RGMII_RX_CTL E25 8000 2400 100 R 50 50 1 1 I
X ENET0_RGMII_RXC E26 8000 2500 100 R 50 50 1 1 I
X ENET0_RGMII_TXD2 E27 8000 2600 100 R 50 50 1 1 O
X ENET0_RGMII_TXD3 E28 8000 2700 100 R 50 50 1 1 O
X ENET0_RGMII_TXD0 E29 8000 2800 100 R 50 50 1 1 O
X UART2_RXD E3 8000 200 100 R 50 50 1 1 I
X ENET0_RGMII_TXD1 E30 8000 2900 100 R 50 50 1 1 O
X ENET0_RGMII_TX_CTL E31 8000 3000 100 R 50 50 1 1 O
X ENET0_RGMII_TXC E32 8000 3100 100 R 50 50 1 1 O
X ENET0_MDC E33 8000 3200 100 R 50 50 1 1 O
X ENET0_MDIO E34 8000 3300 100 R 50 50 1 1 B
X VDD_ETH_1V0 E35 8000 3400 100 R 50 50 1 1 N
X VCC_ENET_2V5 E36 8000 3500 100 R 50 50 1 1 N
X UART2_TXD E4 8000 300 100 R 50 50 1 1 O
X NC E5 8000 400 100 R 50 50 1 1 W
X NC E6 8000 500 100 R 50 50 1 1 W
X VDDA_PHY_3V3 E7 8000 600 100 R 50 50 1 1 N
X VDDA_1V8 E8 8000 700 100 R 50 50 1 1 N
X VDD_VPU_0V9 E9 8000 800 100 R 50 50 1 1 N
X GND F1 10000 0 100 R 50 50 1 1 W
X GND F10 10000 900 100 R 50 50 1 1 W
X GND F11 10000 1000 100 R 50 50 1 1 W
X GND F12 10000 1100 100 R 50 50 1 1 W
X GND F13 10000 1200 100 R 50 50 1 1 W
X GND F14 10000 1300 100 R 50 50 1 1 W
X GND F15 10000 1400 100 R 50 50 1 1 W
X GND F16 10000 1500 100 R 50 50 1 1 W
X GND F17 10000 1600 100 R 50 50 1 1 W
X GND F18 10000 1700 100 R 50 50 1 1 W
X GND F2 10000 100 100 R 50 50 1 1 W
X GND F3 10000 200 100 R 50 50 1 1 W
X GND F4 10000 300 100 R 50 50 1 1 W
X GND F5 10000 400 100 R 50 50 1 1 W
X GND F6 10000 500 100 R 50 50 1 1 W
X GND F7 10000 600 100 R 50 50 1 1 W
X GND F8 10000 700 100 R 50 50 1 1 W
X GND F9 10000 800 100 R 50 50 1 1 W
ENDDRAW
ENDDEF
#
#End Library

+ 10666
- 7355
reform2-motherboard/reform2-motherboard/reform2-motherboard.kicad_pcb
File diff suppressed because it is too large
View File


+ 264
- 901
reform2-motherboard/reform2-motherboard/reform2-motherboard.sch
File diff suppressed because it is too large
View File


+ 0
- 24
reform2-motherboard/reform2-motherboard/reform2-pcie.sch View File

@@ -585,30 +585,6 @@ Wire Wire Line
9400 1800 9750 1800
Connection ~ 9400 1800
$Comp
L Mechanical:MountingHole_Pad H1
U 1 1 610E8506
P 10150 3150
F 0 "H1" H 10250 3199 50 0000 L CNN
F 1 "NGFF-Mount1" H 10250 3108 50 0000 L CNN
F 2 "MountingHole:MountingHole_3.2mm_M3_DIN965_Pad" H 10150 3150 50 0001 C CNN
F 3 "~" H 10150 3150 50 0001 C CNN
1 10150 3150
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0179
U 1 1 610E8EF7
P 10150 3400
F 0 "#PWR0179" H 10150 3150 50 0001 C CNN
F 1 "GND" H 10155 3227 50 0000 C CNN
F 2 "" H 10150 3400 50 0001 C CNN
F 3 "" H 10150 3400 50 0001 C CNN
1 10150 3400
1 0 0 -1
$EndComp
Wire Wire Line
10150 3400 10150 3250
$Comp
L reform2:48099-5701 J11
U 1 1 610F1B47
P 3550 6350


+ 2
- 2
reform2-motherboard/reform2-motherboard/reform2-power.sch View File

@@ -3997,7 +3997,7 @@ U 1 1 5D579C32
P 14450 3350
F 0 "U19" H 14450 3592 50 0000 C CNN
F 1 "TLV1117-15" H 14450 3501 50 0000 C CNN
F 2 "" H 14450 3350 50 0001 C CNN
F 2 "Package_TO_SOT_SMD:SOT-223" H 14450 3350 50 0001 C CNN
F 3 "http://www.ti.com/lit/ds/symlink/tlv1117.pdf" H 14450 3350 50 0001 C CNN
F 4 "Texas Instruments" H 14450 3350 50 0001 C CNN "Manufacturer"
F 5 "TLV1117-15" H 14450 3350 50 0001 C CNN "Manufacturer_No"
@@ -4175,7 +4175,7 @@ U 1 1 5EB4B7BD
P 14500 4300
F 0 "U17" H 14500 4542 50 0000 C CNN
F 1 "TLV1117-18" H 14500 4451 50 0000 C CNN
F 2 "" H 14500 4300 50 0001 C CNN
F 2 "Package_TO_SOT_SMD:SOT-223" H 14500 4300 50 0001 C CNN
F 3 "http://www.ti.com/lit/ds/symlink/tlv1117.pdf" H 14500 4300 50 0001 C CNN
F 4 "Texas Instruments" H 14500 4300 50 0001 C CNN "Manufacturer"
F 5 "TLV1117-18" H 14500 4300 50 0001 C CNN "Manufacturer_No"


+ 2
- 8
reform2-motherboard/reform2-motherboard/reform2-usb.sch View File

@@ -2362,14 +2362,6 @@ Wire Wire Line
11300 1750 11450 1750
Connection ~ 11450 1750
Wire Wire Line
11300 2300 11300 1950
Wire Wire Line
11300 1950 11450 1950
Connection ~ 11300 1950
Wire Wire Line
11300 1950 11300 1750
Connection ~ 11450 1950
Wire Wire Line
11450 1950 11850 1950
Connection ~ 11850 1950
Wire Wire Line
@@ -2394,4 +2386,6 @@ $EndComp
Wire Wire Line
13050 2000 13050 1950
Connection ~ 13050 1950
Wire Wire Line
11300 1750 11300 2300
$EndSCHEMATC

+ 216
- 0
reform2-motherboard/reform2-motherboard/reform2.lib View File

@@ -243,6 +243,222 @@ X 4 4 200 50 100 L 40 40 0 0 P
ENDDRAW
ENDDEF
#
# CL-SOM-iMX8
#
DEF CL-SOM-iMX8 U 0 40 Y Y 1 F N
F0 "U" -50 5050 50 H V C CNN
F1 "CL-SOM-iMX8" 0 4950 50 H V C CNN
F2 "footprints:TE_2-2013289-1" -350 2700 50 H I C CNN
F3 "" -350 2700 50 H I C CNN
DRAW
S -850 4850 700 -5450 0 1 0 f
X GND 1 -950 4750 100 R 50 50 1 1 W
X VSYS 10 800 4350 100 L 50 50 1 1 O
X QSPI_A_SS1_B 100 800 -150 100 L 50 50 1 1 O
X CSI_P1_DP2 101 -950 -150 100 R 50 50 1 1 O
X QSPI_A_DQS 102 800 -250 100 L 50 50 1 1 O
X CSI_P1_DN2 103 -950 -250 100 R 50 50 1 1 O
X QSPI_A_SCLK 104 800 -350 100 L 50 50 1 1 O
X GND 105 -950 -350 100 R 50 50 1 1 O
X SAI1_RX_SYNC 106 800 -450 100 L 50 50 1 1 O
X CSI_P1_CKP 107 -950 -450 100 R 50 50 1 1 O
X SAI1_MCLK 108 800 -550 100 L 50 50 1 1 O
X CSI_P1_CKN 109 -950 -550 100 R 50 50 1 1 O
X ECSPI1_MOSI 11 -950 4250 100 R 50 50 1 1 W
X SAI1_TX_SYNC 110 800 -650 100 L 50 50 1 1 O
X UART3_TX 111 -950 -650 100 R 50 50 1 1 O
X SAI1_TX_BCLK 112 800 -750 100 L 50 50 1 1 O
X CSI_P1_DN3 113 -950 -750 100 R 50 50 1 1 O
X VSYS 114 800 -850 100 L 50 50 1 1 O
X CSI_P1_DP3 115 -950 -850 100 R 50 50 1 1 O
X SAI1_TX_DATA[0] 116 800 -950 100 L 50 50 1 1 O
X UART3_RX 117 -950 -950 100 R 50 50 1 1 O
X SAI1_TX_DATA[1] 118 800 -1050 100 L 50 50 1 1 O
X PCIE1_REF_CLKP 119 -950 -1050 100 R 50 50 1 1 O
X ETH1_MDI1N 12 800 4250 100 L 50 50 1 1 O
X SAI1_TX_DATA[2] 120 800 -1150 100 L 50 50 1 1 O
X PCIE1_REF_CLKN 121 -950 -1150 100 R 50 50 1 1 O
X SAI1_TX_DATA[3] 122 800 -1250 100 L 50 50 1 1 O
X GND 123 -950 -1250 100 R 50 50 1 1 O
X GPIO3_IO[16] 124 800 -1350 100 L 50 50 1 1 O
X PCIE1_TXN_P 125 -950 -1350 100 R 50 50 1 1 O
X SAI1_TX_DATA[3] 126 800 -1450 100 L 50 50 1 1 O
X PCIE1_TXN_N 127 -950 -1450 100 R 50 50 1 1 O
X SAI1_TX_DATA[4] 128 800 -1550 100 L 50 50 1 1 O
X ENET1_MDC 129 -950 -1550 100 R 50 50 1 1 O
X ECSPI1_SCLK 13 -950 4150 100 R 50 50 1 1 W
X SAI1_TX_DATA[7] 130 800 -1650 100 L 50 50 1 1 O
X PCIE1_RXN_P 131 -950 -1650 100 R 50 50 1 1 O
X VSYS 132 800 -1750 100 L 50 50 1 1 O
X PCIE1_RXN_N 133 -950 -1750 100 R 50 50 1 1 O
X SAI1_RX_DATA[0] 134 800 -1850 100 L 50 50 1 1 O
X ENET1_MDIO 135 -950 -1850 100 R 50 50 1 1 O
X SAI1_RX_DATA[1] 136 800 -1950 100 L 50 50 1 1 O
X SAI1_RX_DATA[4] 137 -950 -1950 100 R 50 50 1 1 O
X SAI1_RX_DATA[2] 138 800 -2050 100 L 50 50 1 1 O
X SAI1_RX_DATA[5] 139 -950 -2050 100 R 50 50 1 1 O
X SAI1_TX_DATA[5] 139 -950 -2250 100 R 50 50 1 1 O
X ETH1_MDI1P 14 800 4150 100 L 50 50 1 1 O
X SAI1_RX_DATA[3] 140 800 -2150 100 L 50 50 1 1 O
X GND 141 -950 -2350 100 R 50 50 1 1 O
X GND 141 -950 -2150 100 R 50 50 1 1 O
X SAI1_TX_BCLK 142 800 -2250 100 L 50 50 1 1 O
X SAI1_TX_DATA[5] 143 -950 -2450 100 R 50 50 1 1 O
X SAI1_TX_DATA[0] 144 800 -2350 100 L 50 50 1 1 O
X SAI1_RX_DATA[6] 145 -950 -2550 100 R 50 50 1 1 O
X SAI1_TX_DATA[1] 146 800 -2450 100 L 50 50 1 1 O
X QSPI_B_SCLK 147 -950 -2650 100 R 50 50 1 1 O
X SAI1_TX_DATA[2] 148 800 -2550 100 L 50 50 1 1 O
X QSPI_B_DATA[3] 149 -950 -2750 100 R 50 50 1 1 O
X ECSPI1_MISO 15 -950 4050 100 R 50 50 1 1 W
X VSYS 150 800 -2650 100 L 50 50 1 1 O
X QSPI_B_DATA[2] 151 -950 -2850 100 R 50 50 1 1 O
X SAI1_RX_DATA[7] 152 800 -2750 100 L 50 50 1 1 O
X QSPI_B_DATA[1] 153 -950 -2950 100 R 50 50 1 1 O
X USDHC2_RESET_B 154 800 -2850 100 L 50 50 1 1 O
X QSPI_B_DATA[0] 155 -950 -3050 100 R 50 50 1 1 O
X USB2_VBUS_DET 156 800 -2950 100 L 50 50 1 1 O
X QSPI_B_DQS 157 -950 -3150 100 R 50 50 1 1 O
X USB2_RX_P 158 800 -3050 100 L 50 50 1 1 O
X GND 159 -950 -3250 100 R 50 50 1 1 O
X ETH1_LED1_SPD 16 800 4050 100 L 50 50 1 1 O
X USB2_RX_N 160 800 -3150 100 L 50 50 1 1 O
X LVDS1_TX3_P 161 -950 -3350 100 R 50 50 1 1 O
X SAI1_TX_DATA[6] 162 800 -3250 100 L 50 50 1 1 O
X LVDS1_TX3_N 163 -950 -3450 100 R 50 50 1 1 O
X USB2_TX_P 164 800 -3350 100 L 50 50 1 1 O
X ONOFF 165 -950 -3550 100 R 50 50 1 1 O
X USB2_TX_N 166 800 -3450 100 L 50 50 1 1 O
X PCIE2_RXN_N 167 -950 -3650 100 R 50 50 1 1 O
X VSYS 168 800 -3550 100 L 50 50 1 1 O
X PCIE2_RXN_P 169 -950 -3750 100 R 50 50 1 1 O
X ECSPI1_SS0 17 -950 3950 100 R 50 50 1 1 W
X USB2_DN 170 800 -3650 100 L 50 50 1 1 O
X COLD_RESET_IN 171 -950 -3850 100 R 50 50 1 1 O
X USB2_DP 172 800 -3750 100 L 50 50 1 1 O
X PCIE2_TXN_N 173 -950 -3950 100 R 50 50 1 1 O
X USB1_ID 174 800 -3850 100 L 50 50 1 1 O
X PCIE2_TXN_P 175 -950 -4050 100 R 50 50 1 1 O
X USB1_DP 176 800 -3950 100 L 50 50 1 1 O
X GND 177 -950 -4150 100 R 50 50 1 1 O
X USB1_DN 178 800 -4050 100 L 50 50 1 1 O
X PCIE2_REF_CLKN 179 -950 -4250 100 R 50 50 1 1 O
X ETH1_MDI2N 18 800 3950 100 L 50 50 1 1 O
X USB1_VBUS_DET 180 800 -4150 100 L 50 50 1 1 O
X PCIE2_REF_CLKP 181 -950 -4350 100 R 50 50 1 1 O
X USB1_RX_P 182 800 -4250 100 L 50 50 1 1 O
X VCC_RTC 183 -950 -4450 100 R 50 50 1 1 O
X USB1_RX_N 184 800 -4350 100 L 50 50 1 1 O
X ALT_BOOT 185 -950 -4550 100 R 50 50 1 1 O
X VSYS 186 800 -4450 100 L 50 50 1 1 O
X NC 187 -950 -4650 100 R 50 50 1 1 O
X USB1_TX_P 188 800 -4550 100 L 50 50 1 1 O
X EEPROM_WP 189 -950 -4750 100 R 50 50 1 1 O
X GND 19 -950 3850 100 R 50 50 1 1 W
X USB1_TX_N 190 800 -4650 100 L 50 50 1 1 O
X MICBIAS 191 -950 -4850 100 R 50 50 1 1 O
X SAI1_RX_BCLK 192 800 -4750 100 L 50 50 1 1 O
X MICIN 193 -950 -4950 100 R 50 50 1 1 O
X SAI1_TX_DATA[4] 194 800 -4850 100 L 50 50 1 1 O
X AUD_GND 195 -950 -5050 100 R 50 50 1 1 O
X PWM3_OUT 196 800 -4950 100 L 50 50 1 1 O
X SAI2_TX_BCLK 197 -950 -5150 100 R 50 50 1 1 O
X PWM2_OUT 198 800 -5050 100 L 50 50 1 1 O
X AVDD33_ETH 2 800 4750 100 L 50 50 1 1 O
X ETH1_MDI2P 20 800 3850 100 L 50 50 1 1 O
X PWM1_OUT 200 800 -5150 100 L 50 50 1 1 O
X SAI2_TX_SYNC 201 -950 -5250 100 R 50 50 1 1 O
X PMIC_ON_REQ 202 800 -5250 100 L 50 50 1 1 O
X SAI2_RX_DATA[0] 203 -950 -5350 100 R 50 50 1 1 O
X VSYS 204 800 -5350 100 L 50 50 1 1 O
X LVDS1_TX0_P 21 -950 3750 100 R 50 50 1 1 O
X ETH1_LED3 22 800 3750 100 L 50 50 1 1 O
X LVDS1_TX0_N 23 -950 3650 100 R 50 50 1 1 O
X ETH1_MDI3N 24 800 3650 100 L 50 50 1 1 O
X HDMI_DDC_SCL 25 -950 3550 100 R 50 50 1 1 O
X ETH1_MDI3P 26 800 3550 100 L 50 50 1 1 O
X HDMI_AUXN 27 -950 3450 100 R 50 50 1 1 O
X VSYS 28 800 3450 100 L 50 50 1 1 O
X HDMI_AUXP 29 -950 3350 100 R 50 50 1 1 O
X PCIE2_CLKREQ_B 3 -950 4650 100 R 50 50 1 1 W
X HDMI_CLKP 30 800 3350 100 L 50 50 1 1 O
X HDMI_DDC_SDA 31 -950 3250 100 R 50 50 1 1 O
X HDMI_CLKN 32 800 3250 100 L 50 50 1 1 O
X DSI_DP2 33 -950 3150 100 R 50 50 1 1 O
X HDMI_CEC 34 800 3150 100 L 50 50 1 1 O
X DSI_DN2 35 -950 3050 100 R 50 50 1 1 O
X HDMI_TXP0 36 800 3050 100 L 50 50 1 1 O
X GND 37 -950 2950 100 R 50 50 1 1 O
X HDMI_TXN0 38 800 2950 100 L 50 50 1 1 O
X DSI_DP0 39 -950 2850 100 R 50 50 1 1 O
X ETH1_LED_ACT 4 800 4650 100 L 50 50 1 1 O
X HDMI_HPD 40 800 2850 100 L 50 50 1 1 O
X DSI_DN0 41 -950 2750 100 R 50 50 1 1 O
X HDMI_TXP1 42 800 2750 100 L 50 50 1 1 O
X I2C3_SCL 43 -950 2650 100 R 50 50 1 1 O
X HDMI_TXN1 44 800 2650 100 L 50 50 1 1 O
X DSI_DP1 45 -950 2550 100 R 50 50 1 1 O
X VSYS 46 800 2550 100 L 50 50 1 1 O
X DSI_DN1 47 -950 2450 100 R 50 50 1 1 O
X HDMI_TXP2 48 800 2450 100 L 50 50 1 1 O
X I2C3_SDA 49 -950 2350 100 R 50 50 1 1 O
X PCIE1_CLKREQ_B 5 -950 4550 100 R 50 50 1 1 W
X HDMI_TXN2 50 800 2350 100 L 50 50 1 1 O
X DSI_DP3 51 -950 2250 100 R 50 50 1 1 O
X ENET1_MDC 52 800 2250 100 L 50 50 1 1 O
X DSI_DN3 53 -950 2150 100 R 50 50 1 1 O
X JTAG_MOD 54 800 2150 100 L 50 50 1 1 O
X GND 55 -950 2050 100 R 50 50 1 1 O
X JTAG_NTRST 56 800 2050 100 L 50 50 1 1 O
X DSI_CKN 57 -950 1950 100 R 50 50 1 1 O
X UART2_TX 58 800 1950 100 L 50 50 1 1 O
X DSI_CKP 59 -950 1850 100 R 50 50 1 1 O
X ETH1_MDI0N 6 800 4550 100 L 50 50 1 1 O
X GPIO3_IO[17] 60 800 1850 100 L 50 50 1 1 O
X USDHC2_CD_B 61 -950 1750 100 R 50 50 1 1 O
X GPIO1_IO[19] 62 800 1750 100 L 50 50 1 1 O
X VSYS 64 800 1650 100 L 50 50 1 1 O
X ECSPI3_MISO 65 -950 1650 100 R 50 50 1 1 O
X JTAG_TCK 66 800 1550 100 L 50 50 1 1 O
X USDHC2_WP 67 -950 1550 100 R 50 50 1 1 O
X JTAG_TMS 68 800 1450 100 L 50 50 1 1 O
X ECSPI3_SCLK 69 -950 1450 100 R 50 50 1 1 O
X QSPI_BSS0_B 7 -950 4450 100 R 50 50 1 1 W
X JTAG_TDI 70 800 1350 100 L 50 50 1 1 O
X GND 71 -950 1350 100 R 50 50 1 1 O
X JTAG_TDO 72 800 1250 100 L 50 50 1 1 O
X PCIE1_CLKREQ_B 73 -950 1250 100 R 50 50 1 1 O
X QSPI_A_DATA[0] 74 800 1150 100 L 50 50 1 1 O
X PCIE2_CLKREQ_B 75 -950 1150 100 R 50 50 1 1 O
X QSPI_A_DATA[1] 76 800 1050 100 L 50 50 1 1 O
X LVDS1_CLK_P 77 -950 1050 100 R 50 50 1 1 O
X VSYS 78 800 950 100 L 50 50 1 1 O
X LVDS1_CLK_N 79 -950 950 100 R 50 50 1 1 O
X ETH1_MDI0P 8 800 4450 100 L 50 50 1 1 O
X USDHC2_CLK 80 800 850 100 L 50 50 1 1 O
X GPIO3_IO[18] 81 -950 850 100 R 50 50 1 1 O
X USDHC2_CMD 82 800 750 100 L 50 50 1 1 O
X CSI_P1_DP0 83 -950 750 100 R 50 50 1 1 O
X USDHC2_DATA0 84 800 650 100 L 50 50 1 1 O
X CSI_P1_DN0 85 -950 650 100 R 50 50 1 1 O
X USDHC2_DATA1 86 800 550 100 L 50 50 1 1 O
X GND 87 -950 550 100 R 50 50 1 1 O
X USDHC2_DATA2 88 800 450 100 L 50 50 1 1 O
X CSI_P1_DP1 89 -950 450 100 R 50 50 1 1 O
X QSPI_B_SS1_B 9 -950 4350 100 R 50 50 1 1 W
X USDHC2_DATA3 90 800 350 100 L 50 50 1 1 O
X CSI_P1_DN1 91 -950 350 100 R 50 50 1 1 O
X QSPI_A_DATA[2] 92 800 250 100 L 50 50 1 1 O
X LVDS1_TX1_P 93 -950 250 100 R 50 50 1 1 O
X QSPI_A_DATA[3] 94 800 150 100 L 50 50 1 1 O
X LVDS1_TX1_N 95 -950 150 100 R 50 50 1 1 O
X VSYS 96 800 50 100 L 50 50 1 1 O
X LVDS1_TX2_P 97 -950 50 100 R 50 50 1 1 O
X QSPI_A_SS0_B 98 800 -50 100 L 50 50 1 1 O
X LVDS1_TX2_N 99 -950 -50 100 R 50 50 1 1 O
ENDDRAW
ENDDEF
#
# CM2020-00TR
#
DEF CM2020-00TR U? 0 40 Y Y 1 F N


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