Browse Source

WIP: reform2 motherboard: more sanity and footprint checks, passives

reform2
mntmn 1 year ago
parent
commit
3c689cd509
10 changed files with 1705 additions and 1035 deletions
  1. +737
    -486
      reform2-motherboard/reform2-motherboard/reform2-display.sch
  2. +2
    -2
      reform2-motherboard/reform2-motherboard/reform2-eth.sch
  3. +3
    -3
      reform2-motherboard/reform2-motherboard/reform2-hdmi.sch
  4. +104
    -35
      reform2-motherboard/reform2-motherboard/reform2-motherboard-cache.lib
  5. +38
    -2
      reform2-motherboard/reform2-motherboard/reform2-motherboard.sch
  6. +30
    -32
      reform2-motherboard/reform2-motherboard/reform2-pcie.sch
  7. +528
    -298
      reform2-motherboard/reform2-motherboard/reform2-power.sch
  8. +61
    -15
      reform2-motherboard/reform2-motherboard/reform2-sd.sch
  9. +162
    -162
      reform2-motherboard/reform2-motherboard/reform2-usb.sch
  10. +40
    -0
      reform2-motherboard/reform2-motherboard/reform2.lib

+ 737
- 486
reform2-motherboard/reform2-motherboard/reform2-display.sch
File diff suppressed because it is too large
View File


+ 2
- 2
reform2-motherboard/reform2-motherboard/reform2-eth.sch View File

@@ -6,12 +6,12 @@ $Descr A4 11693 8268
encoding utf-8
Sheet 4 9
Title "MNT Reform 2 Ethernet"
Date "2019-06-21"
Date "2019-07-03"
Rev "0.1"
Comp "MNT Research GmbH"
Comment1 "https://mntre.com"
Comment2 "Engineer: Lukas F. Hartmann"
Comment3 ""
Comment3 "License: GPL v3+"
Comment4 ""
$EndDescr
$Comp


+ 3
- 3
reform2-motherboard/reform2-motherboard/reform2-hdmi.sch View File

@@ -6,12 +6,12 @@ $Descr A4 11693 8268
encoding utf-8
Sheet 8 9
Title "MNT Reform 2 External Display"
Date "2019-06-21"
Date "2019-07-03"
Rev "0.1"
Comp "MNT Research GmbH"
Comment1 "https://mntre.com"
Comment2 "Engineer: Lukas F. Hartmann"
Comment3 ""
Comment3 "License: GPL v3+"
Comment4 ""
$EndDescr
$Comp
@@ -293,7 +293,7 @@ L Device:C_Small C30
U 1 1 5D14719E
P 7400 1400
F 0 "C30" H 7492 1446 50 0000 L CNN
F 1 "C_Small" H 7492 1355 50 0000 L CNN
F 1 "0.1uF" H 7492 1355 50 0000 L CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 7400 1400 50 0001 C CNN
F 3 "~" H 7400 1400 50 0001 C CNN
1 7400 1400


+ 104
- 35
reform2-motherboard/reform2-motherboard/reform2-motherboard-cache.lib View File

@@ -1,46 +1,35 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Audio_TLV320AIC23BPW
# Amplifier_Audio_MAX9715ETE+
#
DEF Audio_TLV320AIC23BPW U 0 20 Y Y 1 F N
F0 "U" 650 1050 50 H V C CNN
F1 "Audio_TLV320AIC23BPW" 650 950 50 H V C CNN
F2 "Package_SO:TSSOP-28_4.4x9.7mm_P0.65mm" 0 0 50 H I C CIN
DEF Amplifier_Audio_MAX9715ETE+ U 0 20 Y Y 1 F N
F0 "U" -300 450 50 H V C CNN
F1 "Amplifier_Audio_MAX9715ETE+" 350 450 50 H V C CNN
F2 "Package_DFN_QFN:TQFN-16-1EP_5x5mm_P0.8mm_EP3.1x3.1mm" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
TSSOP*4.4x9.7mm*P0.65mm*
TQFN*1EP*5x5mm*P0.8mm*
$ENDFPLIST
DRAW
S -700 900 700 -900 0 1 10 f
X BVDD 1 -300 1000 100 D 50 50 1 1 W
X RHPOUT 10 800 300 100 L 50 50 1 1 P
X HPGND 11 300 -1000 100 U 50 50 1 1 W
X LOUT 12 800 700 100 L 50 50 1 1 P
X ROUT 13 800 600 100 L 50 50 1 1 P
X AVDD 14 100 1000 100 D 50 50 1 1 W
X AGND 15 100 -1000 100 U 50 50 1 1 W
X VMID 16 800 -600 100 L 50 50 1 1 P
X MICBIAS 17 800 -200 100 L 50 50 1 1 P
X MICIN 18 800 -400 100 L 50 50 1 1 P
X RLINEIN 19 800 0 100 L 50 50 1 1 P
X CLKOUT 2 -800 -700 100 R 50 50 1 1 O
X LLINEIN 20 800 100 100 L 50 50 1 1 P
X ~CS~ 21 -800 400 100 R 50 50 1 1 I
X MODE 22 -800 500 100 R 50 50 1 1 I
X SDIN 23 -800 700 100 R 50 50 1 1 I
X SCLK 24 -800 600 100 R 50 50 1 1 I
X XTI/MCK 25 -800 -500 100 R 50 50 1 1 P
X XTO 26 -800 -600 100 R 50 50 1 1 P
X DVDD 27 -100 1000 100 D 50 50 1 1 W
X DGND 28 -100 -1000 100 U 50 50 1 1 W
X BCLK 3 -800 0 100 R 50 50 1 1 B
X DIN 4 -800 200 100 R 50 50 1 1 I
X LRCIN 5 -800 100 100 R 50 50 1 1 I
X DOUT 6 -800 -200 100 R 50 50 1 1 O
X LRCOUT 7 -800 -300 100 R 50 50 1 1 O
X HPVDD 8 300 1000 100 D 50 50 1 1 W
X LHPOUT 9 800 400 100 L 50 50 1 1 P
S -400 400 400 -400 0 1 10 f
X PGND 1 0 -500 100 U 50 50 1 1 W
X OUTR- 10 500 -200 100 L 50 50 1 1 O
X OUTR+ 11 500 -100 100 L 50 50 1 1 O
X PGND 12 0 -500 100 U 50 50 1 1 P N
X BIAS 13 -500 -300 100 R 50 50 1 1 P
X VDD 14 -100 500 100 D 50 50 1 1 W
X INR 15 -500 200 100 R 50 50 1 1 I
X INL 16 -500 300 100 R 50 50 1 1 I
X PAD 17 100 -500 100 U 50 50 1 1 P
X OUTL+ 2 500 200 100 L 50 50 1 1 O
X OUTL- 3 500 100 100 L 50 50 1 1 O
X PVDD 4 0 500 100 D 50 50 1 1 W
X NC 5 500 0 100 L 50 50 1 1 N N
X GAIN 6 -500 0 100 R 50 50 1 1 I
X GND 7 -100 -500 100 U 50 50 1 1 W
X ~SHDN 8 -500 -100 100 R 50 50 1 1 I
X PVDD 9 0 500 100 D 50 50 1 1 P N
ENDDRAW
ENDDEF
#
@@ -522,6 +511,25 @@ X ~ 2 0 -100 80 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_Crystal_Small
#
DEF Device_Crystal_Small Y 0 40 N N 1 F N
F0 "Y" 0 100 50 H V C CNN
F1 "Device_Crystal_Small" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Crystal*
$ENDFPLIST
DRAW
S -30 -60 30 60 0 1 0 N
P 2 0 1 15 -50 -30 -50 30 N
P 2 0 1 15 50 -30 50 30 N
X 1 1 -100 0 50 R 50 50 1 1 P
X 2 2 100 0 50 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_D_Schottky_Small_ALT
#
DEF Device_D_Schottky_Small_ALT D 0 10 N N 1 F N
@@ -968,6 +976,27 @@ F0 "U" -150 125 50 H V C CNN
F1 "Regulator_Linear_TLV1117-15" 0 125 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
SOT?223*
TO?263*
TO?252*
TO?220*
$ENDFPLIST
DRAW
S -200 -200 200 75 0 1 10 f
X GND 1 0 -300 100 U 50 50 1 1 W
X VO 2 300 0 100 L 50 50 1 1 w
X VI 3 -300 0 100 R 50 50 1 1 W
ENDDRAW
ENDDEF
#
# Regulator_Linear_TLV1117-18
#
DEF Regulator_Linear_TLV1117-18 U 0 10 Y Y 1 F N
F0 "U" -150 125 50 H V C CNN
F1 "Regulator_Linear_TLV1117-18" 0 125 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS LM1117-2.5 LM1117-3.3 LM1117-5.0 TLV1117-15 TLV1117-18 TLV1117-25 TLV1117-33 TLV1117-50
$FPLIST
SOT?223*
@@ -2275,6 +2304,46 @@ X DBCN 9 -700 -400 100 R 40 40 0 0 I
ENDDRAW
ENDDEF
#
# reform2_WM8731
#
DEF reform2_WM8731 U 0 40 Y Y 1 F N
F0 "U" -50 1450 50 H V C CNN
F1 "reform2_WM8731" 0 1300 50 H V C CNN
F2 "" -50 1450 50 H I C CNN
F3 "" -50 1450 50 H I C CNN
DRAW
S -450 1250 450 -1900 0 1 6 f
X DBVDD 1 -550 1100 100 R 50 50 1 1 W
X RHPOUT 10 550 -300 100 L 50 50 1 1 O
X HPGND 11 550 -1800 100 L 50 50 1 1 P
X LOUT 12 550 700 100 L 50 50 1 1 O
X ROUT 13 550 500 100 L 50 50 1 1 O
X AVDD 14 -550 -1550 100 R 50 50 1 1 W
X AGND 15 -550 -1800 100 R 50 50 1 1 W
X VMID 16 550 -1000 100 L 50 50 1 1 w
X MICBIAS 17 550 150 100 L 50 50 1 1 P
X MICIN 18 550 -100 100 L 50 50 1 1 I
X RLINEIN 19 550 900 100 L 50 50 1 1 I
X CLKOUT 2 550 -1200 100 L 50 50 1 1 O
X LLINEIN 20 550 1100 100 L 50 50 1 1 I
X MODE 21 -550 -1250 100 R 50 50 1 1 I
X CSB 22 -550 -1150 100 R 50 50 1 1 I
X SDIN 23 -550 -1050 100 R 50 50 1 1 I
X SCLK 24 -550 -950 100 R 50 50 1 1 I
X XTI/MCLK 25 -550 -650 100 R 50 50 1 1 I
X XTO 26 -550 -450 100 R 50 50 1 1 O
X DCVDD 27 -550 600 100 R 50 50 1 1 W
X DGND 28 -550 850 100 R 50 50 1 1 W
X BCLK 3 -550 -150 100 R 50 50 1 1 I C
X DACDAT 4 -550 250 100 R 50 50 1 1 I
X DACLRC 5 -550 150 100 R 50 50 1 1 I
X ADCDAT 6 -550 50 100 R 50 50 1 1 O
X ADCLRC 7 -550 -50 100 R 50 50 1 1 I
X HPVDD 8 550 -1550 100 L 50 50 1 1 W
X LHPOUT 9 550 -600 100 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# reform2_phycore-imx8m-alpha
#
DEF reform2_phycore-imx8m-alpha U 0 40 Y Y 1 F N


+ 38
- 2
reform2-motherboard/reform2-motherboard/reform2-motherboard.sch View File

@@ -6,12 +6,12 @@ $Descr A2 23386 16535
encoding utf-8
Sheet 1 9
Title "MNT Reform 2"
Date "2019-06-21"
Date "2019-07-03"
Rev "0.1"
Comp "MNT Research GmbH"
Comment1 "https://mntre.com"
Comment2 "Engineer: Lukas F. Hartmann"
Comment3 ""
Comment3 "License: GPL v3+"
Comment4 ""
$EndDescr
$Comp
@@ -847,4 +847,40 @@ F 3 "" H 18750 8900 50 0001 C CNN
1 18750 8900
1 0 0 -1
$EndComp
Text GLabel 6400 6500 0 50 Output ~ 0
BACKLIGHT_EN
Text GLabel 6400 6800 0 50 Output ~ 0
BACKLIGHT_PWM
Wire Wire Line
6400 6800 6500 6800
Wire Wire Line
6400 6500 6500 6500
Text GLabel 6450 12300 0 50 Output ~ 0
DAC_TXFS
Text GLabel 6450 12400 0 50 Output ~ 0
DAC_DOUT
Text GLabel 6450 12500 0 50 Input ~ 0
DAC_DIN
Text GLabel 6450 12200 0 50 Output ~ 0
DAC_BCLK
Wire Wire Line
6450 12500 6500 12500
Wire Wire Line
6450 12400 6500 12400
Wire Wire Line
6450 12300 6500 12300
Text GLabel 6450 12600 0 50 Output ~ 0
DAC_RXFS
Wire Wire Line
6450 12600 6500 12600
Wire Wire Line
6450 12200 6500 12200
Text GLabel 6450 12100 0 50 Output ~ 0
DAC_MCLK
Wire Wire Line
6450 12100 6500 12100
Text GLabel 6450 12700 0 50 Output ~ 0
DAC_RXCLK
Wire Wire Line
6450 12700 6500 12700
$EndSCHEMATC

+ 30
- 32
reform2-motherboard/reform2-motherboard/reform2-pcie.sch View File

@@ -6,12 +6,12 @@ $Descr A4 11693 8268
encoding utf-8
Sheet 6 9
Title "MNT Reform 2 PCIe"
Date "2019-06-21"
Date "2019-07-03"
Rev "0.1"
Comp "MNT Research GmbH"
Comment1 "https://mntre.com"
Comment2 "Engineer: Lukas F. Hartmann"
Comment3 ""
Comment3 "License: GPL v3+"
Comment4 ""
$EndDescr
$Comp
@@ -376,8 +376,6 @@ F 3 "" H 4000 2150 50 0001 C CNN
1 0 0 -1
$EndComp
Connection ~ 4000 2150
Text Notes 3200 1500 0 50 ~ 0
TODO: 1.5V?
Text Notes 8200 1200 0 50 ~ 0
1-2199230-5
Text Notes 8200 1300 0 50 ~ 0
@@ -714,10 +712,10 @@ Wire Wire Line
9000 3150 9750 3150
Connection ~ 9750 3150
$Comp
L Device:LED_Small D?
L Device:LED_Small D23
U 1 1 5D21DAF3
P 9250 2750
F 0 "D?" H 9250 2985 50 0000 C CNN
F 0 "D23" H 9250 2985 50 0000 C CNN
F 1 "LED_NVME" H 9250 2894 50 0000 C CNN
F 2 "LED_SMD:LED_0603_1608Metric" V 9250 2750 50 0001 C CNN
F 3 "~" V 9250 2750 50 0001 C CNN
@@ -727,10 +725,10 @@ $EndComp
Wire Wire Line
9150 2750 9000 2750
$Comp
L Device:R_Small R?
L Device:R_Small R110
U 1 1 5D21DAFE
P 9550 2750
F 0 "R?" V 9354 2750 50 0000 C CNN
F 0 "R110" V 9354 2750 50 0000 C CNN
F 1 "240" V 9445 2750 50 0000 C CNN
F 2 "Resistor_SMD:R_0603_1608Metric" H 9550 2750 50 0001 C CNN
F 3 "~" H 9550 2750 50 0001 C CNN
@@ -852,10 +850,10 @@ Wire Wire Line
NoConn ~ 8200 2550
NoConn ~ 8200 2650
$Comp
L Device:R_Small R?
L Device:R_Small R107
U 1 1 5D2DBE2E
P 7700 2850
F 0 "R?" V 7600 2850 50 0000 C CNN
F 0 "R107" V 7600 2850 50 0000 C CNN
F 1 "0" V 7700 2850 50 0000 C CNN
F 2 "" H 7700 2850 50 0001 C CNN
F 3 "~" H 7700 2850 50 0001 C CNN
@@ -863,10 +861,10 @@ F 3 "~" H 7700 2850 50 0001 C CNN
0 1 1 0
$EndComp
$Comp
L Device:R_Small R?
L Device:R_Small R104
U 1 1 5D2DCFF0
P 7450 2950
F 0 "R?" V 7350 2950 50 0000 C CNN
F 0 "R104" V 7350 2950 50 0000 C CNN
F 1 "0" V 7450 2950 50 0000 C CNN
F 2 "" H 7450 2950 50 0001 C CNN
F 3 "~" H 7450 2950 50 0001 C CNN
@@ -888,10 +886,10 @@ Wire Wire Line
Wire Wire Line
8200 2850 7800 2850
$Comp
L Device:R_Small R?
L Device:R_Small R108
U 1 1 5D2F70BD
P 7700 3450
F 0 "R?" V 7600 3450 50 0000 C CNN
F 0 "R108" V 7600 3450 50 0000 C CNN
F 1 "0" V 7700 3450 50 0000 C CNN
F 2 "" H 7700 3450 50 0001 C CNN
F 3 "~" H 7700 3450 50 0001 C CNN
@@ -899,10 +897,10 @@ F 3 "~" H 7700 3450 50 0001 C CNN
0 1 1 0
$EndComp
$Comp
L Device:R_Small R?
L Device:R_Small R105
U 1 1 5D2F70C7
P 7450 3550
F 0 "R?" V 7350 3550 50 0000 C CNN
F 0 "R105" V 7350 3550 50 0000 C CNN
F 1 "0" V 7450 3550 50 0000 C CNN
F 2 "" H 7450 3550 50 0001 C CNN
F 3 "~" H 7450 3550 50 0001 C CNN
@@ -924,10 +922,10 @@ Connection ~ 7300 3550
Wire Wire Line
7300 3550 7300 3650
$Comp
L Device:R_Small R?
L Device:R_Small R109
U 1 1 5D304129
P 7700 4050
F 0 "R?" V 7600 4050 50 0000 C CNN
F 0 "R109" V 7600 4050 50 0000 C CNN
F 1 "0" V 7700 4050 50 0000 C CNN
F 2 "" H 7700 4050 50 0001 C CNN
F 3 "~" H 7700 4050 50 0001 C CNN
@@ -935,10 +933,10 @@ F 3 "~" H 7700 4050 50 0001 C CNN
0 1 1 0
$EndComp
$Comp
L Device:R_Small R?
L Device:R_Small R106
U 1 1 5D304133
P 7450 4150
F 0 "R?" V 7350 4150 50 0000 C CNN
F 0 "R106" V 7350 4150 50 0000 C CNN
F 1 "0" V 7450 4150 50 0000 C CNN
F 2 "" H 7450 4150 50 0001 C CNN
F 3 "~" H 7450 4150 50 0001 C CNN
@@ -960,10 +958,10 @@ Connection ~ 7300 4150
Wire Wire Line
7300 4150 7300 4250
$Comp
L Device:C_Small C?
L Device:C_Small C122
U 1 1 5D313053
P 7050 4650
F 0 "C?" V 6821 4650 50 0000 C CNN
F 0 "C122" V 6821 4650 50 0000 C CNN
F 1 "100nF" V 6912 4650 50 0000 C CNN
F 2 "" H 7050 4650 50 0001 C CNN
F 3 "~" H 7050 4650 50 0001 C CNN
@@ -971,10 +969,10 @@ F 3 "~" H 7050 4650 50 0001 C CNN
0 1 1 0
$EndComp
$Comp
L Device:C_Small C?
L Device:C_Small C121
U 1 1 5D319B59
P 6750 4750
F 0 "C?" V 6521 4750 50 0000 C CNN
F 0 "C121" V 6521 4750 50 0000 C CNN
F 1 "100nF" V 6612 4750 50 0000 C CNN
F 2 "" H 6750 4750 50 0001 C CNN
F 3 "~" H 6750 4750 50 0001 C CNN
@@ -1012,10 +1010,10 @@ PCIE_WDISn
Wire Wire Line
4600 4500 4150 4500
$Comp
L Device:C_Small C?
L Device:C_Small C120
U 1 1 5D6779B0
P 5200 2400
F 0 "C?" H 5292 2446 50 0000 L CNN
F 0 "C120" H 5292 2446 50 0000 L CNN
F 1 "10uF" H 5292 2355 50 0000 L CNN
F 2 "" H 5200 2400 50 0001 C CNN
F 3 "~" H 5200 2400 50 0001 C CNN
@@ -1023,10 +1021,10 @@ F 3 "~" H 5200 2400 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L Device:C_Small C?
L Device:C_Small C119
U 1 1 5D677BF9
P 4800 2400
F 0 "C?" H 4892 2446 50 0000 L CNN
F 0 "C119" H 4892 2446 50 0000 L CNN
F 1 "0.1uF" H 4892 2355 50 0000 L CNN
F 2 "" H 4800 2400 50 0001 C CNN
F 3 "~" H 4800 2400 50 0001 C CNN
@@ -1034,10 +1032,10 @@ F 3 "~" H 4800 2400 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L power:+1V5 #PWR?
L power:+1V5 #PWR0212
U 1 1 5D678680
P 5550 2250
F 0 "#PWR?" H 5550 2100 50 0001 C CNN
F 0 "#PWR0212" H 5550 2100 50 0001 C CNN
F 1 "+1V5" H 5565 2423 50 0000 C CNN
F 2 "" H 5550 2250 50 0001 C CNN
F 3 "" H 5550 2250 50 0001 C CNN
@@ -1052,10 +1050,10 @@ Connection ~ 5200 2300
Wire Wire Line
5200 2300 4800 2300
$Comp
L power:GND #PWR?
L power:GND #PWR0213
U 1 1 5D67FFE8
P 5200 2650
F 0 "#PWR?" H 5200 2400 50 0001 C CNN
F 0 "#PWR0213" H 5200 2400 50 0001 C CNN
F 1 "GND" H 5205 2477 50 0000 C CNN
F 2 "" H 5200 2650 50 0001 C CNN
F 3 "" H 5200 2650 50 0001 C CNN


+ 528
- 298
reform2-motherboard/reform2-motherboard/reform2-power.sch
File diff suppressed because it is too large
View File


+ 61
- 15
reform2-motherboard/reform2-motherboard/reform2-sd.sch View File

@@ -6,12 +6,12 @@ $Descr A4 11693 8268
encoding utf-8
Sheet 7 9
Title "MNT Reform 2 SD Card"
Date "2019-06-21"
Date "2019-07-03"
Rev "0.1"
Comp "MNT Research GmbH"
Comment1 "https://mntre.com"
Comment2 "Engineer: Lukas F. Hartmann"
Comment3 ""
Comment3 "License: GPL v3+"
Comment4 ""
$EndDescr
$Comp
@@ -37,9 +37,9 @@ Text GLabel 4450 3250 0 50 Input ~ 0
SD2_CMD
Text GLabel 4450 3550 0 50 Input ~ 0
SD2_CLK
Text GLabel 7550 3350 2 50 Input ~ 0
Text GLabel 7550 3350 2 50 Output ~ 0
SD2_WP
Text GLabel 7550 3250 2 50 Input ~ 0
Text GLabel 7550 3250 2 50 Output ~ 0
SD2_CD
Wire Wire Line
4450 3050 5300 3050
@@ -85,17 +85,15 @@ Wire Wire Line
$Comp
L power:+3V3 #PWR0152
U 1 1 5D1CC1EA
P 4850 2750
F 0 "#PWR0152" H 4850 2600 50 0001 C CNN
F 1 "+3V3" H 4865 2923 50 0000 C CNN
F 2 "" H 4850 2750 50 0001 C CNN
F 3 "" H 4850 2750 50 0001 C CNN
1 4850 2750
P 4050 2400
F 0 "#PWR0152" H 4050 2250 50 0001 C CNN
F 1 "+3V3" H 4065 2573 50 0000 C CNN
F 2 "" H 4050 2400 50 0001 C CNN
F 3 "" H 4050 2400 50 0001 C CNN
1 4050 2400
1 0 0 -1
$EndComp
Wire Wire Line
4850 2750 4850 3450
Wire Wire Line
4850 3450 5300 3450
$Comp
L power:GND #PWR0153
@@ -144,11 +142,59 @@ Wire Wire Line
7200 3550 7200 3650
Connection ~ 7200 3650
Text Notes 5450 2400 0 50 ~ 0
TODO: isolation / level shift?
Text Notes 5450 2550 0 50 ~ 0
TODO: caps
TODO: ESD diodes
Text Notes 5450 2200 0 50 ~ 0
TODO: CD/WP polarity?
Text Notes 5600 4250 0 50 ~ 0
Replace with Molex 5035000993
Text Notes 5650 4400 0 50 ~ 0
Replace with TE 1775059-1
$Comp
L Device:C_Small C?
U 1 1 5EE5821E
P 4050 2550
F 0 "C?" H 4142 2596 50 0000 L CNN
F 1 "47uF" H 4142 2505 50 0000 L CNN
F 2 "" H 4050 2550 50 0001 C CNN
F 3 "~" H 4050 2550 50 0001 C CNN
1 4050 2550
1 0 0 -1
$EndComp
$Comp
L Device:C_Small C?
U 1 1 5EE585F1
P 4400 2550
F 0 "C?" H 4492 2596 50 0000 L CNN
F 1 "0.1uF" H 4492 2505 50 0000 L CNN
F 2 "" H 4400 2550 50 0001 C CNN
F 3 "~" H 4400 2550 50 0001 C CNN
1 4400 2550
1 0 0 -1
$EndComp
Wire Wire Line
4850 2450 4400 2450
Wire Wire Line
4850 2450 4850 3450
Wire Wire Line
4400 2450 4050 2450
Connection ~ 4400 2450
Wire Wire Line
4050 2400 4050 2450
Connection ~ 4050 2450
$Comp
L power:GND #PWR?
U 1 1 5EE59DFE
P 4050 2700
F 0 "#PWR?" H 4050 2450 50 0001 C CNN
F 1 "GND" H 4055 2527 50 0000 C CNN
F 2 "" H 4050 2700 50 0001 C CNN
F 3 "" H 4050 2700 50 0001 C CNN
1 4050 2700
1 0 0 -1
$EndComp
Wire Wire Line
4050 2650 4050 2700
Wire Wire Line
4050 2650 4400 2650
Connection ~ 4050 2650
$EndSCHEMATC

+ 162
- 162
reform2-motherboard/reform2-motherboard/reform2-usb.sch
File diff suppressed because it is too large
View File


+ 40
- 0
reform2-motherboard/reform2-motherboard/reform2.lib View File

@@ -960,6 +960,46 @@ X DBCN 9 -700 -400 100 R 40 40 0 0 I
ENDDRAW
ENDDEF
#
# WM8731
#
DEF WM8731 U 0 40 Y Y 1 F N
F0 "U" -50 1450 50 H V C CNN
F1 "WM8731" 0 1300 50 H V C CNN
F2 "" -50 1450 50 H I C CNN
F3 "" -50 1450 50 H I C CNN
DRAW
S -450 1250 450 -1900 0 1 6 f
X DBVDD 1 -550 1100 100 R 50 50 1 1 W
X RHPOUT 10 550 -300 100 L 50 50 1 1 O
X HPGND 11 550 -1800 100 L 50 50 1 1 P
X LOUT 12 550 700 100 L 50 50 1 1 O
X ROUT 13 550 500 100 L 50 50 1 1 O
X AVDD 14 -550 -1550 100 R 50 50 1 1 W
X AGND 15 -550 -1800 100 R 50 50 1 1 W
X VMID 16 550 -1000 100 L 50 50 1 1 w
X MICBIAS 17 550 150 100 L 50 50 1 1 P
X MICIN 18 550 -100 100 L 50 50 1 1 I
X RLINEIN 19 550 900 100 L 50 50 1 1 I
X CLKOUT 2 550 -1200 100 L 50 50 1 1 O
X LLINEIN 20 550 1100 100 L 50 50 1 1 I
X MODE 21 -550 -1250 100 R 50 50 1 1 I
X CSB 22 -550 -1150 100 R 50 50 1 1 I
X SDIN 23 -550 -1050 100 R 50 50 1 1 I
X SCLK 24 -550 -950 100 R 50 50 1 1 I
X XTI/MCLK 25 -550 -650 100 R 50 50 1 1 I
X XTO 26 -550 -450 100 R 50 50 1 1 O
X DCVDD 27 -550 600 100 R 50 50 1 1 W
X DGND 28 -550 850 100 R 50 50 1 1 W
X BCLK 3 -550 -150 100 R 50 50 1 1 I C
X DACDAT 4 -550 250 100 R 50 50 1 1 I
X DACLRC 5 -550 150 100 R 50 50 1 1 I
X ADCDAT 6 -550 50 100 R 50 50 1 1 O
X ADCLRC 7 -550 -50 100 R 50 50 1 1 I
X HPVDD 8 550 -1550 100 L 50 50 1 1 W
X LHPOUT 9 550 -600 100 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# phycore-imx8m-alpha
#
DEF phycore-imx8m-alpha U 0 40 Y Y 1 F N


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