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WIP: reform 2 motherboard: tweaks for CL-SOM

reform2-clsom
mntmn 1 year ago
parent
commit
083f0de347
12 changed files with 3124 additions and 2906 deletions
  1. +2
    -2
      reform2-motherboard/reform2-motherboard/reform2-audio.sch
  2. +2
    -2
      reform2-motherboard/reform2-motherboard/reform2-display.sch
  3. +7
    -5
      reform2-motherboard/reform2-motherboard/reform2-eth.sch
  4. +2
    -2
      reform2-motherboard/reform2-motherboard/reform2-hdmi.sch
  5. +93
    -139
      reform2-motherboard/reform2-motherboard/reform2-motherboard-cache.lib
  6. +2049
    -2327
      reform2-motherboard/reform2-motherboard/reform2-motherboard.kicad_pcb
  7. +784
    -325
      reform2-motherboard/reform2-motherboard/reform2-motherboard.sch
  8. +10
    -4
      reform2-motherboard/reform2-motherboard/reform2-pcie.sch
  9. +60
    -2
      reform2-motherboard/reform2-motherboard/reform2-power.sch
  10. +2
    -2
      reform2-motherboard/reform2-motherboard/reform2-sd.sch
  11. +21
    -4
      reform2-motherboard/reform2-motherboard/reform2-usb.sch
  12. +92
    -92
      reform2-motherboard/reform2-motherboard/reform2.lib

+ 2
- 2
reform2-motherboard/reform2-motherboard/reform2-audio.sch View File

@@ -6,8 +6,8 @@ $Descr A4 11693 8268
encoding utf-8
Sheet 9 9
Title "Reform 2 Audio"
Date "2019-07-03"
Rev "0.1"
Date "2019-07-09"
Rev "0.1.1"
Comp "MNT Research GmbH"
Comment1 "https://mntre.com"
Comment2 "Engineer: Lukas F. Hartmann"


+ 2
- 2
reform2-motherboard/reform2-motherboard/reform2-display.sch View File

@@ -6,8 +6,8 @@ $Descr A4 11693 8268
encoding utf-8
Sheet 5 9
Title "MNT Reform 2 Internal Display"
Date "2019-07-03"
Rev "0.1"
Date "2019-07-09"
Rev "0.1.1"
Comp "MNT Research GmbH"
Comment1 "https://mntre.com"
Comment2 "Engineer: Lukas F. Hartmann"


+ 7
- 5
reform2-motherboard/reform2-motherboard/reform2-eth.sch View File

@@ -6,8 +6,8 @@ $Descr A4 11693 8268
encoding utf-8
Sheet 4 9
Title "MNT Reform 2 Ethernet"
Date "2019-07-03"
Rev "0.1"
Date "2019-07-09"
Rev "0.1.1"
Comp "MNT Research GmbH"
Comment1 "https://mntre.com"
Comment2 "Engineer: Lukas F. Hartmann"
@@ -225,9 +225,9 @@ Wire Wire Line
4150 4850 5050 4850
Wire Wire Line
4150 4850 4150 5450
Text GLabel 5050 5050 0 60 Output ~ 0
ETH0_LED_LINK
Text GLabel 5050 5650 0 60 Output ~ 0
Text GLabel 5050 5650 0 60 Input ~ 0
ETH0_LED_LINK1
Text GLabel 5050 5050 0 60 Input ~ 0
ETH0_LED_RX
Text GLabel 5050 2250 0 60 Output ~ 0
ETH0_D-
@@ -245,4 +245,6 @@ Text GLabel 5050 4650 0 60 Output ~ 0
ETH0_A-
Text GLabel 5050 4050 0 60 Output ~ 0
ETH0_A+
Text GLabel 5050 5250 0 60 Input ~ 0
ETH0_LED_LINK2
$EndSCHEMATC

+ 2
- 2
reform2-motherboard/reform2-motherboard/reform2-hdmi.sch View File

@@ -6,8 +6,8 @@ $Descr A4 11693 8268
encoding utf-8
Sheet 8 9
Title "MNT Reform 2 External Display"
Date "2019-07-03"
Rev "0.1"
Date "2019-07-09"
Rev "0.1.1"
Comp "MNT Research GmbH"
Comment1 "https://mntre.com"
Comment2 "Engineer: Lukas F. Hartmann"


+ 93
- 139
reform2-motherboard/reform2-motherboard/reform2-motherboard-cache.lib View File

@@ -1180,31 +1180,6 @@ X ~ 2 300 0 200 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Switch_SW_DIP_x02
#
DEF Switch_SW_DIP_x02 SW 0 0 Y N 1 F N
F0 "SW" 0 250 50 H V C CNN
F1 "Switch_SW_DIP_x02" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
SW?DIP?x2*
$ENDFPLIST
DRAW
C -80 0 20 0 0 0 N
C -80 100 20 0 0 0 N
C 80 0 20 0 0 0 N
C 80 100 20 0 0 0 N
S -150 200 150 -100 0 1 10 f
P 2 0 0 0 -60 5 93 46 N
P 2 0 0 0 -60 105 93 146 N
X ~ 1 -300 100 200 R 50 50 1 1 P
X ~ 2 -300 0 200 R 50 50 1 1 P
X ~ 3 300 0 200 L 50 50 1 1 P
X ~ 4 300 100 200 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Switch_SW_Push
#
DEF Switch_SW_Push SW 0 40 N N 1 F N
@@ -1742,25 +1717,7 @@ T 0 -777 2030 40 0 0 0 TRD4+ Normal 0 L B
T 0 -776 1427 40 0 0 0 TRD4- Normal 0 L B
T 0 -776 -1176 40 0 0 0 YEL+ Normal 0 L B
T 0 -778 -1380 40 0 0 0 YEL- Normal 0 L B
P 2 0 0 10 -800 -2000 -800 -2100 N
P 2 0 0 10 -800 -1800 -800 -2000 N
P 2 0 0 10 -800 -1600 -800 -1800 N
P 2 0 0 10 -800 -1400 -800 -1600 N
P 2 0 0 10 -800 -1200 -800 -1400 N
P 2 0 0 10 -800 -1000 -800 -1200 N
P 2 0 0 10 -800 -700 -800 -1000 N
P 2 0 0 10 -800 -400 -800 -700 N
P 2 0 0 10 -800 -200 -800 -400 N
P 2 0 0 10 -800 100 -800 -200 N
P 2 0 0 10 -800 400 -800 100 N
P 2 0 0 10 -800 600 -800 400 N
P 2 0 0 10 -800 900 -800 600 N
P 2 0 0 10 -800 1200 -800 900 N
P 2 0 0 10 -800 1400 -800 1200 N
P 2 0 0 10 -800 1700 -800 1400 N
P 2 0 0 10 -800 2000 -800 1700 N
P 2 0 0 10 -800 2100 -800 2000 N
P 2 0 0 10 -800 2100 800 2100 N
S -800 2100 800 -2100 0 0 10 f
P 2 0 0 10 -700 -2000 -625 -2000 N
P 2 0 0 10 -700 -1800 -625 -1800 N
P 2 0 0 10 -700 -1400 -625 -1400 N
@@ -1940,10 +1897,7 @@ P 2 0 0 6 700 900 700 100 N
P 2 0 0 6 700 1700 569 1700 N
P 2 0 0 6 700 1700 700 900 N
P 2 0 0 6 725 -1900 675 -2000 N
P 2 0 0 10 800 -2100 -800 -2100 N
P 2 0 0 6 800 -1800 600 -1800 N
P 2 0 0 10 800 -1800 800 -2100 N
P 2 0 0 10 800 2100 800 -1800 N
P 3 0 0 6 -270 -1620 -285 -1655 -305 -1635 F
P 3 0 0 6 -265 -1935 -300 -1920 -280 -1900 F
P 3 0 0 6 -265 -1665 -280 -1700 -300 -1680 F
@@ -2180,124 +2134,123 @@ F3 "" -350 2700 50 H I C CNN
DRAW
S -850 4850 700 -5450 0 1 0 f
X GND 1 -950 4750 100 R 50 50 1 1 W
X VSYS 10 800 4350 100 L 50 50 1 1 O
X VSYS 10 800 4350 100 L 50 50 1 1 W
X QSPI_A_SS1_B 100 800 -150 100 L 50 50 1 1 O
X CSI_P1_DP2 101 -950 -150 100 R 50 50 1 1 O
X CSI_P1_DP2 101 -950 -250 100 R 50 50 1 1 O
X QSPI_A_DQS 102 800 -250 100 L 50 50 1 1 O
X CSI_P1_DN2 103 -950 -250 100 R 50 50 1 1 O
X CSI_P1_DN2 103 -950 -350 100 R 50 50 1 1 O
X QSPI_A_SCLK 104 800 -350 100 L 50 50 1 1 O
X GND 105 -950 -350 100 R 50 50 1 1 O
X GND 105 -950 -450 100 R 50 50 1 1 W
X SAI1_RX_SYNC 106 800 -450 100 L 50 50 1 1 O
X CSI_P1_CKP 107 -950 -450 100 R 50 50 1 1 O
X CSI_P1_CKP 107 -950 -550 100 R 50 50 1 1 O
X SAI1_MCLK 108 800 -550 100 L 50 50 1 1 O
X CSI_P1_CKN 109 -950 -550 100 R 50 50 1 1 O
X ECSPI1_MOSI 11 -950 4250 100 R 50 50 1 1 W
X CSI_P1_CKN 109 -950 -650 100 R 50 50 1 1 O
X ECSPI1_MOSI 11 -950 4250 100 R 50 50 1 1 O
X SAI1_TX_SYNC 110 800 -650 100 L 50 50 1 1 O
X UART3_TX 111 -950 -650 100 R 50 50 1 1 O
X UART3_TX 111 -950 -750 100 R 50 50 1 1 O
X SAI1_TX_BCLK 112 800 -750 100 L 50 50 1 1 O
X CSI_P1_DN3 113 -950 -750 100 R 50 50 1 1 O
X VSYS 114 800 -850 100 L 50 50 1 1 O
X CSI_P1_DP3 115 -950 -850 100 R 50 50 1 1 O
X CSI_P1_DN3 113 -950 -850 100 R 50 50 1 1 O
X VSYS 114 800 -850 100 L 50 50 1 1 W
X CSI_P1_DP3 115 -950 -950 100 R 50 50 1 1 O
X SAI1_TX_DATA[0] 116 800 -950 100 L 50 50 1 1 O
X UART3_RX 117 -950 -950 100 R 50 50 1 1 O
X UART3_RX 117 -950 -1050 100 R 50 50 1 1 O
X SAI1_TX_DATA[1] 118 800 -1050 100 L 50 50 1 1 O
X PCIE1_REF_CLKP 119 -950 -1050 100 R 50 50 1 1 O
X PCIE1_REF_CLKP 119 -950 -1150 100 R 50 50 1 1 O
X ETH1_MDI1N 12 800 4250 100 L 50 50 1 1 O
X SAI1_TX_DATA[2] 120 800 -1150 100 L 50 50 1 1 O
X PCIE1_REF_CLKN 121 -950 -1150 100 R 50 50 1 1 O
X PCIE1_REF_CLKN 121 -950 -1250 100 R 50 50 1 1 O
X SAI1_TX_DATA[3] 122 800 -1250 100 L 50 50 1 1 O
X GND 123 -950 -1250 100 R 50 50 1 1 O
X GND 123 -950 -1350 100 R 50 50 1 1 W
X GPIO3_IO[16] 124 800 -1350 100 L 50 50 1 1 O
X PCIE1_TXN_P 125 -950 -1350 100 R 50 50 1 1 O
X PCIE1_TXN_P 125 -950 -1450 100 R 50 50 1 1 O
X SAI1_TX_DATA[3] 126 800 -1450 100 L 50 50 1 1 O
X PCIE1_TXN_N 127 -950 -1450 100 R 50 50 1 1 O
X PCIE1_TXN_N 127 -950 -1550 100 R 50 50 1 1 O
X SAI1_TX_DATA[4] 128 800 -1550 100 L 50 50 1 1 O
X ENET1_MDC 129 -950 -1550 100 R 50 50 1 1 O
X ECSPI1_SCLK 13 -950 4150 100 R 50 50 1 1 W
X ENET1_MDC 129 -950 -1650 100 R 50 50 1 1 O
X ECSPI1_SCLK 13 -950 4150 100 R 50 50 1 1 O
X SAI1_TX_DATA[7] 130 800 -1650 100 L 50 50 1 1 O
X PCIE1_RXN_P 131 -950 -1650 100 R 50 50 1 1 O
X VSYS 132 800 -1750 100 L 50 50 1 1 O
X PCIE1_RXN_N 133 -950 -1750 100 R 50 50 1 1 O
X PCIE1_RXN_P 131 -950 -1750 100 R 50 50 1 1 O
X VSYS 132 800 -1750 100 L 50 50 1 1 W
X PCIE1_RXN_N 133 -950 -1850 100 R 50 50 1 1 O
X SAI1_RX_DATA[0] 134 800 -1850 100 L 50 50 1 1 O
X ENET1_MDIO 135 -950 -1850 100 R 50 50 1 1 O
X ENET1_MDIO 135 -950 -1950 100 R 50 50 1 1 O
X SAI1_RX_DATA[1] 136 800 -1950 100 L 50 50 1 1 O
X SAI1_RX_DATA[4] 137 -950 -1950 100 R 50 50 1 1 O
X SAI1_RX_DATA[4] 137 -950 -2050 100 R 50 50 1 1 O
X SAI1_RX_DATA[2] 138 800 -2050 100 L 50 50 1 1 O
X SAI1_RX_DATA[5] 139 -950 -2050 100 R 50 50 1 1 O
X SAI1_TX_DATA[5] 139 -950 -2250 100 R 50 50 1 1 O
X SAI1_RX_DATA[5] 139 -950 -2150 100 R 50 50 1 1 O
X ETH1_MDI1P 14 800 4150 100 L 50 50 1 1 O
X SAI1_RX_DATA[3] 140 800 -2150 100 L 50 50 1 1 O
X GND 141 -950 -2350 100 R 50 50 1 1 O
X GND 141 -950 -2150 100 R 50 50 1 1 O
X GND 141 -950 -2250 100 R 50 50 1 1 W
X SAI1_TX_BCLK 142 800 -2250 100 L 50 50 1 1 O
X SAI1_TX_DATA[5] 143 -950 -2450 100 R 50 50 1 1 O
X SAI1_TX_DATA[5] 143 -950 -2350 100 R 50 50 1 1 O
X SAI1_TX_DATA[0] 144 800 -2350 100 L 50 50 1 1 O
X SAI1_RX_DATA[6] 145 -950 -2550 100 R 50 50 1 1 O
X SAI1_RX_DATA[6] 145 -950 -2450 100 R 50 50 1 1 O
X SAI1_TX_DATA[1] 146 800 -2450 100 L 50 50 1 1 O
X QSPI_B_SCLK 147 -950 -2650 100 R 50 50 1 1 O
X QSPI_B_SCLK 147 -950 -2550 100 R 50 50 1 1 O
X SAI1_TX_DATA[2] 148 800 -2550 100 L 50 50 1 1 O
X QSPI_B_DATA[3] 149 -950 -2750 100 R 50 50 1 1 O
X ECSPI1_MISO 15 -950 4050 100 R 50 50 1 1 W
X VSYS 150 800 -2650 100 L 50 50 1 1 O
X QSPI_B_DATA[2] 151 -950 -2850 100 R 50 50 1 1 O
X QSPI_B_DATA[3] 149 -950 -2650 100 R 50 50 1 1 O
X ECSPI1_MISO 15 -950 4050 100 R 50 50 1 1 O
X VSYS 150 800 -2650 100 L 50 50 1 1 W
X QSPI_B_DATA[2] 151 -950 -2750 100 R 50 50 1 1 O
X SAI1_RX_DATA[7] 152 800 -2750 100 L 50 50 1 1 O
X QSPI_B_DATA[1] 153 -950 -2950 100 R 50 50 1 1 O
X QSPI_B_DATA[1] 153 -950 -2850 100 R 50 50 1 1 O
X USDHC2_RESET_B 154 800 -2850 100 L 50 50 1 1 O
X QSPI_B_DATA[0] 155 -950 -3050 100 R 50 50 1 1 O
X QSPI_B_DATA[0] 155 -950 -2950 100 R 50 50 1 1 O
X USB2_VBUS_DET 156 800 -2950 100 L 50 50 1 1 O
X QSPI_B_DQS 157 -950 -3150 100 R 50 50 1 1 O
X QSPI_B_DQS 157 -950 -3050 100 R 50 50 1 1 O
X USB2_RX_P 158 800 -3050 100 L 50 50 1 1 O
X GND 159 -950 -3250 100 R 50 50 1 1 O
X GND 159 -950 -3150 100 R 50 50 1 1 W
X ETH1_LED1_SPD 16 800 4050 100 L 50 50 1 1 O
X USB2_RX_N 160 800 -3150 100 L 50 50 1 1 O
X LVDS1_TX3_P 161 -950 -3350 100 R 50 50 1 1 O
X LVDS1_TX3_P 161 -950 -3250 100 R 50 50 1 1 O
X SAI1_TX_DATA[6] 162 800 -3250 100 L 50 50 1 1 O
X LVDS1_TX3_N 163 -950 -3450 100 R 50 50 1 1 O
X LVDS1_TX3_N 163 -950 -3350 100 R 50 50 1 1 O
X USB2_TX_P 164 800 -3350 100 L 50 50 1 1 O
X ONOFF 165 -950 -3550 100 R 50 50 1 1 O
X ONOFF 165 -950 -3450 100 R 50 50 1 1 O
X USB2_TX_N 166 800 -3450 100 L 50 50 1 1 O
X PCIE2_RXN_N 167 -950 -3650 100 R 50 50 1 1 O
X VSYS 168 800 -3550 100 L 50 50 1 1 O
X PCIE2_RXN_P 169 -950 -3750 100 R 50 50 1 1 O
X ECSPI1_SS0 17 -950 3950 100 R 50 50 1 1 W
X PCIE2_RXN_N 167 -950 -3550 100 R 50 50 1 1 O
X VSYS 168 800 -3550 100 L 50 50 1 1 W
X PCIE2_RXN_P 169 -950 -3650 100 R 50 50 1 1 O
X ECSPI1_SS0 17 -950 3950 100 R 50 50 1 1 O
X USB2_DN 170 800 -3650 100 L 50 50 1 1 O
X COLD_RESET_IN 171 -950 -3850 100 R 50 50 1 1 O
X COLD_RESET_IN 171 -950 -3750 100 R 50 50 1 1 O
X USB2_DP 172 800 -3750 100 L 50 50 1 1 O
X PCIE2_TXN_N 173 -950 -3950 100 R 50 50 1 1 O
X PCIE2_TXN_N 173 -950 -3850 100 R 50 50 1 1 O
X USB1_ID 174 800 -3850 100 L 50 50 1 1 O
X PCIE2_TXN_P 175 -950 -4050 100 R 50 50 1 1 O
X PCIE2_TXN_P 175 -950 -3950 100 R 50 50 1 1 O
X USB1_DP 176 800 -3950 100 L 50 50 1 1 O
X GND 177 -950 -4150 100 R 50 50 1 1 O
X GND 177 -950 -4050 100 R 50 50 1 1 W
X USB1_DN 178 800 -4050 100 L 50 50 1 1 O
X PCIE2_REF_CLKN 179 -950 -4250 100 R 50 50 1 1 O
X PCIE2_REF_CLKN 179 -950 -4150 100 R 50 50 1 1 O
X ETH1_MDI2N 18 800 3950 100 L 50 50 1 1 O
X USB1_VBUS_DET 180 800 -4150 100 L 50 50 1 1 O
X PCIE2_REF_CLKP 181 -950 -4350 100 R 50 50 1 1 O
X PCIE2_REF_CLKP 181 -950 -4250 100 R 50 50 1 1 O
X USB1_RX_P 182 800 -4250 100 L 50 50 1 1 O
X VCC_RTC 183 -950 -4450 100 R 50 50 1 1 O
X VCC_RTC 183 -950 -4350 100 R 50 50 1 1 O
X USB1_RX_N 184 800 -4350 100 L 50 50 1 1 O
X ALT_BOOT 185 -950 -4550 100 R 50 50 1 1 O
X ALT_BOOT 185 -950 -4450 100 R 50 50 1 1 O
X VSYS 186 800 -4450 100 L 50 50 1 1 O
X NC 187 -950 -4650 100 R 50 50 1 1 O
X NC 187 -950 -4550 100 R 50 50 1 1 N
X USB1_TX_P 188 800 -4550 100 L 50 50 1 1 O
X EEPROM_WP 189 -950 -4750 100 R 50 50 1 1 O
X EEPROM_WP 189 -950 -4650 100 R 50 50 1 1 O
X GND 19 -950 3850 100 R 50 50 1 1 W
X USB1_TX_N 190 800 -4650 100 L 50 50 1 1 O
X MICBIAS 191 -950 -4850 100 R 50 50 1 1 O
X SAI2_MCLK 191 -950 -4750 100 R 50 50 1 1 O
X SAI1_RX_BCLK 192 800 -4750 100 L 50 50 1 1 O
X MICIN 193 -950 -4950 100 R 50 50 1 1 O
X MICIN 193 -950 -4850 100 R 50 50 1 1 O
X SAI1_TX_DATA[4] 194 800 -4850 100 L 50 50 1 1 O
X AUD_GND 195 -950 -5050 100 R 50 50 1 1 O
X AUD_GND 195 -950 -4950 100 R 50 50 1 1 P
X PWM3_OUT 196 800 -4950 100 L 50 50 1 1 O
X SAI2_TX_BCLK 197 -950 -5150 100 R 50 50 1 1 O
X SAI2_TX_BCLK 197 -950 -5050 100 R 50 50 1 1 O
X PWM2_OUT 198 800 -5050 100 L 50 50 1 1 O
X AVDD33_ETH 2 800 4750 100 L 50 50 1 1 O
X SAI2_TX_SYNC 199 -950 -5150 100 R 50 50 1 1 I
X AVDD33_ETH 2 800 4750 100 L 50 50 1 1 w
X ETH1_MDI2P 20 800 3850 100 L 50 50 1 1 O
X PWM1_OUT 200 800 -5150 100 L 50 50 1 1 O
X SAI2_TX_SYNC 201 -950 -5250 100 R 50 50 1 1 O
X SAI2_TX_DATA[0] 201 -950 -5250 100 R 50 50 1 1 O
X PMIC_ON_REQ 202 800 -5250 100 L 50 50 1 1 O
X SAI2_RX_DATA[0] 203 -950 -5350 100 R 50 50 1 1 O
X VSYS 204 800 -5350 100 L 50 50 1 1 O
X VSYS 204 800 -5350 100 L 50 50 1 1 W
X LVDS1_TX0_P 21 -950 3750 100 R 50 50 1 1 O
X ETH1_LED3 22 800 3750 100 L 50 50 1 1 O
X LVDS1_TX0_N 23 -950 3650 100 R 50 50 1 1 O
@@ -2305,9 +2258,9 @@ X ETH1_MDI3N 24 800 3650 100 L 50 50 1 1 O
X HDMI_DDC_SCL 25 -950 3550 100 R 50 50 1 1 O
X ETH1_MDI3P 26 800 3550 100 L 50 50 1 1 O
X HDMI_AUXN 27 -950 3450 100 R 50 50 1 1 O
X VSYS 28 800 3450 100 L 50 50 1 1 O
X VSYS 28 800 3450 100 L 50 50 1 1 W
X HDMI_AUXP 29 -950 3350 100 R 50 50 1 1 O
X PCIE2_CLKREQ_B 3 -950 4650 100 R 50 50 1 1 W
X PCIE2_CLKREQ_B 3 -950 4650 100 R 50 50 1 1 O
X HDMI_CLKP 30 800 3350 100 L 50 50 1 1 O
X HDMI_DDC_SDA 31 -950 3250 100 R 50 50 1 1 O
X HDMI_CLKN 32 800 3250 100 L 50 50 1 1 O
@@ -2315,7 +2268,7 @@ X DSI_DP2 33 -950 3150 100 R 50 50 1 1 O
X HDMI_CEC 34 800 3150 100 L 50 50 1 1 O
X DSI_DN2 35 -950 3050 100 R 50 50 1 1 O
X HDMI_TXP0 36 800 3050 100 L 50 50 1 1 O
X GND 37 -950 2950 100 R 50 50 1 1 O
X GND 37 -950 2950 100 R 50 50 1 1 W
X HDMI_TXN0 38 800 2950 100 L 50 50 1 1 O
X DSI_DP0 39 -950 2850 100 R 50 50 1 1 O
X ETH1_LED_ACT 4 800 4650 100 L 50 50 1 1 O
@@ -2325,17 +2278,17 @@ X HDMI_TXP1 42 800 2750 100 L 50 50 1 1 O
X I2C3_SCL 43 -950 2650 100 R 50 50 1 1 O
X HDMI_TXN1 44 800 2650 100 L 50 50 1 1 O
X DSI_DP1 45 -950 2550 100 R 50 50 1 1 O
X VSYS 46 800 2550 100 L 50 50 1 1 O
X VSYS 46 800 2550 100 L 50 50 1 1 W
X DSI_DN1 47 -950 2450 100 R 50 50 1 1 O
X HDMI_TXP2 48 800 2450 100 L 50 50 1 1 O
X I2C3_SDA 49 -950 2350 100 R 50 50 1 1 O
X PCIE1_CLKREQ_B 5 -950 4550 100 R 50 50 1 1 W
X PCIE1_CLKREQ_B 5 -950 4550 100 R 50 50 1 1 O
X HDMI_TXN2 50 800 2350 100 L 50 50 1 1 O
X DSI_DP3 51 -950 2250 100 R 50 50 1 1 O
X ENET1_MDC 52 800 2250 100 L 50 50 1 1 O
X DSI_DN3 53 -950 2150 100 R 50 50 1 1 O
X JTAG_MOD 54 800 2150 100 L 50 50 1 1 O
X GND 55 -950 2050 100 R 50 50 1 1 O
X GND 55 -950 2050 100 R 50 50 1 1 W
X JTAG_NTRST 56 800 2050 100 L 50 50 1 1 O
X DSI_CKN 57 -950 1950 100 R 50 50 1 1 O
X UART2_TX 58 800 1950 100 L 50 50 1 1 O
@@ -2344,45 +2297,46 @@ X ETH1_MDI0N 6 800 4550 100 L 50 50 1 1 O
X GPIO3_IO[17] 60 800 1850 100 L 50 50 1 1 O
X USDHC2_CD_B 61 -950 1750 100 R 50 50 1 1 O
X GPIO1_IO[19] 62 800 1750 100 L 50 50 1 1 O
X VSYS 64 800 1650 100 L 50 50 1 1 O
X ECSPI3_MISO 65 -950 1650 100 R 50 50 1 1 O
X UART2_RX 63 -950 1650 100 R 50 50 1 1 O
X VSYS 64 800 1650 100 L 50 50 1 1 W
X ECSPI3_MISO 65 -950 1550 100 R 50 50 1 1 O
X JTAG_TCK 66 800 1550 100 L 50 50 1 1 O
X USDHC2_WP 67 -950 1550 100 R 50 50 1 1 O
X USDHC2_WP 67 -950 1450 100 R 50 50 1 1 O
X JTAG_TMS 68 800 1450 100 L 50 50 1 1 O
X ECSPI3_SCLK 69 -950 1450 100 R 50 50 1 1 O
X QSPI_BSS0_B 7 -950 4450 100 R 50 50 1 1 W
X ECSPI3_SCLK 69 -950 1350 100 R 50 50 1 1 O
X QSPI_BSS0_B 7 -950 4450 100 R 50 50 1 1 O
X JTAG_TDI 70 800 1350 100 L 50 50 1 1 O
X GND 71 -950 1350 100 R 50 50 1 1 O
X GND 71 -950 1250 100 R 50 50 1 1 W
X JTAG_TDO 72 800 1250 100 L 50 50 1 1 O
X PCIE1_CLKREQ_B 73 -950 1250 100 R 50 50 1 1 O
X I2C4_SCL 73 -950 1150 100 R 50 50 1 1 O
X QSPI_A_DATA[0] 74 800 1150 100 L 50 50 1 1 O
X PCIE2_CLKREQ_B 75 -950 1150 100 R 50 50 1 1 O
X I2C4_SDA 75 -950 1050 100 R 50 50 1 1 O
X QSPI_A_DATA[1] 76 800 1050 100 L 50 50 1 1 O
X LVDS1_CLK_P 77 -950 1050 100 R 50 50 1 1 O
X VSYS 78 800 950 100 L 50 50 1 1 O
X LVDS1_CLK_N 79 -950 950 100 R 50 50 1 1 O
X LVDS1_CLK_P 77 -950 950 100 R 50 50 1 1 O
X VSYS 78 800 950 100 L 50 50 1 1 W
X LVDS1_CLK_N 79 -950 850 100 R 50 50 1 1 O
X ETH1_MDI0P 8 800 4450 100 L 50 50 1 1 O
X USDHC2_CLK 80 800 850 100 L 50 50 1 1 O
X GPIO3_IO[18] 81 -950 850 100 R 50 50 1 1 O
X GPIO3_IO[18] 81 -950 750 100 R 50 50 1 1 O
X USDHC2_CMD 82 800 750 100 L 50 50 1 1 O
X CSI_P1_DP0 83 -950 750 100 R 50 50 1 1 O
X CSI_P1_DP0 83 -950 650 100 R 50 50 1 1 O
X USDHC2_DATA0 84 800 650 100 L 50 50 1 1 O
X CSI_P1_DN0 85 -950 650 100 R 50 50 1 1 O
X CSI_P1_DN0 85 -950 550 100 R 50 50 1 1 O
X USDHC2_DATA1 86 800 550 100 L 50 50 1 1 O
X GND 87 -950 550 100 R 50 50 1 1 O
X GND 87 -950 450 100 R 50 50 1 1 W
X USDHC2_DATA2 88 800 450 100 L 50 50 1 1 O
X CSI_P1_DP1 89 -950 450 100 R 50 50 1 1 O
X QSPI_B_SS1_B 9 -950 4350 100 R 50 50 1 1 W
X CSI_P1_DP1 89 -950 350 100 R 50 50 1 1 O
X QSPI_B_SS1_B 9 -950 4350 100 R 50 50 1 1 O
X USDHC2_DATA3 90 800 350 100 L 50 50 1 1 O
X CSI_P1_DN1 91 -950 350 100 R 50 50 1 1 O
X CSI_P1_DN1 91 -950 250 100 R 50 50 1 1 O
X QSPI_A_DATA[2] 92 800 250 100 L 50 50 1 1 O
X LVDS1_TX1_P 93 -950 250 100 R 50 50 1 1 O
X LVDS1_TX1_P 93 -950 150 100 R 50 50 1 1 O
X QSPI_A_DATA[3] 94 800 150 100 L 50 50 1 1 O
X LVDS1_TX1_N 95 -950 150 100 R 50 50 1 1 O
X VSYS 96 800 50 100 L 50 50 1 1 O
X LVDS1_TX2_P 97 -950 50 100 R 50 50 1 1 O
X LVDS1_TX1_N 95 -950 50 100 R 50 50 1 1 O
X VSYS 96 800 50 100 L 50 50 1 1 W
X LVDS1_TX2_P 97 -950 -50 100 R 50 50 1 1 O
X QSPI_A_SS0_B 98 800 -50 100 L 50 50 1 1 O
X LVDS1_TX2_N 99 -950 -50 100 R 50 50 1 1 O
X LVDS1_TX2_N 99 -950 -150 100 R 50 50 1 1 O
ENDDRAW
ENDDEF
#


+ 2049
- 2327
reform2-motherboard/reform2-motherboard/reform2-motherboard.kicad_pcb
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+ 784
- 325
reform2-motherboard/reform2-motherboard/reform2-motherboard.sch
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+ 10
- 4
reform2-motherboard/reform2-motherboard/reform2-pcie.sch View File

@@ -6,8 +6,8 @@ $Descr A4 11693 8268
encoding utf-8
Sheet 6 9
Title "MNT Reform 2 PCIe"
Date "2019-07-03"
Rev "0.1"
Date "2019-07-09"
Rev "0.1.1"
Comp "MNT Research GmbH"
Comment1 "https://mntre.com"
Comment2 "Engineer: Lukas F. Hartmann"
@@ -1025,7 +1025,6 @@ NoConn ~ 2850 3100
NoConn ~ 2850 3200
NoConn ~ 2850 4500
NoConn ~ 2850 4600
NoConn ~ 2850 5200
NoConn ~ 2850 5300
NoConn ~ 2850 5400
NoConn ~ 2850 5500
@@ -1034,7 +1033,6 @@ NoConn ~ 4150 5100
NoConn ~ 4150 5000
NoConn ~ 4150 4900
NoConn ~ 4150 4800
NoConn ~ 9000 4850
Text GLabel 4600 4500 2 50 Input ~ 0
PCIE_WDISn
Wire Wire Line
@@ -1120,4 +1118,12 @@ Wire Wire Line
Connection ~ 4500 4100
Wire Wire Line
4500 4100 4500 5300
Text GLabel 2400 5200 0 50 Output ~ 0
PCIE1_CLKREQn
Wire Wire Line
2850 5200 2400 5200
Text GLabel 9850 4850 2 50 Output ~ 0
PCIE2_CLKREQn
Wire Wire Line
9850 4850 9000 4850
$EndSCHEMATC

+ 60
- 2
reform2-motherboard/reform2-motherboard/reform2-power.sch View File

@@ -6,8 +6,8 @@ $Descr A3 16535 11693
encoding utf-8
Sheet 2 9
Title "MNT Reform 2 Power System"
Date "2019-07-03"
Rev "0.1"
Date "2019-07-09"
Rev "0.1.1"
Comp "MNT Research GmbH"
Comment1 "https://mntre.com"
Comment2 "Engineer: Lukas F. Hartmann"
@@ -4528,4 +4528,62 @@ Text Notes 11500 2750 0 50 ~ 0
Up to 5A @ 3.3V
Text Notes 11500 1700 0 50 ~ 0
Up to 3A @ 5V
$Bitmap
Pos 15350 10250
Scale 1.000000
Data
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65 1C 87 F1 67 77 45 B1 08 82 26 F1 D2 6A 5A FF 00 0B B5 16 4C 36 12 5D 2F 9D 69 BC 04 0D 5E 62
A3 A4 B1 D0 CE 4B C4 24 42 2A 05 03 21 85 FA 07 68 B4 8A 60 67 21 12 6D 04 0D 1A 90 04 4C 97 B5
98 19 CE 64 F7 9C 39 B7 77 DE DF 7B F6 3C 1F 38 EC 16 CB EC 97 2D 1E 66 66 77 CF 80 24 49 92 24
49 92 24 49 92 24 49 92 24 49 92 24 49 92 24 49 92 24 49 92 24 49 92 24 49 52 42 8F 00 7B A2 47
B4 1C 8A 1E D0 F2 10 70 5F F4 08 49 03 C7 81 B3 94 13 AD 3F 80 67 A2 47 D4 8E 02 DF 60 B4 A4 62
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D4 8C 96 3A 19 AC FC 4A 8C D6 09 8C 96 16 80 C1 8A 61 B4 BA ED 07 3E 05 EE 89 1E A2 B2 18 AC 38
46 AB DB 01 E0 14 46 4B 2D 06 2B 96 D1 EA D6 5C 1E 1A 2D 01 06 AB 04 4D B4 3E C2 68 0D 73 80 EA
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24 46 6B E9 18 AC B2 95 16 AD 4B 54 67 5A 46 4B 21 7C 4F F7 C9 9D 07 7E 4D 70 9C 9F A7 FC FA 26
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60 41 9A 68 A5 08 16 A4 89 96 C1 92 12 9B 37 5A 29 83 05 55 B4 2E CC B8 25 65 B0 60 FE 68 19 2C
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17 AD 3E 83 05 D3 47 AB AF 60 C1 F4 D1 32 58 52 06 D3 44 AB EF 60 C1 74 D1 EA 33 58 50 45 EB 65
26 8B 96 C1 92 32 99 34 5A 39 82 05 93 47 AB EF 60 C1 E4 D1 32 58 52 46 6B 54 4F 9C E9 8A 56 AE
60 C1 64 D1 CA 11 2C 98 2C 5A 06 4B CA 6C 5C B4 72 06 0B AA 68 7D 3F 62 4B CE 60 C1 F8 68 19 2C
29 40 57 B4 72 07 0B 60 1F A3 A3 95 33 58 D0 1D 2D 83 25 05 19 15 AD 88 60 C1 E8 68 E5 0E 16 8C
8E 96 C1 92 02 0D 8B 56 54 B0 A0 8A D6 0F C4 07 0B 86 47 CB 60 49 C1 D6 A8 9E 38 73 9D F8 60 C1
F6 68 45 05 0B AA 68 1D 61 10 2D 83 25 15 A0 1D AD E8 60 C1 CD D1 8A 0C 16 DC 1C 2D 83 25 15 A2
89 56 09 0F 93 80 41 B4 A2 83 05 83 68 FD 14 3D 44 D2 C0 1A B0 1E 3D A2 65 1F F0 60 F4 88 DA 0A
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EndData
$EndBitmap
$EndSCHEMATC

+ 2
- 2
reform2-motherboard/reform2-motherboard/reform2-sd.sch View File

@@ -6,8 +6,8 @@ $Descr A4 11693 8268
encoding utf-8
Sheet 7 9
Title "MNT Reform 2 SD Card"
Date "2019-07-03"
Rev "0.1"
Date "2019-07-09"
Rev "0.1.1"
Comp "MNT Research GmbH"
Comment1 "https://mntre.com"
Comment2 "Engineer: Lukas F. Hartmann"


+ 21
- 4
reform2-motherboard/reform2-motherboard/reform2-usb.sch View File

@@ -6,8 +6,8 @@ $Descr A3 16535 11693
encoding utf-8
Sheet 3 9
Title "MNT Reform 2 USB"
Date "2019-07-03"
Rev "0.1"
Date "2019-07-09"
Rev "0.1.1"
Comp "MNT Research GmbH"
Comment1 "https://mntre.com"
Comment2 "Engineer: Lukas F. Hartmann"
@@ -720,8 +720,6 @@ F 3 "" H 9500 4800 50 0001 C CNN
$EndComp
Wire Wire Line
9500 4800 9500 4750
Text Notes 3750 10300 0 50 ~ 0
TODO: wire up port power switches
$Comp
L Device:R_Small R60
U 1 1 5DB86F24
@@ -2388,4 +2386,23 @@ Wire Wire Line
Connection ~ 13050 1950
Wire Wire Line
11300 1750 11300 2300
Text GLabel 9000 1100 0 50 Input ~ 0
USB_PWR
$Comp
L power:+5V #PWR0126
U 1 1 5DBF4AD4
P 9200 1000
F 0 "#PWR0126" H 9200 850 50 0001 C CNN
F 1 "+5V" H 9215 1173 50 0000 C CNN
F 2 "" H 9200 1000 50 0001 C CNN
F 3 "" H 9200 1000 50 0001 C CNN
1 9200 1000
1 0 0 -1
$EndComp
Wire Wire Line
9200 1000 9200 1100
Wire Wire Line
9200 1100 9000 1100
Text Notes 1350 8150 0 50 ~ 0
TODO: get rid of these?!
$EndSCHEMATC

+ 92
- 92
reform2-motherboard/reform2-motherboard/reform2.lib View File

@@ -253,124 +253,123 @@ F3 "" -350 2700 50 H I C CNN
DRAW
S -850 4850 700 -5450 0 1 0 f
X GND 1 -950 4750 100 R 50 50 1 1 W
X VSYS 10 800 4350 100 L 50 50 1 1 O
X VSYS 10 800 4350 100 L 50 50 1 1 W
X QSPI_A_SS1_B 100 800 -150 100 L 50 50 1 1 O
X CSI_P1_DP2 101 -950 -150 100 R 50 50 1 1 O
X CSI_P1_DP2 101 -950 -250 100 R 50 50 1 1 O
X QSPI_A_DQS 102 800 -250 100 L 50 50 1 1 O
X CSI_P1_DN2 103 -950 -250 100 R 50 50 1 1 O
X CSI_P1_DN2 103 -950 -350 100 R 50 50 1 1 O
X QSPI_A_SCLK 104 800 -350 100 L 50 50 1 1 O
X GND 105 -950 -350 100 R 50 50 1 1 O
X GND 105 -950 -450 100 R 50 50 1 1 W
X SAI1_RX_SYNC 106 800 -450 100 L 50 50 1 1 O
X CSI_P1_CKP 107 -950 -450 100 R 50 50 1 1 O
X CSI_P1_CKP 107 -950 -550 100 R 50 50 1 1 O
X SAI1_MCLK 108 800 -550 100 L 50 50 1 1 O
X CSI_P1_CKN 109 -950 -550 100 R 50 50 1 1 O
X ECSPI1_MOSI 11 -950 4250 100 R 50 50 1 1 W
X CSI_P1_CKN 109 -950 -650 100 R 50 50 1 1 O
X ECSPI1_MOSI 11 -950 4250 100 R 50 50 1 1 O
X SAI1_TX_SYNC 110 800 -650 100 L 50 50 1 1 O
X UART3_TX 111 -950 -650 100 R 50 50 1 1 O
X UART3_TX 111 -950 -750 100 R 50 50 1 1 O
X SAI1_TX_BCLK 112 800 -750 100 L 50 50 1 1 O
X CSI_P1_DN3 113 -950 -750 100 R 50 50 1 1 O
X VSYS 114 800 -850 100 L 50 50 1 1 O
X CSI_P1_DP3 115 -950 -850 100 R 50 50 1 1 O
X CSI_P1_DN3 113 -950 -850 100 R 50 50 1 1 O
X VSYS 114 800 -850 100 L 50 50 1 1 W
X CSI_P1_DP3 115 -950 -950 100 R 50 50 1 1 O
X SAI1_TX_DATA[0] 116 800 -950 100 L 50 50 1 1 O
X UART3_RX 117 -950 -950 100 R 50 50 1 1 O
X UART3_RX 117 -950 -1050 100 R 50 50 1 1 O
X SAI1_TX_DATA[1] 118 800 -1050 100 L 50 50 1 1 O
X PCIE1_REF_CLKP 119 -950 -1050 100 R 50 50 1 1 O
X PCIE1_REF_CLKP 119 -950 -1150 100 R 50 50 1 1 O
X ETH1_MDI1N 12 800 4250 100 L 50 50 1 1 O
X SAI1_TX_DATA[2] 120 800 -1150 100 L 50 50 1 1 O
X PCIE1_REF_CLKN 121 -950 -1150 100 R 50 50 1 1 O
X PCIE1_REF_CLKN 121 -950 -1250 100 R 50 50 1 1 O
X SAI1_TX_DATA[3] 122 800 -1250 100 L 50 50 1 1 O
X GND 123 -950 -1250 100 R 50 50 1 1 O
X GND 123 -950 -1350 100 R 50 50 1 1 W
X GPIO3_IO[16] 124 800 -1350 100 L 50 50 1 1 O
X PCIE1_TXN_P 125 -950 -1350 100 R 50 50 1 1 O
X PCIE1_TXN_P 125 -950 -1450 100 R 50 50 1 1 O
X SAI1_TX_DATA[3] 126 800 -1450 100 L 50 50 1 1 O
X PCIE1_TXN_N 127 -950 -1450 100 R 50 50 1 1 O
X PCIE1_TXN_N 127 -950 -1550 100 R 50 50 1 1 O
X SAI1_TX_DATA[4] 128 800 -1550 100 L 50 50 1 1 O
X ENET1_MDC 129 -950 -1550 100 R 50 50 1 1 O
X ECSPI1_SCLK 13 -950 4150 100 R 50 50 1 1 W
X ENET1_MDC 129 -950 -1650 100 R 50 50 1 1 O
X ECSPI1_SCLK 13 -950 4150 100 R 50 50 1 1 O
X SAI1_TX_DATA[7] 130 800 -1650 100 L 50 50 1 1 O
X PCIE1_RXN_P 131 -950 -1650 100 R 50 50 1 1 O
X VSYS 132 800 -1750 100 L 50 50 1 1 O
X PCIE1_RXN_N 133 -950 -1750 100 R 50 50 1 1 O
X PCIE1_RXN_P 131 -950 -1750 100 R 50 50 1 1 O
X VSYS 132 800 -1750 100 L 50 50 1 1 W
X PCIE1_RXN_N 133 -950 -1850 100 R 50 50 1 1 O
X SAI1_RX_DATA[0] 134 800 -1850 100 L 50 50 1 1 O
X ENET1_MDIO 135 -950 -1850 100 R 50 50 1 1 O
X ENET1_MDIO 135 -950 -1950 100 R 50 50 1 1 O
X SAI1_RX_DATA[1] 136 800 -1950 100 L 50 50 1 1 O
X SAI1_RX_DATA[4] 137 -950 -1950 100 R 50 50 1 1 O
X SAI1_RX_DATA[4] 137 -950 -2050 100 R 50 50 1 1 O
X SAI1_RX_DATA[2] 138 800 -2050 100 L 50 50 1 1 O
X SAI1_RX_DATA[5] 139 -950 -2050 100 R 50 50 1 1 O
X SAI1_TX_DATA[5] 139 -950 -2250 100 R 50 50 1 1 O
X SAI1_RX_DATA[5] 139 -950 -2150 100 R 50 50 1 1 O
X ETH1_MDI1P 14 800 4150 100 L 50 50 1 1 O
X SAI1_RX_DATA[3] 140 800 -2150 100 L 50 50 1 1 O
X GND 141 -950 -2350 100 R 50 50 1 1 O
X GND 141 -950 -2150 100 R 50 50 1 1 O
X GND 141 -950 -2250 100 R 50 50 1 1 W
X SAI1_TX_BCLK 142 800 -2250 100 L 50 50 1 1 O
X SAI1_TX_DATA[5] 143 -950 -2450 100 R 50 50 1 1 O
X SAI1_TX_DATA[5] 143 -950 -2350 100 R 50 50 1 1 O
X SAI1_TX_DATA[0] 144 800 -2350 100 L 50 50 1 1 O
X SAI1_RX_DATA[6] 145 -950 -2550 100 R 50 50 1 1 O
X SAI1_RX_DATA[6] 145 -950 -2450 100 R 50 50 1 1 O
X SAI1_TX_DATA[1] 146 800 -2450 100 L 50 50 1 1 O
X QSPI_B_SCLK 147 -950 -2650 100 R 50 50 1 1 O
X QSPI_B_SCLK 147 -950 -2550 100 R 50 50 1 1 O
X SAI1_TX_DATA[2] 148 800 -2550 100 L 50 50 1 1 O
X QSPI_B_DATA[3] 149 -950 -2750 100 R 50 50 1 1 O
X ECSPI1_MISO 15 -950 4050 100 R 50 50 1 1 W
X VSYS 150 800 -2650 100 L 50 50 1 1 O
X QSPI_B_DATA[2] 151 -950 -2850 100 R 50 50 1 1 O
X QSPI_B_DATA[3] 149 -950 -2650 100 R 50 50 1 1 O
X ECSPI1_MISO 15 -950 4050 100 R 50 50 1 1 O
X VSYS 150 800 -2650 100 L 50 50 1 1 W
X QSPI_B_DATA[2] 151 -950 -2750 100 R 50 50 1 1 O
X SAI1_RX_DATA[7] 152 800 -2750 100 L 50 50 1 1 O
X QSPI_B_DATA[1] 153 -950 -2950 100 R 50 50 1 1 O
X QSPI_B_DATA[1] 153 -950 -2850 100 R 50 50 1 1 O
X USDHC2_RESET_B 154 800 -2850 100 L 50 50 1 1 O
X QSPI_B_DATA[0] 155 -950 -3050 100 R 50 50 1 1 O
X QSPI_B_DATA[0] 155 -950 -2950 100 R 50 50 1 1 O
X USB2_VBUS_DET 156 800 -2950 100 L 50 50 1 1 O
X QSPI_B_DQS 157 -950 -3150 100 R 50 50 1 1 O
X QSPI_B_DQS 157 -950 -3050 100 R 50 50 1 1 O
X USB2_RX_P 158 800 -3050 100 L 50 50 1 1 O
X GND 159 -950 -3250 100 R 50 50 1 1 O
X GND 159 -950 -3150 100 R 50 50 1 1 W
X ETH1_LED1_SPD 16 800 4050 100 L 50 50 1 1 O
X USB2_RX_N 160 800 -3150 100 L 50 50 1 1 O
X LVDS1_TX3_P 161 -950 -3350 100 R 50 50 1 1 O
X LVDS1_TX3_P 161 -950 -3250 100 R 50 50 1 1 O
X SAI1_TX_DATA[6] 162 800 -3250 100 L 50 50 1 1 O
X LVDS1_TX3_N 163 -950 -3450 100 R 50 50 1 1 O
X LVDS1_TX3_N 163 -950 -3350 100 R 50 50 1 1 O
X USB2_TX_P 164 800 -3350 100 L 50 50 1 1 O
X ONOFF 165 -950 -3550 100 R 50 50 1 1 O
X ONOFF 165 -950 -3450 100 R 50 50 1 1 O
X USB2_TX_N 166 800 -3450 100 L 50 50 1 1 O
X PCIE2_RXN_N 167 -950 -3650 100 R 50 50 1 1 O
X VSYS 168 800 -3550 100 L 50 50 1 1 O
X PCIE2_RXN_P 169 -950 -3750 100 R 50 50 1 1 O
X ECSPI1_SS0 17 -950 3950 100 R 50 50 1 1 W
X PCIE2_RXN_N 167 -950 -3550 100 R 50 50 1 1 O
X VSYS 168 800 -3550 100 L 50 50 1 1 W
X PCIE2_RXN_P 169 -950 -3650 100 R 50 50 1 1 O
X ECSPI1_SS0 17 -950 3950 100 R 50 50 1 1 O
X USB2_DN 170 800 -3650 100 L 50 50 1 1 O
X COLD_RESET_IN 171 -950 -3850 100 R 50 50 1 1 O
X COLD_RESET_IN 171 -950 -3750 100 R 50 50 1 1 O
X USB2_DP 172 800 -3750 100 L 50 50 1 1 O
X PCIE2_TXN_N 173 -950 -3950 100 R 50 50 1 1 O
X PCIE2_TXN_N 173 -950 -3850 100 R 50 50 1 1 O
X USB1_ID 174 800 -3850 100 L 50 50 1 1 O
X PCIE2_TXN_P 175 -950 -4050 100 R 50 50 1 1 O
X PCIE2_TXN_P 175 -950 -3950 100 R 50 50 1 1 O
X USB1_DP 176 800 -3950 100 L 50 50 1 1 O
X GND 177 -950 -4150 100 R 50 50 1 1 O
X GND 177 -950 -4050 100 R 50 50 1 1 W
X USB1_DN 178 800 -4050 100 L 50 50 1 1 O
X PCIE2_REF_CLKN 179 -950 -4250 100 R 50 50 1 1 O
X PCIE2_REF_CLKN 179 -950 -4150 100 R 50 50 1 1 O
X ETH1_MDI2N 18 800 3950 100 L 50 50 1 1 O
X USB1_VBUS_DET 180 800 -4150 100 L 50 50 1 1 O
X PCIE2_REF_CLKP 181 -950 -4350 100 R 50 50 1 1 O
X PCIE2_REF_CLKP 181 -950 -4250 100 R 50 50 1 1 O
X USB1_RX_P 182 800 -4250 100 L 50 50 1 1 O
X VCC_RTC 183 -950 -4450 100 R 50 50 1 1 O
X VCC_RTC 183 -950 -4350 100 R 50 50 1 1 O
X USB1_RX_N 184 800 -4350 100 L 50 50 1 1 O
X ALT_BOOT 185 -950 -4550 100 R 50 50 1 1 O
X ALT_BOOT 185 -950 -4450 100 R 50 50 1 1 O
X VSYS 186 800 -4450 100 L 50 50 1 1 O
X NC 187 -950 -4650 100 R 50 50 1 1 O
X NC 187 -950 -4550 100 R 50 50 1 1 N
X USB1_TX_P 188 800 -4550 100 L 50 50 1 1 O
X EEPROM_WP 189 -950 -4750 100 R 50 50 1 1 O
X EEPROM_WP 189 -950 -4650 100 R 50 50 1 1 O
X GND 19 -950 3850 100 R 50 50 1 1 W
X USB1_TX_N 190 800 -4650 100 L 50 50 1 1 O
X MICBIAS 191 -950 -4850 100 R 50 50 1 1 O
X SAI2_MCLK 191 -950 -4750 100 R 50 50 1 1 O
X SAI1_RX_BCLK 192 800 -4750 100 L 50 50 1 1 O
X MICIN 193 -950 -4950 100 R 50 50 1 1 O
X MICIN 193 -950 -4850 100 R 50 50 1 1 O
X SAI1_TX_DATA[4] 194 800 -4850 100 L 50 50 1 1 O
X AUD_GND 195 -950 -5050 100 R 50 50 1 1 O
X AUD_GND 195 -950 -4950 100 R 50 50 1 1 P
X PWM3_OUT 196 800 -4950 100 L 50 50 1 1 O
X SAI2_TX_BCLK 197 -950 -5150 100 R 50 50 1 1 O
X SAI2_TX_BCLK 197 -950 -5050 100 R 50 50 1 1 O
X PWM2_OUT 198 800 -5050 100 L 50 50 1 1 O
X AVDD33_ETH 2 800 4750 100 L 50 50 1 1 O
X SAI2_TX_SYNC 199 -950 -5150 100 R 50 50 1 1 I
X AVDD33_ETH 2 800 4750 100 L 50 50 1 1 w
X ETH1_MDI2P 20 800 3850 100 L 50 50 1 1 O
X PWM1_OUT 200 800 -5150 100 L 50 50 1 1 O
X SAI2_TX_SYNC 201 -950 -5250 100 R 50 50 1 1 O
X SAI2_TX_DATA[0] 201 -950 -5250 100 R 50 50 1 1 O
X PMIC_ON_REQ 202 800 -5250 100 L 50 50 1 1 O
X SAI2_RX_DATA[0] 203 -950 -5350 100 R 50 50 1 1 O
X VSYS 204 800 -5350 100 L 50 50 1 1 O
X VSYS 204 800 -5350 100 L 50 50 1 1 W
X LVDS1_TX0_P 21 -950 3750 100 R 50 50 1 1 O
X ETH1_LED3 22 800 3750 100 L 50 50 1 1 O
X LVDS1_TX0_N 23 -950 3650 100 R 50 50 1 1 O
@@ -378,9 +377,9 @@ X ETH1_MDI3N 24 800 3650 100 L 50 50 1 1 O
X HDMI_DDC_SCL 25 -950 3550 100 R 50 50 1 1 O
X ETH1_MDI3P 26 800 3550 100 L 50 50 1 1 O
X HDMI_AUXN 27 -950 3450 100 R 50 50 1 1 O
X VSYS 28 800 3450 100 L 50 50 1 1 O
X VSYS 28 800 3450 100 L 50 50 1 1 W
X HDMI_AUXP 29 -950 3350 100 R 50 50 1 1 O
X PCIE2_CLKREQ_B 3 -950 4650 100 R 50 50 1 1 W
X PCIE2_CLKREQ_B 3 -950 4650 100 R 50 50 1 1 O
X HDMI_CLKP 30 800 3350 100 L 50 50 1 1 O
X HDMI_DDC_SDA 31 -950 3250 100 R 50 50 1 1 O
X HDMI_CLKN 32 800 3250 100 L 50 50 1 1 O
@@ -388,7 +387,7 @@ X DSI_DP2 33 -950 3150 100 R 50 50 1 1 O
X HDMI_CEC 34 800 3150 100 L 50 50 1 1 O
X DSI_DN2 35 -950 3050 100 R 50 50 1 1 O
X HDMI_TXP0 36 800 3050 100 L 50 50 1 1 O
X GND 37 -950 2950 100 R 50 50 1 1 O
X GND 37 -950 2950 100 R 50 50 1 1 W
X HDMI_TXN0 38 800 2950 100 L 50 50 1 1 O
X DSI_DP0 39 -950 2850 100 R 50 50 1 1 O
X ETH1_LED_ACT 4 800 4650 100 L 50 50 1 1 O
@@ -398,17 +397,17 @@ X HDMI_TXP1 42 800 2750 100 L 50 50 1 1 O
X I2C3_SCL 43 -950 2650 100 R 50 50 1 1 O
X HDMI_TXN1 44 800 2650 100 L 50 50 1 1 O
X DSI_DP1 45 -950 2550 100 R 50 50 1 1 O
X VSYS 46 800 2550 100 L 50 50 1 1 O
X VSYS 46 800 2550 100 L 50 50 1 1 W
X DSI_DN1 47 -950 2450 100 R 50 50 1 1 O
X HDMI_TXP2 48 800 2450 100 L 50 50 1 1 O
X I2C3_SDA 49 -950 2350 100 R 50 50 1 1 O
X PCIE1_CLKREQ_B 5 -950 4550 100 R 50 50 1 1 W
X PCIE1_CLKREQ_B 5 -950 4550 100 R 50 50 1 1 O
X HDMI_TXN2 50 800 2350 100 L 50 50 1 1 O
X DSI_DP3 51 -950 2250 100 R 50 50 1 1 O
X ENET1_MDC 52 800 2250 100 L 50 50 1 1 O
X DSI_DN3 53 -950 2150 100 R 50 50 1 1 O
X JTAG_MOD 54 800 2150 100 L 50 50 1 1 O
X GND 55 -950 2050 100 R 50 50 1 1 O
X GND 55 -950 2050 100 R 50 50 1 1 W
X JTAG_NTRST 56 800 2050 100 L 50 50 1 1 O
X DSI_CKN 57 -950 1950 100 R 50 50 1 1 O
X UART2_TX 58 800 1950 100 L 50 50 1 1 O
@@ -417,45 +416,46 @@ X ETH1_MDI0N 6 800 4550 100 L 50 50 1 1 O
X GPIO3_IO[17] 60 800 1850 100 L 50 50 1 1 O
X USDHC2_CD_B 61 -950 1750 100 R 50 50 1 1 O
X GPIO1_IO[19] 62 800 1750 100 L 50 50 1 1 O
X VSYS 64 800 1650 100 L 50 50 1 1 O
X ECSPI3_MISO 65 -950 1650 100 R 50 50 1 1 O
X UART2_RX 63 -950 1650 100 R 50 50 1 1 O
X VSYS 64 800 1650 100 L 50 50 1 1 W
X ECSPI3_MISO 65 -950 1550 100 R 50 50 1 1 O
X JTAG_TCK 66 800 1550 100 L 50 50 1 1 O
X USDHC2_WP 67 -950 1550 100 R 50 50 1 1 O
X USDHC2_WP 67 -950 1450 100 R 50 50 1 1 O
X JTAG_TMS 68 800 1450 100 L 50 50 1 1 O
X ECSPI3_SCLK 69 -950 1450 100 R 50 50 1 1 O
X QSPI_BSS0_B 7 -950 4450 100 R 50 50 1 1 W
X ECSPI3_SCLK 69 -950 1350 100 R 50 50 1 1 O
X QSPI_BSS0_B 7 -950 4450 100 R 50 50 1 1 O
X JTAG_TDI 70 800 1350 100 L 50 50 1 1 O
X GND 71 -950 1350 100 R 50 50 1 1 O
X GND 71 -950 1250 100 R 50 50 1 1 W
X JTAG_TDO 72 800 1250 100 L 50 50 1 1 O
X PCIE1_CLKREQ_B 73 -950 1250 100 R 50 50 1 1 O
X I2C4_SCL 73 -950 1150 100 R 50 50 1 1 O
X QSPI_A_DATA[0] 74 800 1150 100 L 50 50 1 1 O
X PCIE2_CLKREQ_B 75 -950 1150 100 R 50 50 1 1 O
X I2C4_SDA 75 -950 1050 100 R 50 50 1 1 O
X QSPI_A_DATA[1] 76 800 1050 100 L 50 50 1 1 O
X LVDS1_CLK_P 77 -950 1050 100 R 50 50 1 1 O
X VSYS 78 800 950 100 L 50 50 1 1 O
X LVDS1_CLK_N 79 -950 950 100 R 50 50 1 1 O
X LVDS1_CLK_P 77 -950 950 100 R 50 50 1 1 O
X VSYS 78 800 950 100 L 50 50 1 1 W
X LVDS1_CLK_N 79 -950 850 100 R 50 50 1 1 O
X ETH1_MDI0P 8 800 4450 100 L 50 50 1 1 O
X USDHC2_CLK 80 800 850 100 L 50 50 1 1 O
X GPIO3_IO[18] 81 -950 850 100 R 50 50 1 1 O
X GPIO3_IO[18] 81 -950 750 100 R 50 50 1 1 O
X USDHC2_CMD 82 800 750 100 L 50 50 1 1 O
X CSI_P1_DP0 83 -950 750 100 R 50 50 1 1 O
X CSI_P1_DP0 83 -950 650 100 R 50 50 1 1 O
X USDHC2_DATA0 84 800 650 100 L 50 50 1 1 O
X CSI_P1_DN0 85 -950 650 100 R 50 50 1 1 O
X CSI_P1_DN0 85 -950 550 100 R 50 50 1 1 O
X USDHC2_DATA1 86 800 550 100 L 50 50 1 1 O
X GND 87 -950 550 100 R 50 50 1 1 O
X GND 87 -950 450 100 R 50 50 1 1 W
X USDHC2_DATA2 88 800 450 100 L 50 50 1 1 O
X CSI_P1_DP1 89 -950 450 100 R 50 50 1 1 O
X QSPI_B_SS1_B 9 -950 4350 100 R 50 50 1 1 W
X CSI_P1_DP1 89 -950 350 100 R 50 50 1 1 O
X QSPI_B_SS1_B 9 -950 4350 100 R 50 50 1 1 O
X USDHC2_DATA3 90 800 350 100 L 50 50 1 1 O
X CSI_P1_DN1 91 -950 350 100 R 50 50 1 1 O
X CSI_P1_DN1 91 -950 250 100 R 50 50 1 1 O
X QSPI_A_DATA[2] 92 800 250 100 L 50 50 1 1 O
X LVDS1_TX1_P 93 -950 250 100 R 50 50 1 1 O
X LVDS1_TX1_P 93 -950 150 100 R 50 50 1 1 O
X QSPI_A_DATA[3] 94 800 150 100 L 50 50 1 1 O
X LVDS1_TX1_N 95 -950 150 100 R 50 50 1 1 O
X VSYS 96 800 50 100 L 50 50 1 1 O
X LVDS1_TX2_P 97 -950 50 100 R 50 50 1 1 O
X LVDS1_TX1_N 95 -950 50 100 R 50 50 1 1 O
X VSYS 96 800 50 100 L 50 50 1 1 W
X LVDS1_TX2_P 97 -950 -50 100 R 50 50 1 1 O
X QSPI_A_SS0_B 98 800 -50 100 L 50 50 1 1 O
X LVDS1_TX2_N 99 -950 -50 100 R 50 50 1 1 O
X LVDS1_TX2_N 99 -950 -150 100 R 50 50 1 1 O
ENDDRAW
ENDDEF
#


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