Fork of the vendor (Boundary Devices) u-boot for Reform 2, with minor tweaks. The goal is to migrate to mainstream u-boot or barebox ASAP. The main impediment so far is the 4GB RAM config.
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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  6. * Contributor: Mahavir Jain <mjain@marvell.com>
  7. */
  8. #include <common.h>
  9. #include <asm/arch/cpu.h>
  10. #include <asm/arch/armada100.h>
  11. /*
  12. * Timer registers
  13. * Refer Section A.6 in Datasheet
  14. */
  15. struct armd1tmr_registers {
  16. u32 clk_ctrl; /* Timer clk control reg */
  17. u32 match[9]; /* Timer match registers */
  18. u32 count[3]; /* Timer count registers */
  19. u32 status[3];
  20. u32 ie[3];
  21. u32 preload[3]; /* Timer preload value */
  22. u32 preload_ctrl[3];
  23. u32 wdt_match_en;
  24. u32 wdt_match_r;
  25. u32 wdt_val;
  26. u32 wdt_sts;
  27. u32 icr[3];
  28. u32 wdt_icr;
  29. u32 cer; /* Timer count enable reg */
  30. u32 cmr;
  31. u32 ilr[3];
  32. u32 wcr;
  33. u32 wfar;
  34. u32 wsar;
  35. u32 cvwr;
  36. };
  37. #define TIMER 0 /* Use TIMER 0 */
  38. /* Each timer has 3 match registers */
  39. #define MATCH_CMP(x) ((3 * TIMER) + x)
  40. #define TIMER_LOAD_VAL 0xffffffff
  41. #define COUNT_RD_REQ 0x1
  42. DECLARE_GLOBAL_DATA_PTR;
  43. /* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
  44. /* For preventing risk of instability in reading counter value,
  45. * first set read request to register cvwr and then read same
  46. * register after it captures counter value.
  47. */
  48. ulong read_timer(void)
  49. {
  50. struct armd1tmr_registers *armd1timers =
  51. (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
  52. volatile int loop=100;
  53. writel(COUNT_RD_REQ, &armd1timers->cvwr);
  54. while (loop--);
  55. return(readl(&armd1timers->cvwr));
  56. }
  57. ulong get_timer_masked(void)
  58. {
  59. ulong now = read_timer();
  60. if (now >= gd->arch.tbl) {
  61. /* normal mode */
  62. gd->arch.tbu += now - gd->arch.tbl;
  63. } else {
  64. /* we have an overflow ... */
  65. gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
  66. }
  67. gd->arch.tbl = now;
  68. return gd->arch.tbu;
  69. }
  70. ulong get_timer(ulong base)
  71. {
  72. return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
  73. base);
  74. }
  75. void __udelay(unsigned long usec)
  76. {
  77. ulong delayticks;
  78. ulong endtime;
  79. delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
  80. endtime = get_timer_masked() + delayticks;
  81. while (get_timer_masked() < endtime);
  82. }
  83. /*
  84. * init the Timer
  85. */
  86. int timer_init(void)
  87. {
  88. struct armd1apb1_registers *apb1clkres =
  89. (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
  90. struct armd1tmr_registers *armd1timers =
  91. (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
  92. /* Enable Timer clock at 3.25 MHZ */
  93. writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
  94. /* load value into timer */
  95. writel(0x0, &armd1timers->clk_ctrl);
  96. /* Use Timer 0 Match Resiger 0 */
  97. writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
  98. /* Preload value is 0 */
  99. writel(0x0, &armd1timers->preload[TIMER]);
  100. /* Enable match comparator 0 for Timer 0 */
  101. writel(0x1, &armd1timers->preload_ctrl[TIMER]);
  102. /* Enable timer 0 */
  103. writel(0x1, &armd1timers->cer);
  104. /* init the gd->arch.tbu and gd->arch.tbl value */
  105. gd->arch.tbl = read_timer();
  106. gd->arch.tbu = 0;
  107. return 0;
  108. }
  109. #define MPMU_APRR_WDTR (1<<4)
  110. #define TMR_WFAR 0xbaba /* WDT Register First key */
  111. #define TMP_WSAR 0xeb10 /* WDT Register Second key */
  112. /*
  113. * This function uses internal Watchdog Timer
  114. * based reset mechanism.
  115. * Steps to write watchdog registers (protected access)
  116. * 1. Write key value to TMR_WFAR reg.
  117. * 2. Write key value to TMP_WSAR reg.
  118. * 3. Perform write operation.
  119. */
  120. void reset_cpu (unsigned long ignored)
  121. {
  122. struct armd1mpmu_registers *mpmu =
  123. (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
  124. struct armd1tmr_registers *armd1timers =
  125. (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
  126. u32 val;
  127. /* negate hardware reset to the WDT after system reset */
  128. val = readl(&mpmu->aprr);
  129. val = val | MPMU_APRR_WDTR;
  130. writel(val, &mpmu->aprr);
  131. /* reset/enable WDT clock */
  132. writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
  133. readl(&mpmu->wdtpcr);
  134. writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
  135. readl(&mpmu->wdtpcr);
  136. /* clear previous WDT status */
  137. writel(TMR_WFAR, &armd1timers->wfar);
  138. writel(TMP_WSAR, &armd1timers->wsar);
  139. writel(0, &armd1timers->wdt_sts);
  140. /* set match counter */
  141. writel(TMR_WFAR, &armd1timers->wfar);
  142. writel(TMP_WSAR, &armd1timers->wsar);
  143. writel(0xf, &armd1timers->wdt_match_r);
  144. /* enable WDT reset */
  145. writel(TMR_WFAR, &armd1timers->wfar);
  146. writel(TMP_WSAR, &armd1timers->wsar);
  147. writel(0x3, &armd1timers->wdt_match_en);
  148. while(1);
  149. }
  150. /*
  151. * This function is derived from PowerPC code (read timebase as long long).
  152. * On ARM it just returns the timer value.
  153. */
  154. unsigned long long get_ticks(void)
  155. {
  156. return get_timer(0);
  157. }
  158. /*
  159. * This function is derived from PowerPC code (timebase clock frequency).
  160. * On ARM it returns the number of timer ticks per second.
  161. */
  162. ulong get_tbclk (void)
  163. {
  164. return (ulong)CONFIG_SYS_HZ;
  165. }