Fork of the vendor (Boundary Devices) u-boot for Reform 2, with minor tweaks. The goal is to migrate to mainstream u-boot or barebox ASAP. The main impediment so far is the 4GB RAM config.
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
This repo is archived. You can view files and clone it, but cannot push or open issues/pull-requests.
 
 
 
 
 
 

116 lines
2.5 KiB

  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
  6. * Contributor: Mahavir Jain <mjain@marvell.com>
  7. */
  8. #include <common.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/armada100.h>
  11. DECLARE_GLOBAL_DATA_PTR;
  12. /*
  13. * ARMADA100 DRAM controller supports upto 8 banks
  14. * for chip select 0 and 1
  15. */
  16. /*
  17. * DDR Memory Control Registers
  18. * Refer Datasheet Appendix A.17
  19. */
  20. struct armd1ddr_map_registers {
  21. u32 cs; /* Memory Address Map Register -CS */
  22. u32 pad[3];
  23. };
  24. struct armd1ddr_registers {
  25. u8 pad[0x100 - 0x000];
  26. struct armd1ddr_map_registers mmap[2];
  27. };
  28. /*
  29. * armd1_sdram_base - reads SDRAM Base Address Register
  30. */
  31. u32 armd1_sdram_base(int chip_sel)
  32. {
  33. struct armd1ddr_registers *ddr_regs =
  34. (struct armd1ddr_registers *)ARMD1_DRAM_BASE;
  35. u32 result = 0;
  36. u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
  37. if (!CS_valid)
  38. return 0;
  39. result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
  40. return result;
  41. }
  42. /*
  43. * armd1_sdram_size - reads SDRAM size
  44. */
  45. u32 armd1_sdram_size(int chip_sel)
  46. {
  47. struct armd1ddr_registers *ddr_regs =
  48. (struct armd1ddr_registers *)ARMD1_DRAM_BASE;
  49. u32 result = 0;
  50. u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
  51. if (!CS_valid)
  52. return 0;
  53. result = readl(&ddr_regs->mmap[chip_sel].cs);
  54. result = (result >> 16) & 0xF;
  55. if (result < 0x7) {
  56. printf("Unknown DRAM Size\n");
  57. return -1;
  58. } else {
  59. return ((0x8 << (result - 0x7)) * 1024 * 1024);
  60. }
  61. }
  62. int dram_init(void)
  63. {
  64. int i;
  65. gd->ram_size = 0;
  66. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  67. gd->bd->bi_dram[i].start = armd1_sdram_base(i);
  68. gd->bd->bi_dram[i].size = armd1_sdram_size(i);
  69. /*
  70. * It is assumed that all memory banks are consecutive
  71. * and without gaps.
  72. * If the gap is found, ram_size will be reported for
  73. * consecutive memory only
  74. */
  75. if (gd->bd->bi_dram[i].start != gd->ram_size)
  76. break;
  77. gd->ram_size += gd->bd->bi_dram[i].size;
  78. }
  79. for (; i < CONFIG_NR_DRAM_BANKS; i++) {
  80. /* If above loop terminated prematurely, we need to set
  81. * remaining banks' start address & size as 0. Otherwise other
  82. * u-boot functions and Linux kernel gets wrong values which
  83. * could result in crash */
  84. gd->bd->bi_dram[i].start = 0;
  85. gd->bd->bi_dram[i].size = 0;
  86. }
  87. return 0;
  88. }
  89. /*
  90. * If this function is not defined here,
  91. * board.c alters dram bank zero configuration defined above.
  92. */
  93. int dram_init_banksize(void)
  94. {
  95. dram_init();
  96. return 0;
  97. }