Fork of the vendor (Boundary Devices) u-boot for Reform 2, with minor tweaks. The goal is to migrate to mainstream u-boot or barebox ASAP. The main impediment so far is the 4GB RAM config.
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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  6. * Contributor: Mahavir Jain <mjain@marvell.com>
  7. */
  8. #include <common.h>
  9. #include <asm/arch/cpu.h>
  10. #include <asm/arch/armada100.h>
  11. #define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
  12. #define SET_MRVL_ID (1<<8)
  13. #define L2C_RAM_SEL (1<<4)
  14. int arch_cpu_init(void)
  15. {
  16. u32 val;
  17. struct armd1cpu_registers *cpuregs =
  18. (struct armd1cpu_registers *) ARMD1_CPU_BASE;
  19. struct armd1apb1_registers *apb1clkres =
  20. (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
  21. struct armd1mpmu_registers *mpmu =
  22. (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
  23. /* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
  24. val = readl(&cpuregs->cpu_conf);
  25. val = val | SET_MRVL_ID;
  26. writel(val, &cpuregs->cpu_conf);
  27. /* Enable Clocks for all hardware units */
  28. writel(0xFFFFFFFF, &mpmu->acgr);
  29. /* Turn on AIB and AIB-APB Functional clock */
  30. writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
  31. /* ensure L2 cache is not mapped as SRAM */
  32. val = readl(&cpuregs->cpu_conf);
  33. val = val & ~(L2C_RAM_SEL);
  34. writel(val, &cpuregs->cpu_conf);
  35. /* Enable GPIO clock */
  36. writel(APBC_APBCLK, &apb1clkres->gpio);
  37. #ifdef CONFIG_I2C_MV
  38. /* Enable general I2C clock */
  39. writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
  40. writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
  41. /* Enable power I2C clock */
  42. writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
  43. writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
  44. #endif
  45. /*
  46. * Enable Functional and APB clock at 14.7456MHz
  47. * for configured UART console
  48. */
  49. #if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
  50. writel(UARTCLK14745KHZ, &apb1clkres->uart3);
  51. #elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
  52. writel(UARTCLK14745KHZ, &apb1clkres->uart2);
  53. #else
  54. writel(UARTCLK14745KHZ, &apb1clkres->uart1);
  55. #endif
  56. icache_enable();
  57. return 0;
  58. }
  59. #if defined(CONFIG_DISPLAY_CPUINFO)
  60. int print_cpuinfo(void)
  61. {
  62. u32 id;
  63. struct armd1cpu_registers *cpuregs =
  64. (struct armd1cpu_registers *) ARMD1_CPU_BASE;
  65. id = readl(&cpuregs->chip_id);
  66. printf("SoC: Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
  67. return 0;
  68. }
  69. #endif
  70. #ifdef CONFIG_I2C_MV
  71. void i2c_clk_enable(void)
  72. {
  73. }
  74. #endif