Fork of the vendor (Boundary Devices) u-boot for Reform 2, with minor tweaks. The goal is to migrate to mainstream u-boot or barebox ASAP. The main impediment so far is the 4GB RAM config.
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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * armboot - Startup Code for ARM920 CPU-core
  4. *
  5. * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
  6. * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  7. * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
  8. */
  9. #include <asm-offsets.h>
  10. #include <common.h>
  11. #include <config.h>
  12. /*
  13. *************************************************************************
  14. *
  15. * Startup Code (called from the ARM reset exception vector)
  16. *
  17. * do important init only if we don't start from memory!
  18. * relocate armboot to ram
  19. * setup stack
  20. * jump to second stage
  21. *
  22. *************************************************************************
  23. */
  24. .globl reset
  25. reset:
  26. /*
  27. * set the cpu to SVC32 mode
  28. */
  29. mrs r0, cpsr
  30. bic r0, r0, #0x1f
  31. orr r0, r0, #0xd3
  32. msr cpsr, r0
  33. #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
  34. /*
  35. * relocate exception table
  36. */
  37. ldr r0, =_start
  38. ldr r1, =0x0
  39. mov r2, #16
  40. copyex:
  41. subs r2, r2, #1
  42. ldr r3, [r0], #4
  43. str r3, [r1], #4
  44. bne copyex
  45. #endif
  46. /*
  47. * we do sys-critical inits only at reboot,
  48. * not when booting from ram!
  49. */
  50. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  51. bl cpu_init_crit
  52. #endif
  53. bl _main
  54. /*------------------------------------------------------------------------------*/
  55. .globl c_runtime_cpu_setup
  56. c_runtime_cpu_setup:
  57. mov pc, lr
  58. /*
  59. *************************************************************************
  60. *
  61. * CPU_init_critical registers
  62. *
  63. * setup important registers
  64. * setup memory timing
  65. *
  66. *************************************************************************
  67. */
  68. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  69. cpu_init_crit:
  70. /*
  71. * flush v4 I/D caches
  72. */
  73. mov r0, #0
  74. mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
  75. mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
  76. /*
  77. * disable MMU stuff and caches
  78. */
  79. mrc p15, 0, r0, c1, c0, 0
  80. bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
  81. bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
  82. orr r0, r0, #0x00000002 @ set bit 1 (A) Align
  83. orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
  84. mcr p15, 0, r0, c1, c0, 0
  85. #ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
  86. /*
  87. * before relocating, we have to setup RAM timing
  88. * because memory timing is board-dependend, you will
  89. * find a lowlevel_init.S in your board directory.
  90. */
  91. mov ip, lr
  92. bl lowlevel_init
  93. mov lr, ip
  94. #endif
  95. mov pc, lr
  96. #endif /* CONFIG_SKIP_LOWLEVEL_INIT */