Fork of the vendor (Boundary Devices) u-boot for Reform 2, with minor tweaks. The goal is to migrate to mainstream u-boot or barebox ASAP. The main impediment so far is the 4GB RAM config.
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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Cirrus Logic EP93xx PLL support.
  4. *
  5. * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
  6. */
  7. #include <common.h>
  8. #include <asm/arch/ep93xx.h>
  9. #include <asm/io.h>
  10. #include <div64.h>
  11. /*
  12. * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
  13. *
  14. * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
  15. * the specified bus in HZ.
  16. */
  17. /*
  18. * return the PLL output frequency
  19. *
  20. * PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1)
  21. * / (X2IPD + 1) / 2^PS
  22. */
  23. static ulong get_PLLCLK(uint32_t *pllreg)
  24. {
  25. uint8_t i;
  26. const uint32_t clkset = readl(pllreg);
  27. uint64_t rate = CONFIG_SYS_CLK_FREQ;
  28. rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
  29. rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
  30. do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */
  31. for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++)
  32. rate >>= 1;
  33. return (ulong)rate;
  34. }
  35. /* return FCLK frequency */
  36. ulong get_FCLK(void)
  37. {
  38. const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
  39. struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
  40. const uint32_t clkset1 = readl(&syscon->clkset1);
  41. const uint8_t fclk_div =
  42. fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7];
  43. const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div;
  44. return fclk_rate;
  45. }
  46. /* return HCLK frequency */
  47. ulong get_HCLK(void)
  48. {
  49. const uint8_t hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
  50. struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
  51. const uint32_t clkset1 = readl(&syscon->clkset1);
  52. const uint8_t hclk_div =
  53. hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7];
  54. const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div;
  55. return hclk_rate;
  56. }
  57. /* return PCLK frequency */
  58. ulong get_PCLK(void)
  59. {
  60. const uint8_t pclk_divisors[] = { 1, 2, 4, 8 };
  61. struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
  62. const uint32_t clkset1 = readl(&syscon->clkset1);
  63. const uint8_t pclk_div =
  64. pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3];
  65. const ulong pclk_rate = get_HCLK() / pclk_div;
  66. return pclk_rate;
  67. }
  68. /* return UCLK frequency */
  69. ulong get_UCLK(void)
  70. {
  71. struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
  72. ulong uclk_rate;
  73. const uint32_t value = readl(&syscon->pwrcnt);
  74. if (value & SYSCON_PWRCNT_UART_BAUD)
  75. uclk_rate = CONFIG_SYS_CLK_FREQ;
  76. else
  77. uclk_rate = CONFIG_SYS_CLK_FREQ / 2;
  78. return uclk_rate;
  79. }