Fork of the vendor (Boundary Devices) u-boot for Reform 2, with minor tweaks. The goal is to migrate to mainstream u-boot or barebox ASAP. The main impediment so far is the 4GB RAM config.
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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Low-level initialization for EP93xx
  4. *
  5. * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
  6. * Copyright (C) 2013
  7. * Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru>
  8. *
  9. * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
  10. * Copyright (C) 2006 Cirrus Logic Inc.
  11. *
  12. * See file CREDITS for list of people who contributed to this
  13. * project.
  14. */
  15. #include <config.h>
  16. #include <asm/arch-ep93xx/ep93xx.h>
  17. /*
  18. /* Configure the SDRAM based on the supplied settings.
  19. *
  20. * Input: r0 - SDRAM DEVCFG register
  21. * r2 - configuration for SDRAM chips
  22. * Output: none
  23. * Modifies: r3, r4
  24. */
  25. ep93xx_sdram_config:
  26. /* Program the SDRAM device configuration register. */
  27. ldr r3, =SDRAM_BASE
  28. #ifdef CONFIG_EDB93XX_SDCS0
  29. str r0, [r3, #SDRAM_OFF_DEVCFG0]
  30. #endif
  31. #ifdef CONFIG_EDB93XX_SDCS1
  32. str r0, [r3, #SDRAM_OFF_DEVCFG1]
  33. #endif
  34. #ifdef CONFIG_EDB93XX_SDCS2
  35. str r0, [r3, #SDRAM_OFF_DEVCFG2]
  36. #endif
  37. #ifdef CONFIG_EDB93XX_SDCS3
  38. str r0, [r3, #SDRAM_OFF_DEVCFG3]
  39. #endif
  40. /* Set the Initialize and MRS bits (issue continuous NOP commands
  41. * (INIT & MRS set))
  42. */
  43. ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
  44. EP93XX_SDRAMCTRL_GLOBALCFG_MRS | \
  45. EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
  46. str r4, [r3, #SDRAM_OFF_GLCONFIG]
  47. /* Delay for 200us. */
  48. mov r4, #0x3000
  49. delay1:
  50. subs r4, r4, #1
  51. bne delay1
  52. /* Clear the MRS bit to issue a precharge all. */
  53. ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
  54. EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
  55. str r4, [r3, #SDRAM_OFF_GLCONFIG]
  56. /* Temporarily set the refresh timer to 0x10. Make it really low so
  57. * that refresh cycles are generated.
  58. */
  59. ldr r4, =0x10
  60. str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
  61. /* Delay for at least 80 SDRAM clock cycles. */
  62. mov r4, #80
  63. delay2:
  64. subs r4, r4, #1
  65. bne delay2
  66. /* Set the refresh timer to the fastest required for any device
  67. * that might be used. Set 9.6 ms refresh time.
  68. */
  69. ldr r4, =0x01e0
  70. str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
  71. /* Select mode register update mode. */
  72. ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_CKE | \
  73. EP93XX_SDRAMCTRL_GLOBALCFG_MRS)
  74. str r4, [r3, #SDRAM_OFF_GLCONFIG]
  75. /* Program the mode register on the SDRAM by performing fake read */
  76. ldr r4, [r2]
  77. /* Select normal operating mode. */
  78. ldr r4, =EP93XX_SDRAMCTRL_GLOBALCFG_CKE
  79. str r4, [r3, #SDRAM_OFF_GLCONFIG]
  80. /* Return to the caller. */
  81. mov pc, lr
  82. /*
  83. * Test to see if the SDRAM has been configured in a usable mode.
  84. *
  85. * Input: r0 - Test address of SDRAM
  86. * Output: r0 - 0 -- Test OK, -1 -- Failed
  87. * Modifies: r0-r5
  88. */
  89. ep93xx_sdram_test:
  90. /* Load the test patterns to be written to SDRAM. */
  91. ldr r1, =0xf00dface
  92. ldr r2, =0xdeadbeef
  93. ldr r3, =0x08675309
  94. ldr r4, =0xdeafc0ed
  95. /* Store the test patterns to SDRAM. */
  96. stmia r0, {r1-r4}
  97. /* Load the test patterns from SDRAM one at a time and compare them
  98. * to the actual pattern.
  99. */
  100. ldr r5, [r0]
  101. cmp r5, r1
  102. ldreq r5, [r0, #0x0004]
  103. cmpeq r5, r2
  104. ldreq r5, [r0, #0x0008]
  105. cmpeq r5, r3
  106. ldreq r5, [r0, #0x000c]
  107. cmpeq r5, r4
  108. /* Return -1 if a mismatch was encountered, 0 otherwise. */
  109. mvnne r0, #0xffffffff
  110. moveq r0, #0x00000000
  111. /* Return to the caller. */
  112. mov pc, lr
  113. /*
  114. * Determine the size of the SDRAM. Use data=address for the scan.
  115. *
  116. * Input: r0 - Start SDRAM address
  117. * Return: r0 - Single block size
  118. * r1 - Valid block mask
  119. * r2 - Total block count
  120. * Modifies: r0-r5
  121. */
  122. ep93xx_sdram_size:
  123. /* Store zero at offset zero. */
  124. str r0, [r0]
  125. /* Start checking for an alias at 1MB into SDRAM. */
  126. ldr r1, =0x00100000
  127. /* Store the offset at the current offset. */
  128. check_block_size:
  129. str r1, [r0, r1]
  130. /* Read back from zero. */
  131. ldr r2, [r0]
  132. /* Stop searching of an alias was found. */
  133. cmp r1, r2
  134. beq found_block_size
  135. /* Advance to the next power of two boundary. */
  136. mov r1, r1, lsl #1
  137. /* Loop back if the size has not reached 256MB. */
  138. cmp r1, #0x10000000
  139. bne check_block_size
  140. /* A full 256MB of memory was found, so return it now. */
  141. ldr r0, =0x10000000
  142. ldr r1, =0x00000000
  143. ldr r2, =0x00000001
  144. mov pc, lr
  145. /* An alias was found. See if the first block is 128MB in size. */
  146. found_block_size:
  147. cmp r1, #0x08000000
  148. /* The first block is 128MB, so there is no further memory. Return it
  149. * now.
  150. */
  151. ldreq r0, =0x08000000
  152. ldreq r1, =0x00000000
  153. ldreq r2, =0x00000001
  154. moveq pc, lr
  155. /* Save the block size, set the block address bits to zero, and
  156. * initialize the block count to one.
  157. */
  158. mov r3, r1
  159. ldr r4, =0x00000000
  160. ldr r5, =0x00000001
  161. /* Look for additional blocks of memory by searching for non-aliases. */
  162. find_blocks:
  163. /* Store zero back to address zero. It may be overwritten. */
  164. str r0, [r0]
  165. /* Advance to the next power of two boundary. */
  166. mov r1, r1, lsl #1
  167. /* Store the offset at the current offset. */
  168. str r1, [r0, r1]
  169. /* Read back from zero. */
  170. ldr r2, [r0]
  171. /* See if a non-alias was found. */
  172. cmp r1, r2
  173. /* If a non-alias was found, then or in the block address bit and
  174. * multiply the block count by two (since there are two unique
  175. * blocks, one with this bit zero and one with it one).
  176. */
  177. orrne r4, r4, r1
  178. movne r5, r5, lsl #1
  179. /* Continue searching if there are more address bits to check. */
  180. cmp r1, #0x08000000
  181. bne find_blocks
  182. /* Return the block size, address mask, and count. */
  183. mov r0, r3
  184. mov r1, r4
  185. mov r2, r5
  186. /* Return to the caller. */
  187. mov pc, lr
  188. .globl lowlevel_init
  189. lowlevel_init:
  190. mov r6, lr
  191. /* Make sure caches are off and invalidated. */
  192. ldr r0, =0x00000000
  193. mcr p15, 0, r0, c1, c0, 0
  194. nop
  195. nop
  196. nop
  197. nop
  198. nop
  199. /* Turn off the green LED and turn on the red LED. If the red LED
  200. * is left on for too long, the external reset circuit described
  201. * by application note AN258 will cause the system to reset.
  202. */
  203. ldr r1, =EP93XX_LED_DATA
  204. ldr r0, [r1]
  205. bic r0, r0, #EP93XX_LED_GREEN_ON
  206. orr r0, r0, #EP93XX_LED_RED_ON
  207. str r0, [r1]
  208. /* Undo the silly static memory controller programming performed
  209. * by the boot rom.
  210. */
  211. ldr r0, =SMC_BASE
  212. /* Set WST1 and WST2 to 31 HCLK cycles (slowest access) */
  213. ldr r1, =0x0000fbe0
  214. /* Reset EP93XX_OFF_SMCBCR0 */
  215. ldr r2, [r0]
  216. orr r2, r2, r1
  217. str r2, [r0]
  218. ldr r2, [r0, #EP93XX_OFF_SMCBCR1]
  219. orr r2, r2, r1
  220. str r2, [r0, #EP93XX_OFF_SMCBCR1]
  221. ldr r2, [r0, #EP93XX_OFF_SMCBCR2]
  222. orr r2, r2, r1
  223. str r2, [r0, #EP93XX_OFF_SMCBCR2]
  224. ldr r2, [r0, #EP93XX_OFF_SMCBCR3]
  225. orr r2, r2, r1
  226. str r2, [r0, #EP93XX_OFF_SMCBCR3]
  227. ldr r2, [r0, #EP93XX_OFF_SMCBCR6]
  228. orr r2, r2, r1
  229. str r2, [r0, #EP93XX_OFF_SMCBCR6]
  230. ldr r2, [r0, #EP93XX_OFF_SMCBCR7]
  231. orr r2, r2, r1
  232. str r2, [r0, #EP93XX_OFF_SMCBCR7]
  233. /* Set the PLL1 and processor clock. */
  234. ldr r0, =SYSCON_BASE
  235. #ifdef CONFIG_EDB9301
  236. /* 332MHz, giving a 166MHz processor clock. */
  237. ldr r1, = 0x02b49907
  238. #else
  239. #ifdef CONFIG_EDB93XX_INDUSTRIAL
  240. /* 384MHz, giving a 196MHz processor clock. */
  241. ldr r1, =0x02a4bb38
  242. #else
  243. /* 400MHz, giving a 200MHz processor clock. */
  244. ldr r1, =0x02a4e39e
  245. #endif
  246. #endif
  247. str r1, [r0, #SYSCON_OFF_CLKSET1]
  248. nop
  249. nop
  250. nop
  251. nop
  252. nop
  253. /* Need to make sure that SDRAM is configured correctly before
  254. * coping the code into it.
  255. */
  256. #ifdef CONFIG_EDB93XX_SDCS0
  257. mov r11, #SDRAM_DEVCFG0_BASE
  258. #endif
  259. #ifdef CONFIG_EDB93XX_SDCS1
  260. mov r11, #SDRAM_DEVCFG1_BASE
  261. #endif
  262. #ifdef CONFIG_EDB93XX_SDCS2
  263. mov r11, #SDRAM_DEVCFG2_BASE
  264. #endif
  265. #ifdef CONFIG_EDB93XX_SDCS3
  266. ldr r0, =SYSCON_BASE
  267. ldr r0, [r0, #SYSCON_OFF_SYSCFG]
  268. ands r0, r0, #SYSCON_SYSCFG_LASDO
  269. moveq r11, #SDRAM_DEVCFG3_ASD0_BASE
  270. movne r11, #SDRAM_DEVCFG3_ASD1_BASE
  271. #endif
  272. /* See Table 13-5 in EP93xx datasheet for more info about DRAM
  273. * register mapping */
  274. /* Try a 32-bit wide configuration of SDRAM. */
  275. ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
  276. EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
  277. EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
  278. EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2)
  279. /* Set burst count: 4 and CAS: 2
  280. * Burst mode [A11:A10]; CAS [A16:A14]
  281. */
  282. orr r2, r11, #0x00008800
  283. bl ep93xx_sdram_config
  284. /* Test the SDRAM. */
  285. mov r0, r11
  286. bl ep93xx_sdram_test
  287. cmp r0, #0x00000000
  288. beq ep93xx_sdram_done
  289. /* Try a 16-bit wide configuration of SDRAM. */
  290. ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
  291. EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
  292. EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
  293. EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 | \
  294. EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH)
  295. /* Set burst count: 8, CAS: 2, sequential burst
  296. * Accoring to Table 13-3 for 16bit operations mapping must be shifted.
  297. * Burst mode [A10:A9]; CAS [A15:A13]
  298. */
  299. orr r2, r11, #0x00004600
  300. bl ep93xx_sdram_config
  301. /* Test the SDRAM. */
  302. mov r0, r11
  303. bl ep93xx_sdram_test
  304. cmp r0, #0x00000000
  305. beq ep93xx_sdram_done
  306. /* Turn off the red LED. */
  307. ldr r0, =EP93XX_LED_DATA
  308. ldr r1, [r0]
  309. bic r1, r1, #EP93XX_LED_RED_ON
  310. str r1, [r0]
  311. /* There is no SDRAM so flash the green LED. */
  312. flash_green:
  313. orr r1, r1, #EP93XX_LED_GREEN_ON
  314. str r1, [r0]
  315. ldr r2, =0x00010000
  316. flash_green_delay_1:
  317. subs r2, r2, #1
  318. bne flash_green_delay_1
  319. bic r1, r1, #EP93XX_LED_GREEN_ON
  320. str r1, [r0]
  321. ldr r2, =0x00010000
  322. flash_green_delay_2:
  323. subs r2, r2, #1
  324. bne flash_green_delay_2
  325. orr r1, r1, #EP93XX_LED_GREEN_ON
  326. str r1, [r0]
  327. ldr r2, =0x00010000
  328. flash_green_delay_3:
  329. subs r2, r2, #1
  330. bne flash_green_delay_3
  331. bic r1, r1, #EP93XX_LED_GREEN_ON
  332. str r1, [r0]
  333. ldr r2, =0x00050000
  334. flash_green_delay_4:
  335. subs r2, r2, #1
  336. bne flash_green_delay_4
  337. b flash_green
  338. ep93xx_sdram_done:
  339. ldr r1, =EP93XX_LED_DATA
  340. ldr r0, [r1]
  341. bic r0, r0, #EP93XX_LED_RED_ON
  342. str r0, [r1]
  343. /* Determine the size of the SDRAM. */
  344. mov r0, r11
  345. bl ep93xx_sdram_size
  346. /* Save the SDRAM characteristics. */
  347. mov r8, r0
  348. mov r9, r1
  349. mov r10, r2
  350. /* Compute total memory size into r1 */
  351. mul r1, r8, r10
  352. #ifdef CONFIG_EDB93XX_SDCS0
  353. ldr r2, [r0, #SDRAM_OFF_DEVCFG0]
  354. #endif
  355. #ifdef CONFIG_EDB93XX_SDCS1
  356. ldr r2, [r0, #SDRAM_OFF_DEVCFG1]
  357. #endif
  358. #ifdef CONFIG_EDB93XX_SDCS2
  359. ldr r2, [r0, #SDRAM_OFF_DEVCFG2]
  360. #endif
  361. #ifdef CONFIG_EDB93XX_SDCS3
  362. ldr r2, [r0, #SDRAM_OFF_DEVCFG3]
  363. #endif
  364. /* Consider small DRAM size as:
  365. * < 32Mb for 32bit bus
  366. * < 64Mb for 16bit bus
  367. */
  368. tst r2, #EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH
  369. moveq r1, r1, lsr #1
  370. cmp r1, #0x02000000
  371. #if defined(CONFIG_EDB9301)
  372. /* Set refresh counter to 20ms for small DRAM size, otherwise 9.6ms */
  373. movlt r1, #0x03f0
  374. movge r1, #0x01e0
  375. #else
  376. /* Set refresh counter to 30.7ms for small DRAM size, otherwise 15ms */
  377. movlt r1, #0x0600
  378. movge r1, #0x2f0
  379. #endif
  380. str r1, [r0, #SDRAM_OFF_REFRSHTIMR]
  381. /* Save the memory configuration information. */
  382. orr r0, r11, #UBOOT_MEMORYCNF_BANK_SIZE
  383. stmia r0, {r8-r11}
  384. mov lr, r6
  385. mov pc, lr