Fork of the vendor (Boundary Devices) u-boot for Reform 2, with minor tweaks. The goal is to migrate to mainstream u-boot or barebox ASAP. The main impediment so far is the 4GB RAM config.
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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * armboot - Startup Code for ARM1176 CPU-core
  4. *
  5. * Copyright (c) 2007 Samsung Electronics
  6. *
  7. * Copyright (C) 2008
  8. * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
  9. *
  10. * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
  11. * 2007-09-21 - Added MoviNAND and OneNAND boot codes by
  12. * jsgood (jsgood.yang@samsung.com)
  13. * Base codes by scsuh (sc.suh)
  14. */
  15. #include <asm-offsets.h>
  16. #include <config.h>
  17. #include <linux/linkage.h>
  18. #ifndef CONFIG_SYS_PHY_UBOOT_BASE
  19. #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
  20. #endif
  21. /*
  22. *************************************************************************
  23. *
  24. * Startup Code (reset vector)
  25. *
  26. * do important init only if we don't start from memory!
  27. * setup Memory and board specific bits prior to relocation.
  28. * relocate armboot to ram
  29. * setup stack
  30. *
  31. *************************************************************************
  32. */
  33. .globl reset
  34. reset:
  35. /* Allow the board to save important registers */
  36. b save_boot_params
  37. .globl save_boot_params_ret
  38. save_boot_params_ret:
  39. /*
  40. * set the cpu to SVC32 mode
  41. */
  42. mrs r0, cpsr
  43. bic r0, r0, #0x3f
  44. orr r0, r0, #0xd3
  45. msr cpsr, r0
  46. /*
  47. *************************************************************************
  48. *
  49. * CPU_init_critical registers
  50. *
  51. * setup important registers
  52. * setup memory timing
  53. *
  54. *************************************************************************
  55. */
  56. /*
  57. * we do sys-critical inits only at reboot,
  58. * not when booting from ram!
  59. */
  60. cpu_init_crit:
  61. /*
  62. * When booting from NAND - it has definitely been a reset, so, no need
  63. * to flush caches and disable the MMU
  64. */
  65. #ifndef CONFIG_SPL_BUILD
  66. /*
  67. * flush v4 I/D caches
  68. */
  69. mov r0, #0
  70. mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
  71. mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
  72. /*
  73. * disable MMU stuff and caches
  74. */
  75. mrc p15, 0, r0, c1, c0, 0
  76. bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
  77. bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
  78. orr r0, r0, #0x00000002 @ set bit 1 (A) Align
  79. orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
  80. /* Prepare to disable the MMU */
  81. adr r2, mmu_disable_phys
  82. sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
  83. b mmu_disable
  84. .align 5
  85. /* Run in a single cache-line */
  86. mmu_disable:
  87. mcr p15, 0, r0, c1, c0, 0
  88. nop
  89. nop
  90. mov pc, r2
  91. mmu_disable_phys:
  92. #endif
  93. /*
  94. * Go setup Memory and board specific bits prior to relocation.
  95. */
  96. bl lowlevel_init /* go setup pll,mux,memory */
  97. bl _main
  98. /*------------------------------------------------------------------------------*/
  99. .globl c_runtime_cpu_setup
  100. c_runtime_cpu_setup:
  101. mov pc, lr
  102. WEAK(save_boot_params)
  103. b save_boot_params_ret /* back to my caller */
  104. ENDPROC(save_boot_params)