Fork of the vendor (Boundary Devices) u-boot for Reform 2, with minor tweaks. The goal is to migrate to mainstream u-boot or barebox ASAP. The main impediment so far is the 4GB RAM config.
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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * armboot - Startup Code for OMP2420/ARM1136 CPU-core
  4. *
  5. * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
  6. *
  7. * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
  8. * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  9. * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
  10. * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
  11. * Copyright (c) 2003 Kshitij <kshitij@ti.com>
  12. */
  13. #include <asm-offsets.h>
  14. #include <config.h>
  15. /*
  16. *************************************************************************
  17. *
  18. * Startup Code (reset vector)
  19. *
  20. * do important init only if we don't start from memory!
  21. * setup Memory and board specific bits prior to relocation.
  22. * relocate armboot to ram
  23. * setup stack
  24. *
  25. *************************************************************************
  26. */
  27. .globl reset
  28. reset:
  29. /*
  30. * set the cpu to SVC32 mode
  31. */
  32. mrs r0,cpsr
  33. bic r0,r0,#0x1f
  34. orr r0,r0,#0xd3
  35. msr cpsr,r0
  36. /* the mask ROM code should have PLL and others stable */
  37. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  38. bl cpu_init_crit
  39. #endif
  40. bl _main
  41. /*------------------------------------------------------------------------------*/
  42. .globl c_runtime_cpu_setup
  43. c_runtime_cpu_setup:
  44. bx lr
  45. /*
  46. *************************************************************************
  47. *
  48. * CPU_init_critical registers
  49. *
  50. * setup important registers
  51. * setup memory timing
  52. *
  53. *************************************************************************
  54. */
  55. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  56. cpu_init_crit:
  57. /*
  58. * flush v4 I/D caches
  59. */
  60. mov r0, #0
  61. mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
  62. mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
  63. /*
  64. * disable MMU stuff and caches
  65. */
  66. mrc p15, 0, r0, c1, c0, 0
  67. bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
  68. bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
  69. orr r0, r0, #0x00000002 @ set bit 1 (A) Align
  70. orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
  71. mcr p15, 0, r0, c1, c0, 0
  72. #ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
  73. /*
  74. * Jump to board specific initialization... The Mask ROM will have already initialized
  75. * basic memory. Go here to bump up clock rate and handle wake up conditions.
  76. */
  77. mov ip, lr /* persevere link reg across call */
  78. bl lowlevel_init /* go setup pll,mux,memory */
  79. mov lr, ip /* restore link */
  80. #endif
  81. mov pc, lr /* back to my caller */
  82. #endif /* CONFIG_SKIP_LOWLEVEL_INIT */