Fork of the vendor (Boundary Devices) u-boot for Reform 2, with minor tweaks. The goal is to migrate to mainstream u-boot or barebox ASAP. The main impediment so far is the 4GB RAM config.
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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Sascha Hauer, Pengutronix
  5. *
  6. * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/crm_regs.h>
  12. /* General purpose timers bitfields */
  13. #define GPTCR_SWR (1<<15) /* Software reset */
  14. #define GPTCR_FRR (1<<9) /* Freerun / restart */
  15. #define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
  16. #define GPTCR_TEN (1) /* Timer enable */
  17. /*
  18. * nothing really to do with interrupts, just starts up a counter.
  19. * The 32KHz 32-bit timer overruns in 134217 seconds
  20. */
  21. int timer_init(void)
  22. {
  23. int i;
  24. struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
  25. struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR;
  26. /* setup GP Timer 1 */
  27. writel(GPTCR_SWR, &gpt->ctrl);
  28. writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1);
  29. for (i = 0; i < 100; i++)
  30. writel(0, &gpt->ctrl); /* We have no udelay by now */
  31. writel(0, &gpt->pre); /* prescaler = 1 */
  32. /* Freerun Mode, 32KHz input */
  33. writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
  34. &gpt->ctrl);
  35. writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl);
  36. return 0;
  37. }