Fork of the vendor (Boundary Devices) u-boot for Reform 2, with minor tweaks. The goal is to migrate to mainstream u-boot or barebox ASAP. The main impediment so far is the 4GB RAM config.
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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
  4. */
  5. #include <asm/io.h>
  6. #include <linux/errno.h>
  7. #include <asm/arch/imx-regs.h>
  8. #include <linux/types.h>
  9. #include <asm/arch/sys_proto.h>
  10. #define ESDCTL_DDR2_EMR2 0x04000000
  11. #define ESDCTL_DDR2_EMR3 0x06000000
  12. #define ESDCTL_PRECHARGE 0x00000400
  13. #define ESDCTL_DDR2_EN_DLL 0x02000400
  14. #define ESDCTL_DDR2_RESET_DLL 0x00000333
  15. #define ESDCTL_DDR2_MR 0x00000233
  16. #define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
  17. enum {
  18. SMODE_NORMAL = 0,
  19. SMODE_PRECHARGE,
  20. SMODE_AUTO_REFRESH,
  21. SMODE_LOAD_REG,
  22. SMODE_MANUAL_REFRESH
  23. };
  24. #define set_mode(x, en, m) (x | (en << 31) | (m << 28))
  25. static inline void dram_wait(unsigned int count)
  26. {
  27. volatile unsigned int wait = count;
  28. while (wait--)
  29. ;
  30. }
  31. void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
  32. u32 row, u32 col, u32 dsize, u32 refresh)
  33. {
  34. struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
  35. u32 *cfg_reg, *ctl_reg;
  36. u32 val;
  37. u32 ctlval;
  38. switch (start_address) {
  39. case CSD0_BASE_ADDR:
  40. cfg_reg = &esdc->esdcfg0;
  41. ctl_reg = &esdc->esdctl0;
  42. break;
  43. case CSD1_BASE_ADDR:
  44. cfg_reg = &esdc->esdcfg1;
  45. ctl_reg = &esdc->esdctl1;
  46. break;
  47. default:
  48. return;
  49. }
  50. /* The MX35 supports 11 up to 14 rows */
  51. if (row < 11 || row > 14 || col < 8 || col > 10)
  52. return;
  53. ctlval = (row - 11) << 24 | (col - 8) << 20 | (dsize << 16);
  54. /* Initialize MISC register for DDR2 */
  55. val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
  56. ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
  57. writel(val, &esdc->esdmisc);
  58. val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
  59. writel(val, &esdc->esdmisc);
  60. /*
  61. * according to DDR2 specs, wait a while before
  62. * the PRECHARGE_ALL command
  63. */
  64. dram_wait(0x20000);
  65. /* Load DDR2 config and timing */
  66. writel(ddr2_config, cfg_reg);
  67. /* Precharge ALL */
  68. writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
  69. ctl_reg);
  70. writel(0xda, start_address + ESDCTL_PRECHARGE);
  71. /* Load mode */
  72. writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
  73. ctl_reg);
  74. writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
  75. writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
  76. writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
  77. writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
  78. /* Precharge ALL */
  79. writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
  80. ctl_reg);
  81. writel(0xda, start_address + ESDCTL_PRECHARGE);
  82. /* Set mode auto refresh : at least two refresh are required */
  83. writel(set_mode(ctlval, 1, SMODE_AUTO_REFRESH),
  84. ctl_reg);
  85. writel(0xda, start_address);
  86. writel(0xda, start_address);
  87. writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
  88. ctl_reg);
  89. writeb(0xda, start_address + ESDCTL_DDR2_MR);
  90. writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
  91. /* OCD mode exit */
  92. writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
  93. /* Set normal mode */
  94. writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh,
  95. ctl_reg);
  96. dram_wait(0x20000);
  97. /* Do not set delay lines, only for MDDR */
  98. }