Fork of the vendor (Boundary Devices) u-boot for Reform 2, with minor tweaks. The goal is to migrate to mainstream u-boot or barebox ASAP. The main impediment so far is the 4GB RAM config.
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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Sascha Hauer, Pengutronix
  5. *
  6. * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <div64.h>
  10. #include <asm/io.h>
  11. #include <linux/errno.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/crm_regs.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/sys_proto.h>
  16. #ifdef CONFIG_FSL_ESDHC
  17. #include <fsl_esdhc.h>
  18. #endif
  19. #include <netdev.h>
  20. #include <spl.h>
  21. #define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
  22. #define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF)
  23. #define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF)
  24. #define CLK_CODE_PATH(c) ((c) & 0xFF)
  25. #define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
  26. #ifdef CONFIG_FSL_ESDHC
  27. DECLARE_GLOBAL_DATA_PTR;
  28. #endif
  29. static int g_clk_mux_auto[8] = {
  30. CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1,
  31. CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1,
  32. };
  33. static int g_clk_mux_consumer[16] = {
  34. CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1,
  35. -1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0),
  36. CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1,
  37. -1, -1, CLK_CODE(4, 2, 0), -1,
  38. };
  39. static int hsp_div_table[3][16] = {
  40. {4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1},
  41. {-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1},
  42. {3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1},
  43. };
  44. u32 get_cpu_rev(void)
  45. {
  46. int reg;
  47. struct iim_regs *iim =
  48. (struct iim_regs *)IIM_BASE_ADDR;
  49. reg = readl(&iim->iim_srev);
  50. if (!reg) {
  51. reg = readw(ROMPATCH_REV);
  52. reg <<= 4;
  53. } else {
  54. reg += CHIP_REV_1_0;
  55. }
  56. return 0x35000 + (reg & 0xFF);
  57. }
  58. static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd)
  59. {
  60. int *pclk_mux;
  61. if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
  62. pclk_mux = g_clk_mux_consumer +
  63. ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
  64. MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
  65. } else {
  66. pclk_mux = g_clk_mux_auto +
  67. ((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >>
  68. MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET);
  69. }
  70. if ((*pclk_mux) == -1)
  71. return -1;
  72. if (fi && fd) {
  73. if (!CLK_CODE_PATH(*pclk_mux)) {
  74. *fi = *fd = 1;
  75. return CLK_CODE_ARM(*pclk_mux);
  76. }
  77. if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
  78. *fi = 3;
  79. *fd = 4;
  80. } else {
  81. *fi = 2;
  82. *fd = 3;
  83. }
  84. }
  85. return CLK_CODE_ARM(*pclk_mux);
  86. }
  87. static int get_ahb_div(u32 pdr0)
  88. {
  89. int *pclk_mux;
  90. pclk_mux = g_clk_mux_consumer +
  91. ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
  92. MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
  93. if ((*pclk_mux) == -1)
  94. return -1;
  95. return CLK_CODE_AHB(*pclk_mux);
  96. }
  97. static u32 decode_pll(u32 reg, u32 infreq)
  98. {
  99. u32 mfi = (reg >> 10) & 0xf;
  100. s32 mfn = reg & 0x3ff;
  101. u32 mfd = (reg >> 16) & 0x3ff;
  102. u32 pd = (reg >> 26) & 0xf;
  103. mfi = mfi <= 5 ? 5 : mfi;
  104. mfn = mfn >= 512 ? mfn - 1024 : mfn;
  105. mfd += 1;
  106. pd += 1;
  107. return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
  108. mfd * pd);
  109. }
  110. static u32 get_mcu_main_clk(void)
  111. {
  112. u32 arm_div = 0, fi = 0, fd = 0;
  113. struct ccm_regs *ccm =
  114. (struct ccm_regs *)IMX_CCM_BASE;
  115. arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
  116. fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
  117. return fi / (arm_div * fd);
  118. }
  119. static u32 get_ipg_clk(void)
  120. {
  121. u32 freq = get_mcu_main_clk();
  122. struct ccm_regs *ccm =
  123. (struct ccm_regs *)IMX_CCM_BASE;
  124. u32 pdr0 = readl(&ccm->pdr0);
  125. return freq / (get_ahb_div(pdr0) * 2);
  126. }
  127. static u32 get_ipg_per_clk(void)
  128. {
  129. u32 freq = get_mcu_main_clk();
  130. struct ccm_regs *ccm =
  131. (struct ccm_regs *)IMX_CCM_BASE;
  132. u32 pdr0 = readl(&ccm->pdr0);
  133. u32 pdr4 = readl(&ccm->pdr4);
  134. u32 div;
  135. if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
  136. div = CCM_GET_DIVIDER(pdr4,
  137. MXC_CCM_PDR4_PER0_PODF_MASK,
  138. MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
  139. } else {
  140. div = CCM_GET_DIVIDER(pdr0,
  141. MXC_CCM_PDR0_PER_PODF_MASK,
  142. MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
  143. div *= get_ahb_div(pdr0);
  144. }
  145. return freq / div;
  146. }
  147. u32 imx_get_uartclk(void)
  148. {
  149. u32 freq;
  150. struct ccm_regs *ccm =
  151. (struct ccm_regs *)IMX_CCM_BASE;
  152. u32 pdr4 = readl(&ccm->pdr4);
  153. if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
  154. freq = get_mcu_main_clk();
  155. else
  156. freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
  157. freq /= CCM_GET_DIVIDER(pdr4,
  158. MXC_CCM_PDR4_UART_PODF_MASK,
  159. MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
  160. return freq;
  161. }
  162. unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
  163. {
  164. u32 nfc_pdf, hsp_podf;
  165. u32 pll, ret_val = 0, usb_podf;
  166. struct ccm_regs *ccm =
  167. (struct ccm_regs *)IMX_CCM_BASE;
  168. u32 reg = readl(&ccm->pdr0);
  169. u32 reg4 = readl(&ccm->pdr4);
  170. reg |= 0x1;
  171. switch (clk) {
  172. case CPU_CLK:
  173. ret_val = get_mcu_main_clk();
  174. break;
  175. case AHB_CLK:
  176. ret_val = get_mcu_main_clk();
  177. break;
  178. case HSP_CLK:
  179. if (reg & CLKMODE_CONSUMER) {
  180. hsp_podf = (reg >> 20) & 0x3;
  181. pll = get_mcu_main_clk();
  182. hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF];
  183. if (hsp_podf > 0) {
  184. ret_val = pll / hsp_podf;
  185. } else {
  186. puts("mismatch HSP with ARM clock setting\n");
  187. ret_val = 0;
  188. }
  189. } else {
  190. ret_val = get_mcu_main_clk();
  191. }
  192. break;
  193. case IPG_CLK:
  194. ret_val = get_ipg_clk();
  195. break;
  196. case IPG_PER_CLK:
  197. ret_val = get_ipg_per_clk();
  198. break;
  199. case NFC_CLK:
  200. nfc_pdf = (reg4 >> 28) & 0xF;
  201. pll = get_mcu_main_clk();
  202. /* AHB/nfc_pdf */
  203. ret_val = pll / (nfc_pdf + 1);
  204. break;
  205. case USB_CLK:
  206. usb_podf = (reg4 >> 22) & 0x3F;
  207. if (reg4 & 0x200)
  208. pll = get_mcu_main_clk();
  209. else
  210. pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
  211. ret_val = pll / (usb_podf + 1);
  212. break;
  213. default:
  214. printf("Unknown clock: %d\n", clk);
  215. break;
  216. }
  217. return ret_val;
  218. }
  219. unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
  220. {
  221. u32 ret_val = 0, pdf, pre_pdf, clk_sel;
  222. struct ccm_regs *ccm =
  223. (struct ccm_regs *)IMX_CCM_BASE;
  224. u32 mpdr2 = readl(&ccm->pdr2);
  225. u32 mpdr3 = readl(&ccm->pdr3);
  226. u32 mpdr4 = readl(&ccm->pdr4);
  227. switch (clk) {
  228. case UART1_BAUD:
  229. case UART2_BAUD:
  230. case UART3_BAUD:
  231. clk_sel = mpdr3 & (1 << 14);
  232. pdf = (mpdr4 >> 10) & 0x3F;
  233. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  234. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  235. break;
  236. case SSI1_BAUD:
  237. pre_pdf = (mpdr2 >> 24) & 0x7;
  238. pdf = mpdr2 & 0x3F;
  239. clk_sel = mpdr2 & (1 << 6);
  240. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  241. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
  242. ((pre_pdf + 1) * (pdf + 1));
  243. break;
  244. case SSI2_BAUD:
  245. pre_pdf = (mpdr2 >> 27) & 0x7;
  246. pdf = (mpdr2 >> 8) & 0x3F;
  247. clk_sel = mpdr2 & (1 << 6);
  248. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  249. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
  250. ((pre_pdf + 1) * (pdf + 1));
  251. break;
  252. case CSI_BAUD:
  253. clk_sel = mpdr2 & (1 << 7);
  254. pdf = (mpdr2 >> 16) & 0x3F;
  255. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  256. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  257. break;
  258. case MSHC_CLK:
  259. pre_pdf = readl(&ccm->pdr1);
  260. clk_sel = (pre_pdf & 0x80);
  261. pdf = (pre_pdf >> 22) & 0x3F;
  262. pre_pdf = (pre_pdf >> 28) & 0x7;
  263. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  264. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
  265. ((pre_pdf + 1) * (pdf + 1));
  266. break;
  267. case ESDHC1_CLK:
  268. clk_sel = mpdr3 & 0x40;
  269. pdf = mpdr3 & 0x3F;
  270. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  271. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  272. break;
  273. case ESDHC2_CLK:
  274. clk_sel = mpdr3 & 0x40;
  275. pdf = (mpdr3 >> 8) & 0x3F;
  276. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  277. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  278. break;
  279. case ESDHC3_CLK:
  280. clk_sel = mpdr3 & 0x40;
  281. pdf = (mpdr3 >> 16) & 0x3F;
  282. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  283. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  284. break;
  285. case SPDIF_CLK:
  286. clk_sel = mpdr3 & 0x400000;
  287. pre_pdf = (mpdr3 >> 29) & 0x7;
  288. pdf = (mpdr3 >> 23) & 0x3F;
  289. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  290. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
  291. ((pre_pdf + 1) * (pdf + 1));
  292. break;
  293. default:
  294. printf("%s(): This clock: %d not supported yet\n",
  295. __func__, clk);
  296. break;
  297. }
  298. return ret_val;
  299. }
  300. unsigned int mxc_get_clock(enum mxc_clock clk)
  301. {
  302. switch (clk) {
  303. case MXC_ARM_CLK:
  304. return get_mcu_main_clk();
  305. case MXC_AHB_CLK:
  306. break;
  307. case MXC_IPG_CLK:
  308. return get_ipg_clk();
  309. case MXC_IPG_PERCLK:
  310. case MXC_I2C_CLK:
  311. return get_ipg_per_clk();
  312. case MXC_UART_CLK:
  313. return imx_get_uartclk();
  314. case MXC_ESDHC1_CLK:
  315. return mxc_get_peri_clock(ESDHC1_CLK);
  316. case MXC_ESDHC2_CLK:
  317. return mxc_get_peri_clock(ESDHC2_CLK);
  318. case MXC_ESDHC3_CLK:
  319. return mxc_get_peri_clock(ESDHC3_CLK);
  320. case MXC_USB_CLK:
  321. return mxc_get_main_clock(USB_CLK);
  322. case MXC_FEC_CLK:
  323. return get_ipg_clk();
  324. case MXC_CSPI_CLK:
  325. return get_ipg_clk();
  326. }
  327. return -1;
  328. }
  329. #ifdef CONFIG_FEC_MXC
  330. /*
  331. * The MX35 has no fuse for MAC, return a NULL MAC
  332. */
  333. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  334. {
  335. memset(mac, 0, 6);
  336. }
  337. u32 imx_get_fecclk(void)
  338. {
  339. return mxc_get_clock(MXC_IPG_CLK);
  340. }
  341. #endif
  342. int do_mx35_showclocks(cmd_tbl_t *cmdtp,
  343. int flag, int argc, char * const argv[])
  344. {
  345. u32 cpufreq = get_mcu_main_clk();
  346. printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
  347. printf("ipg clock : %dHz\n", get_ipg_clk());
  348. printf("ipg per clock : %dHz\n", get_ipg_per_clk());
  349. printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
  350. return 0;
  351. }
  352. U_BOOT_CMD(
  353. clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
  354. "display clocks",
  355. ""
  356. );
  357. #if defined(CONFIG_DISPLAY_CPUINFO)
  358. static char *get_reset_cause(void)
  359. {
  360. /* read RCSR register from CCM module */
  361. struct ccm_regs *ccm =
  362. (struct ccm_regs *)IMX_CCM_BASE;
  363. u32 cause = readl(&ccm->rcsr) & 0x0F;
  364. switch (cause) {
  365. case 0x0000:
  366. return "POR";
  367. case 0x0002:
  368. return "JTAG";
  369. case 0x0004:
  370. return "RST";
  371. case 0x0008:
  372. return "WDOG";
  373. default:
  374. return "unknown reset";
  375. }
  376. }
  377. int print_cpuinfo(void)
  378. {
  379. u32 srev = get_cpu_rev();
  380. printf("CPU: Freescale i.MX35 rev %d.%d at %d MHz.\n",
  381. (srev & 0xF0) >> 4, (srev & 0x0F),
  382. get_mcu_main_clk() / 1000000);
  383. printf("Reset cause: %s\n", get_reset_cause());
  384. return 0;
  385. }
  386. #endif
  387. /*
  388. * Initializes on-chip ethernet controllers.
  389. * to override, implement board_eth_init()
  390. */
  391. int cpu_eth_init(bd_t *bis)
  392. {
  393. int rc = -ENODEV;
  394. #if defined(CONFIG_FEC_MXC)
  395. rc = fecmxc_initialize(bis);
  396. #endif
  397. return rc;
  398. }
  399. #ifdef CONFIG_FSL_ESDHC
  400. /*
  401. * Initializes on-chip MMC controllers.
  402. * to override, implement board_mmc_init()
  403. */
  404. int cpu_mmc_init(bd_t *bis)
  405. {
  406. return fsl_esdhc_mmc_init(bis);
  407. }
  408. #endif
  409. int get_clocks(void)
  410. {
  411. #ifdef CONFIG_FSL_ESDHC
  412. #if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
  413. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  414. #elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
  415. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  416. #else
  417. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
  418. #endif
  419. #endif
  420. return 0;
  421. }
  422. #define RCSR_MEM_CTL_WEIM 0
  423. #define RCSR_MEM_CTL_NAND 1
  424. #define RCSR_MEM_CTL_ATA 2
  425. #define RCSR_MEM_CTL_EXPANSION 3
  426. #define RCSR_MEM_TYPE_NOR 0
  427. #define RCSR_MEM_TYPE_ONENAND 2
  428. #define RCSR_MEM_TYPE_SD 0
  429. #define RCSR_MEM_TYPE_I2C 2
  430. #define RCSR_MEM_TYPE_SPI 3
  431. u32 spl_boot_device(void)
  432. {
  433. struct ccm_regs *ccm =
  434. (struct ccm_regs *)IMX_CCM_BASE;
  435. u32 rcsr = readl(&ccm->rcsr);
  436. u32 mem_type, mem_ctl;
  437. /* In external mode, no boot device is returned */
  438. if ((rcsr >> 10) & 0x03)
  439. return BOOT_DEVICE_NONE;
  440. mem_ctl = (rcsr >> 25) & 0x03;
  441. mem_type = (rcsr >> 23) & 0x03;
  442. switch (mem_ctl) {
  443. case RCSR_MEM_CTL_WEIM:
  444. switch (mem_type) {
  445. case RCSR_MEM_TYPE_NOR:
  446. return BOOT_DEVICE_NOR;
  447. case RCSR_MEM_TYPE_ONENAND:
  448. return BOOT_DEVICE_ONENAND;
  449. default:
  450. return BOOT_DEVICE_NONE;
  451. }
  452. case RCSR_MEM_CTL_NAND:
  453. return BOOT_DEVICE_NAND;
  454. case RCSR_MEM_CTL_EXPANSION:
  455. switch (mem_type) {
  456. case RCSR_MEM_TYPE_SD:
  457. return BOOT_DEVICE_MMC1;
  458. case RCSR_MEM_TYPE_I2C:
  459. return BOOT_DEVICE_I2C;
  460. case RCSR_MEM_TYPE_SPI:
  461. return BOOT_DEVICE_SPI;
  462. default:
  463. return BOOT_DEVICE_NONE;
  464. }
  465. }
  466. return BOOT_DEVICE_NONE;
  467. }