Fork of the vendor (Boundary Devices) u-boot for Reform 2, with minor tweaks. The goal is to migrate to mainstream u-boot or barebox ASAP. The main impediment so far is the 4GB RAM config.
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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Sascha Hauer, Pengutronix
  5. */
  6. #include <common.h>
  7. #include <div64.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/sys_proto.h>
  12. static u32 mx31_decode_pll(u32 reg, u32 infreq)
  13. {
  14. u32 mfi = GET_PLL_MFI(reg);
  15. s32 mfn = GET_PLL_MFN(reg);
  16. u32 mfd = GET_PLL_MFD(reg);
  17. u32 pd = GET_PLL_PD(reg);
  18. mfi = mfi <= 5 ? 5 : mfi;
  19. mfn = mfn >= 512 ? mfn - 1024 : mfn;
  20. mfd += 1;
  21. pd += 1;
  22. return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
  23. mfd * pd);
  24. }
  25. static u32 mx31_get_mpl_dpdgck_clk(void)
  26. {
  27. u32 infreq;
  28. if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
  29. infreq = MXC_CLK32 * 1024;
  30. else
  31. infreq = MXC_HCLK;
  32. return mx31_decode_pll(readl(CCM_MPCTL), infreq);
  33. }
  34. static u32 mx31_get_mcu_main_clk(void)
  35. {
  36. /* For now we assume mpl_dpdgck_clk == mcu_main_clk
  37. * which should be correct for most boards
  38. */
  39. return mx31_get_mpl_dpdgck_clk();
  40. }
  41. static u32 mx31_get_ipg_clk(void)
  42. {
  43. u32 freq = mx31_get_mcu_main_clk();
  44. u32 pdr0 = readl(CCM_PDR0);
  45. freq /= GET_PDR0_MAX_PODF(pdr0) + 1;
  46. freq /= GET_PDR0_IPG_PODF(pdr0) + 1;
  47. return freq;
  48. }
  49. /* hsp is the clock for the ipu */
  50. static u32 mx31_get_hsp_clk(void)
  51. {
  52. u32 freq = mx31_get_mcu_main_clk();
  53. u32 pdr0 = readl(CCM_PDR0);
  54. freq /= GET_PDR0_HSP_PODF(pdr0) + 1;
  55. return freq;
  56. }
  57. void mx31_dump_clocks(void)
  58. {
  59. u32 cpufreq = mx31_get_mcu_main_clk();
  60. printf("mx31 cpu clock: %dMHz\n", cpufreq / 1000000);
  61. printf("ipg clock : %dHz\n", mx31_get_ipg_clk());
  62. printf("hsp clock : %dHz\n", mx31_get_hsp_clk());
  63. }
  64. unsigned int mxc_get_clock(enum mxc_clock clk)
  65. {
  66. switch (clk) {
  67. case MXC_ARM_CLK:
  68. return mx31_get_mcu_main_clk();
  69. case MXC_IPG_CLK:
  70. case MXC_IPG_PERCLK:
  71. case MXC_CSPI_CLK:
  72. case MXC_UART_CLK:
  73. case MXC_ESDHC_CLK:
  74. case MXC_I2C_CLK:
  75. return mx31_get_ipg_clk();
  76. case MXC_IPU_CLK:
  77. return mx31_get_hsp_clk();
  78. }
  79. return -1;
  80. }
  81. u32 imx_get_uartclk(void)
  82. {
  83. return mxc_get_clock(MXC_UART_CLK);
  84. }
  85. void mx31_gpio_mux(unsigned long mode)
  86. {
  87. unsigned long reg, shift, tmp;
  88. reg = IOMUXC_BASE + (mode & 0x1fc);
  89. shift = (~mode & 0x3) * 8;
  90. tmp = readl(reg);
  91. tmp &= ~(0xff << shift);
  92. tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
  93. writel(tmp, reg);
  94. }
  95. void mx31_set_pad(enum iomux_pins pin, u32 config)
  96. {
  97. u32 field, l, reg;
  98. pin &= IOMUX_PADNUM_MASK;
  99. reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4;
  100. field = (pin + 2) % 3;
  101. l = readl(reg);
  102. l &= ~(0x1ff << (field * 10));
  103. l |= config << (field * 10);
  104. writel(l, reg);
  105. }
  106. void mx31_set_gpr(enum iomux_gp_func gp, char en)
  107. {
  108. u32 l;
  109. struct iomuxc_regs *iomuxc = (struct iomuxc_regs *)IOMUXC_BASE;
  110. l = readl(&iomuxc->gpr);
  111. if (en)
  112. l |= gp;
  113. else
  114. l &= ~gp;
  115. writel(l, &iomuxc->gpr);
  116. }
  117. void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)
  118. {
  119. struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE;
  120. struct mx31_weim_cscr *cscr = &weim->cscr[cs];
  121. writel(weimcs->upper, &cscr->upper);
  122. writel(weimcs->lower, &cscr->lower);
  123. writel(weimcs->additional, &cscr->additional);
  124. }
  125. struct mx3_cpu_type mx31_cpu_type[] = {
  126. { .srev = 0x00, .v = 0x10 },
  127. { .srev = 0x10, .v = 0x11 },
  128. { .srev = 0x11, .v = 0x11 },
  129. { .srev = 0x12, .v = 0x1F },
  130. { .srev = 0x13, .v = 0x1F },
  131. { .srev = 0x14, .v = 0x12 },
  132. { .srev = 0x15, .v = 0x12 },
  133. { .srev = 0x28, .v = 0x20 },
  134. { .srev = 0x29, .v = 0x20 },
  135. };
  136. u32 get_cpu_rev(void)
  137. {
  138. u32 i, srev;
  139. /* read SREV register from IIM module */
  140. struct iim_regs *iim = (struct iim_regs *)MX31_IIM_BASE_ADDR;
  141. srev = readl(&iim->iim_srev);
  142. for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
  143. if (srev == mx31_cpu_type[i].srev)
  144. return mx31_cpu_type[i].v | (MXC_CPU_MX31 << 12);
  145. return srev | 0x8000;
  146. }
  147. static char *get_reset_cause(void)
  148. {
  149. /* read RCSR register from CCM module */
  150. struct clock_control_regs *ccm =
  151. (struct clock_control_regs *)CCM_BASE;
  152. u32 cause = readl(&ccm->rcsr) & 0x07;
  153. switch (cause) {
  154. case 0x0000:
  155. return "POR";
  156. case 0x0001:
  157. return "RST";
  158. case 0x0002:
  159. return "WDOG";
  160. case 0x0006:
  161. return "JTAG";
  162. case 0x0007:
  163. return "ARM11P power gating";
  164. default:
  165. return "unknown reset";
  166. }
  167. }
  168. #if defined(CONFIG_DISPLAY_CPUINFO)
  169. int print_cpuinfo(void)
  170. {
  171. u32 srev = get_cpu_rev();
  172. printf("CPU: Freescale i.MX31 rev %d.%d%s at %d MHz.\n",
  173. (srev & 0xF0) >> 4, (srev & 0x0F),
  174. ((srev & 0x8000) ? " unknown" : ""),
  175. mx31_get_mcu_main_clk() / 1000000);
  176. printf("Reset cause: %s\n", get_reset_cause());
  177. return 0;
  178. }
  179. #endif