Fork of the vendor (Boundary Devices) u-boot for Reform 2, with minor tweaks. The goal is to migrate to mainstream u-boot or barebox ASAP. The main impediment so far is the 4GB RAM config.
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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
  5. *
  6. * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  7. */
  8. #include <common.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/arch/clock.h>
  11. void mx31_uart1_hw_init(void)
  12. {
  13. /* setup pins for UART1 */
  14. mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
  15. mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
  16. mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
  17. mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
  18. }
  19. void mx31_uart2_hw_init(void)
  20. {
  21. /* setup pins for UART2 */
  22. mx31_gpio_mux(MUX_RXD2__UART2_RXD_MUX);
  23. mx31_gpio_mux(MUX_TXD2__UART2_TXD_MUX);
  24. mx31_gpio_mux(MUX_RTS2__UART2_RTS_B);
  25. mx31_gpio_mux(MUX_CTS2__UART2_CTS_B);
  26. }
  27. #ifdef CONFIG_MXC_SPI
  28. /*
  29. * Note: putting several spi setups here makes no sense as they may differ
  30. * at board level (physical pin SS0 of CSPI2 may aswell be used as SS0 of CSPI3)
  31. */
  32. void mx31_spi2_hw_init(void)
  33. {
  34. /* SPI2 */
  35. mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
  36. mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
  37. mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
  38. mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
  39. mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
  40. mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
  41. mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
  42. /* start SPI2 clock */
  43. __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
  44. }
  45. #endif