Fork of the vendor (Boundary Devices) u-boot for Reform 2, with minor tweaks. The goal is to migrate to mainstream u-boot or barebox ASAP. The main impediment so far is the 4GB RAM config.
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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2004 Texas Insturments
  4. *
  5. * (C) Copyright 2002
  6. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  7. * Marius Groeger <mgroeger@sysgo.de>
  8. *
  9. * (C) Copyright 2002
  10. * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  11. */
  12. /*
  13. * CPU specific code
  14. */
  15. #include <common.h>
  16. #include <command.h>
  17. #include <asm/system.h>
  18. static void cache_flush(void);
  19. int cleanup_before_linux (void)
  20. {
  21. /*
  22. * this function is called just before we call linux
  23. * it prepares the processor for linux
  24. *
  25. * we turn off caches etc ...
  26. */
  27. disable_interrupts ();
  28. /* turn off I/D-cache */
  29. icache_disable();
  30. dcache_disable();
  31. /* flush I/D-cache */
  32. cache_flush();
  33. return 0;
  34. }
  35. static void cache_flush(void)
  36. {
  37. unsigned long i = 0;
  38. /* clean entire data cache */
  39. asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
  40. /* invalidate both caches and flush btb */
  41. asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
  42. /* mem barrier to sync things */
  43. asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
  44. }
  45. #ifndef CONFIG_SYS_DCACHE_OFF
  46. void invalidate_dcache_all(void)
  47. {
  48. asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
  49. }
  50. void flush_dcache_all(void)
  51. {
  52. asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
  53. asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
  54. }
  55. void invalidate_dcache_range(unsigned long start, unsigned long stop)
  56. {
  57. if (!check_cache_range(start, stop))
  58. return;
  59. while (start < stop) {
  60. asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
  61. start += CONFIG_SYS_CACHELINE_SIZE;
  62. }
  63. }
  64. void flush_dcache_range(unsigned long start, unsigned long stop)
  65. {
  66. if (!check_cache_range(start, stop))
  67. return;
  68. while (start < stop) {
  69. asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
  70. start += CONFIG_SYS_CACHELINE_SIZE;
  71. }
  72. asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
  73. }
  74. #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
  75. void invalidate_dcache_all(void)
  76. {
  77. }
  78. void flush_dcache_all(void)
  79. {
  80. }
  81. #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
  82. #if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
  83. void enable_caches(void)
  84. {
  85. #ifndef CONFIG_SYS_ICACHE_OFF
  86. icache_enable();
  87. #endif
  88. #ifndef CONFIG_SYS_DCACHE_OFF
  89. dcache_enable();
  90. #endif
  91. }
  92. #endif