Fork of the vendor (Boundary Devices) u-boot for Reform 2, with minor tweaks. The goal is to migrate to mainstream u-boot or barebox ASAP. The main impediment so far is the 4GB RAM config.
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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
  4. */
  5. #ifndef __ASM_ARC_IO_H
  6. #define __ASM_ARC_IO_H
  7. #include <linux/types.h>
  8. #include <asm/byteorder.h>
  9. #ifdef __ARCHS__
  10. /*
  11. * ARCv2 based HS38 cores are in-order issue, but still weakly ordered
  12. * due to micro-arch buffering/queuing of load/store, cache hit vs. miss ...
  13. *
  14. * Explicit barrier provided by DMB instruction
  15. * - Operand supports fine grained load/store/load+store semantics
  16. * - Ensures that selected memory operation issued before it will complete
  17. * before any subsequent memory operation of same type
  18. * - DMB guarantees SMP as well as local barrier semantics
  19. * (asm-generic/barrier.h ensures sane smp_*mb if not defined here, i.e.
  20. * UP: barrier(), SMP: smp_*mb == *mb)
  21. * - DSYNC provides DMB+completion_of_cache_bpu_maintenance_ops hence not needed
  22. * in the general case. Plus it only provides full barrier.
  23. */
  24. #define mb() asm volatile("dmb 3\n" : : : "memory")
  25. #define rmb() asm volatile("dmb 1\n" : : : "memory")
  26. #define wmb() asm volatile("dmb 2\n" : : : "memory")
  27. #else
  28. /*
  29. * ARCompact based cores (ARC700) only have SYNC instruction which is super
  30. * heavy weight as it flushes the pipeline as well.
  31. * There are no real SMP implementations of such cores.
  32. */
  33. #define mb() asm volatile("sync\n" : : : "memory")
  34. #endif
  35. #ifdef __ARCHS__
  36. #define __iormb() rmb()
  37. #define __iowmb() wmb()
  38. #else
  39. #define __iormb() asm volatile("" : : : "memory")
  40. #define __iowmb() asm volatile("" : : : "memory")
  41. #endif
  42. static inline void sync(void)
  43. {
  44. /* Not yet implemented */
  45. }
  46. static inline u8 __raw_readb(const volatile void __iomem *addr)
  47. {
  48. u8 b;
  49. __asm__ __volatile__("ldb%U1 %0, %1\n"
  50. : "=r" (b)
  51. : "m" (*(volatile u8 __force *)addr)
  52. : "memory");
  53. return b;
  54. }
  55. static inline u16 __raw_readw(const volatile void __iomem *addr)
  56. {
  57. u16 s;
  58. __asm__ __volatile__("ldw%U1 %0, %1\n"
  59. : "=r" (s)
  60. : "m" (*(volatile u16 __force *)addr)
  61. : "memory");
  62. return s;
  63. }
  64. static inline u32 __raw_readl(const volatile void __iomem *addr)
  65. {
  66. u32 w;
  67. __asm__ __volatile__("ld%U1 %0, %1\n"
  68. : "=r" (w)
  69. : "m" (*(volatile u32 __force *)addr)
  70. : "memory");
  71. return w;
  72. }
  73. static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
  74. {
  75. __asm__ __volatile__("stb%U1 %0, %1\n"
  76. :
  77. : "r" (b), "m" (*(volatile u8 __force *)addr)
  78. : "memory");
  79. }
  80. static inline void __raw_writew(u16 s, volatile void __iomem *addr)
  81. {
  82. __asm__ __volatile__("stw%U1 %0, %1\n"
  83. :
  84. : "r" (s), "m" (*(volatile u16 __force *)addr)
  85. : "memory");
  86. }
  87. static inline void __raw_writel(u32 w, volatile void __iomem *addr)
  88. {
  89. __asm__ __volatile__("st%U1 %0, %1\n"
  90. :
  91. : "r" (w), "m" (*(volatile u32 __force *)addr)
  92. : "memory");
  93. }
  94. static inline int __raw_readsb(unsigned int addr, void *data, int bytelen)
  95. {
  96. __asm__ __volatile__ ("1:ld.di r8, [r0]\n"
  97. "sub.f r2, r2, 1\n"
  98. "bnz.d 1b\n"
  99. "stb.ab r8, [r1, 1]\n"
  100. :
  101. : "r" (addr), "r" (data), "r" (bytelen)
  102. : "r8");
  103. return bytelen;
  104. }
  105. static inline int __raw_readsw(unsigned int addr, void *data, int wordlen)
  106. {
  107. __asm__ __volatile__ ("1:ld.di r8, [r0]\n"
  108. "sub.f r2, r2, 1\n"
  109. "bnz.d 1b\n"
  110. "stw.ab r8, [r1, 2]\n"
  111. :
  112. : "r" (addr), "r" (data), "r" (wordlen)
  113. : "r8");
  114. return wordlen;
  115. }
  116. static inline int __raw_readsl(unsigned int addr, void *data, int longlen)
  117. {
  118. __asm__ __volatile__ ("1:ld.di r8, [r0]\n"
  119. "sub.f r2, r2, 1\n"
  120. "bnz.d 1b\n"
  121. "st.ab r8, [r1, 4]\n"
  122. :
  123. : "r" (addr), "r" (data), "r" (longlen)
  124. : "r8");
  125. return longlen;
  126. }
  127. static inline int __raw_writesb(unsigned int addr, void *data, int bytelen)
  128. {
  129. __asm__ __volatile__ ("1:ldb.ab r8, [r1, 1]\n"
  130. "sub.f r2, r2, 1\n"
  131. "bnz.d 1b\n"
  132. "st.di r8, [r0, 0]\n"
  133. :
  134. : "r" (addr), "r" (data), "r" (bytelen)
  135. : "r8");
  136. return bytelen;
  137. }
  138. static inline int __raw_writesw(unsigned int addr, void *data, int wordlen)
  139. {
  140. __asm__ __volatile__ ("1:ldw.ab r8, [r1, 2]\n"
  141. "sub.f r2, r2, 1\n"
  142. "bnz.d 1b\n"
  143. "st.ab.di r8, [r0, 0]\n"
  144. :
  145. : "r" (addr), "r" (data), "r" (wordlen)
  146. : "r8");
  147. return wordlen;
  148. }
  149. static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
  150. {
  151. __asm__ __volatile__ ("1:ld.ab r8, [r1, 4]\n"
  152. "sub.f r2, r2, 1\n"
  153. "bnz.d 1b\n"
  154. "st.ab.di r8, [r0, 0]\n"
  155. :
  156. : "r" (addr), "r" (data), "r" (longlen)
  157. : "r8");
  158. return longlen;
  159. }
  160. /*
  161. * MMIO can also get buffered/optimized in micro-arch, so barriers needed
  162. * Based on ARM model for the typical use case
  163. *
  164. * <ST [DMA buffer]>
  165. * <writel MMIO "go" reg>
  166. * or:
  167. * <readl MMIO "status" reg>
  168. * <LD [DMA buffer]>
  169. *
  170. * http://lkml.kernel.org/r/20150622133656.GG1583@arm.com
  171. */
  172. #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
  173. #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
  174. #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
  175. #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
  176. #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
  177. #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
  178. /*
  179. * Relaxed API for drivers which can handle barrier ordering themselves
  180. *
  181. * Also these are defined to perform little endian accesses.
  182. * To provide the typical device register semantics of fixed endian,
  183. * swap the byte order for Big Endian
  184. *
  185. * http://lkml.kernel.org/r/201603100845.30602.arnd@arndb.de
  186. */
  187. #define readb_relaxed(c) __raw_readb(c)
  188. #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
  189. __raw_readw(c)); __r; })
  190. #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
  191. __raw_readl(c)); __r; })
  192. #define writeb_relaxed(v,c) __raw_writeb(v,c)
  193. #define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
  194. #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
  195. #define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a)
  196. #define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))
  197. #define out_le32(a, v) out_arch(l, le32, a, v)
  198. #define out_le16(a, v) out_arch(w, le16, a, v)
  199. #define in_le32(a) in_arch(l, le32, a)
  200. #define in_le16(a) in_arch(w, le16, a)
  201. #define out_be32(a, v) out_arch(l, be32, a, v)
  202. #define out_be16(a, v) out_arch(w, be16, a, v)
  203. #define in_be32(a) in_arch(l, be32, a)
  204. #define in_be16(a) in_arch(w, be16, a)
  205. #define out_8(a, v) __raw_writeb(v, a)
  206. #define in_8(a) __raw_readb(a)
  207. /*
  208. * Clear and set bits in one shot. These macros can be used to clear and
  209. * set multiple bits in a register using a single call. These macros can
  210. * also be used to set a multiple-bit bit pattern using a mask, by
  211. * specifying the mask in the 'clear' parameter and the new bit pattern
  212. * in the 'set' parameter.
  213. */
  214. #define clrbits(type, addr, clear) \
  215. out_##type((addr), in_##type(addr) & ~(clear))
  216. #define setbits(type, addr, set) \
  217. out_##type((addr), in_##type(addr) | (set))
  218. #define clrsetbits(type, addr, clear, set) \
  219. out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
  220. #define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
  221. #define setbits_be32(addr, set) setbits(be32, addr, set)
  222. #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
  223. #define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
  224. #define setbits_le32(addr, set) setbits(le32, addr, set)
  225. #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
  226. #define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
  227. #define setbits_be16(addr, set) setbits(be16, addr, set)
  228. #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
  229. #define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
  230. #define setbits_le16(addr, set) setbits(le16, addr, set)
  231. #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
  232. #define clrbits_8(addr, clear) clrbits(8, addr, clear)
  233. #define setbits_8(addr, set) setbits(8, addr, set)
  234. #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
  235. #include <asm-generic/io.h>
  236. #endif /* __ASM_ARC_IO_H */