Fork of the vendor (Boundary Devices) u-boot for Reform 2, with minor tweaks. The goal is to migrate to mainstream u-boot or barebox ASAP. The main impediment so far is the 4GB RAM config.
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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
  4. */
  5. #ifndef __ASM_ARC_CACHE_H
  6. #define __ASM_ARC_CACHE_H
  7. #include <config.h>
  8. /*
  9. * As of today we may handle any L1 cache line length right in software.
  10. * For that essentially cache line length is a variable not constant.
  11. * And to satisfy users of ARCH_DMA_MINALIGN we just use largest line length
  12. * that may exist in either L1 or L2 (AKA SLC) caches on ARC.
  13. */
  14. #define ARCH_DMA_MINALIGN 128
  15. #if defined(ARC_MMU_ABSENT)
  16. #define CONFIG_ARC_MMU_VER 0
  17. #elif defined(CONFIG_ARC_MMU_V2)
  18. #define CONFIG_ARC_MMU_VER 2
  19. #elif defined(CONFIG_ARC_MMU_V3)
  20. #define CONFIG_ARC_MMU_VER 3
  21. #elif defined(CONFIG_ARC_MMU_V4)
  22. #define CONFIG_ARC_MMU_VER 4
  23. #endif
  24. #ifndef __ASSEMBLY__
  25. void cache_init(void);
  26. void flush_n_invalidate_dcache_all(void);
  27. void sync_n_cleanup_cache_all(void);
  28. static const inline int is_ioc_enabled(void)
  29. {
  30. return IS_ENABLED(CONFIG_ARC_DBG_IOC_ENABLE);
  31. }
  32. #endif /* __ASSEMBLY__ */
  33. #endif /* __ASM_ARC_CACHE_H */