Fork of the vendor (Boundary Devices) u-boot for Reform 2, with minor tweaks. The goal is to migrate to mainstream u-boot or barebox ASAP. The main impediment so far is the 4GB RAM config.
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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
  4. */
  5. #ifndef _ASM_ARC_ARCREGS_H
  6. #define _ASM_ARC_ARCREGS_H
  7. #include <asm/cache.h>
  8. #include <config.h>
  9. /*
  10. * ARC architecture has additional address space - auxiliary registers.
  11. * These registers are mostly used for configuration purposes.
  12. * These registers are not memory mapped and special commands are used for
  13. * access: "lr"/"sr".
  14. */
  15. #define ARC_AUX_IDENTITY 0x04
  16. #define ARC_AUX_STATUS32 0x0a
  17. /* Instruction cache related auxiliary registers */
  18. #define ARC_AUX_IC_IVIC 0x10
  19. #define ARC_AUX_IC_CTRL 0x11
  20. #define ARC_AUX_IC_IVIL 0x19
  21. #if (CONFIG_ARC_MMU_VER == 3)
  22. #define ARC_AUX_IC_PTAG 0x1E
  23. #endif
  24. #define ARC_BCR_IC_BUILD 0x77
  25. #define AUX_AUX_CACHE_LIMIT 0x5D
  26. #define ARC_AUX_NON_VOLATILE_LIMIT 0x5E
  27. /* ICCM and DCCM auxiliary registers */
  28. #define ARC_AUX_DCCM_BASE 0x18 /* DCCM Base Addr ARCv2 */
  29. #define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */
  30. /* Timer related auxiliary registers */
  31. #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */
  32. #define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */
  33. #define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */
  34. #define ARC_AUX_TIMER1_CNT 0x100 /* Timer 1 count */
  35. #define ARC_AUX_TIMER1_CTRL 0x101 /* Timer 1 control */
  36. #define ARC_AUX_TIMER1_LIMIT 0x102 /* Timer 1 limit */
  37. #define ARC_AUX_INTR_VEC_BASE 0x25
  38. /* Data cache related auxiliary registers */
  39. #define ARC_AUX_DC_IVDC 0x47
  40. #define ARC_AUX_DC_CTRL 0x48
  41. #define ARC_AUX_DC_IVDL 0x4A
  42. #define ARC_AUX_DC_FLSH 0x4B
  43. #define ARC_AUX_DC_FLDL 0x4C
  44. #if (CONFIG_ARC_MMU_VER == 3)
  45. #define ARC_AUX_DC_PTAG 0x5C
  46. #endif
  47. #define ARC_BCR_DC_BUILD 0x72
  48. #define ARC_BCR_SLC 0xce
  49. #define ARC_AUX_SLC_CONFIG 0x901
  50. #define ARC_AUX_SLC_CTRL 0x903
  51. #define ARC_AUX_SLC_FLUSH 0x904
  52. #define ARC_AUX_SLC_INVALIDATE 0x905
  53. #define ARC_AUX_SLC_IVDL 0x910
  54. #define ARC_AUX_SLC_FLDL 0x912
  55. #define ARC_AUX_SLC_RGN_START 0x914
  56. #define ARC_AUX_SLC_RGN_START1 0x915
  57. #define ARC_AUX_SLC_RGN_END 0x916
  58. #define ARC_AUX_SLC_RGN_END1 0x917
  59. #define ARC_BCR_CLUSTER 0xcf
  60. /* MMU Management regs */
  61. #define ARC_AUX_MMU_BCR 0x06f
  62. /* IO coherency related auxiliary registers */
  63. #define ARC_AUX_IO_COH_ENABLE 0x500
  64. #define ARC_AUX_IO_COH_PARTIAL 0x501
  65. #define ARC_AUX_IO_COH_AP0_BASE 0x508
  66. #define ARC_AUX_IO_COH_AP0_SIZE 0x509
  67. #ifndef __ASSEMBLY__
  68. /* Accessors for auxiliary registers */
  69. #define read_aux_reg(reg) __builtin_arc_lr(reg)
  70. /* gcc builtin sr needs reg param to be long immediate */
  71. #define write_aux_reg(reg_immed, val) \
  72. __builtin_arc_sr((unsigned int)val, reg_immed)
  73. /* ARCNUM [15:8] - field to identify each core in a multi-core system */
  74. #define CPU_ID_GET() ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8)
  75. static const inline int is_isa_arcv2(void)
  76. {
  77. return IS_ENABLED(CONFIG_ISA_ARCV2);
  78. }
  79. static const inline int is_isa_arcompact(void)
  80. {
  81. return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
  82. }
  83. #endif /* __ASSEMBLY__ */
  84. #endif /* _ASM_ARC_ARCREGS_H */