Fork of the vendor (Boundary Devices) u-boot for Reform 2, with minor tweaks. The goal is to migrate to mainstream u-boot or barebox ASAP. The main impediment so far is the 4GB RAM config.
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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
  4. */
  5. /dts-v1/;
  6. #include "skeleton.dtsi"
  7. #include "dt-bindings/clock/snps,hsdk-cgu.h"
  8. / {
  9. #address-cells = <1>;
  10. #size-cells = <1>;
  11. aliases {
  12. console = &uart0;
  13. spi0 = &spi0;
  14. };
  15. cpu_card {
  16. core_clk: core_clk {
  17. #clock-cells = <0>;
  18. compatible = "fixed-clock";
  19. clock-frequency = <1000000000>;
  20. u-boot,dm-pre-reloc;
  21. };
  22. };
  23. clk-fmeas {
  24. clocks = <&cgu_clk CLK_ARC_PLL>, <&cgu_clk CLK_SYS_PLL>,
  25. <&cgu_clk CLK_TUN_PLL>, <&cgu_clk CLK_DDR_PLL>,
  26. <&cgu_clk CLK_ARC>, <&cgu_clk CLK_HDMI_PLL>,
  27. <&cgu_clk CLK_TUN_TUN>, <&cgu_clk CLK_HDMI>,
  28. <&cgu_clk CLK_SYS_APB>, <&cgu_clk CLK_SYS_AXI>,
  29. <&cgu_clk CLK_SYS_ETH>, <&cgu_clk CLK_SYS_USB>,
  30. <&cgu_clk CLK_SYS_SDIO>, <&cgu_clk CLK_SYS_HDMI>,
  31. <&cgu_clk CLK_SYS_GFX_CORE>, <&cgu_clk CLK_SYS_GFX_DMA>,
  32. <&cgu_clk CLK_SYS_GFX_CFG>, <&cgu_clk CLK_SYS_DMAC_CORE>,
  33. <&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk CLK_SYS_SDIO_REF>,
  34. <&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>,
  35. <&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk CLK_SYS_EBI_REF>,
  36. <&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>;
  37. clock-names = "cpu-pll", "sys-pll",
  38. "tun-pll", "ddr-clk",
  39. "cpu-clk", "hdmi-pll",
  40. "tun-clk", "hdmi-clk",
  41. "apb-clk", "axi-clk",
  42. "eth-clk", "usb-clk",
  43. "sdio-clk", "hdmi-sys-clk",
  44. "gfx-core-clk", "gfx-dma-clk",
  45. "gfx-cfg-clk", "dmac-core-clk",
  46. "dmac-cfg-clk", "sdio-ref-clk",
  47. "spi-clk", "i2c-clk",
  48. "uart-clk", "ebi-clk",
  49. "rom-clk", "pwm-clk";
  50. };
  51. cgu_clk: cgu-clk@f0000000 {
  52. compatible = "snps,hsdk-cgu-clock";
  53. reg = <0xf0000000 0x10>, <0xf00014B8 0x4>;
  54. #clock-cells = <1>;
  55. };
  56. uart0: serial0@f0005000 {
  57. compatible = "snps,dw-apb-uart";
  58. reg = <0xf0005000 0x1000>;
  59. reg-shift = <2>;
  60. reg-io-width = <4>;
  61. };
  62. ethernet@f0008000 {
  63. #interrupt-cells = <1>;
  64. compatible = "altr,socfpga-stmmac";
  65. reg = <0xf0008000 0x2000>;
  66. phy-mode = "gmii";
  67. };
  68. ehci@0xf0040000 {
  69. compatible = "generic-ehci";
  70. reg = <0xf0040000 0x100>;
  71. };
  72. ohci@0xf0060000 {
  73. compatible = "generic-ohci";
  74. reg = <0xf0060000 0x100>;
  75. };
  76. spi0: spi@f0020000 {
  77. compatible = "snps,dw-apb-ssi";
  78. reg = <0xf0020000 0x1000>;
  79. #address-cells = <1>;
  80. #size-cells = <0>;
  81. spi-max-frequency = <4000000>;
  82. clocks = <&cgu_clk CLK_SYS_SPI_REF>;
  83. clock-names = "spi_clk";
  84. cs-gpio = <&cs_gpio 0>;
  85. spi_flash@0 {
  86. compatible = "spi-flash";
  87. reg = <0>;
  88. spi-max-frequency = <4000000>;
  89. };
  90. };
  91. cs_gpio: gpio@f00014b0 {
  92. compatible = "snps,hsdk-creg-gpio";
  93. reg = <0xf00014b0 0x4>;
  94. gpio-controller;
  95. #gpio-cells = <1>;
  96. gpio-bank-name = "hsdk-spi-cs";
  97. gpio-count = <1>;
  98. };
  99. };