Fork of the vendor (Boundary Devices) u-boot for Reform 2, with minor tweaks. The goal is to migrate to mainstream u-boot or barebox ASAP. The main impediment so far is the 4GB RAM config.
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  1. /*
  2. * Copyright 2017 NXP
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <spl.h>
  8. #include <asm/io.h>
  9. #include <errno.h>
  10. #include <asm/io.h>
  11. #include <asm/mach-imx/iomux-v3.h>
  12. #include <asm/arch/imx8mq_pins.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <power/pmic.h>
  15. #include <power/pfuze100_pmic.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/mach-imx/gpio.h>
  18. #include <asm/mach-imx/mxc_i2c.h>
  19. #include <fsl_esdhc_imx.h>
  20. #include <mmc.h>
  21. #include <asm/arch/ddr.h>
  22. #ifdef CONFIG_IMX8M_LPDDR4
  23. #include <asm/arch/imx8m_ddr.h>
  24. #endif
  25. DECLARE_GLOBAL_DATA_PTR;
  26. void spl_dram_init(void)
  27. {
  28. /* ddr init */
  29. ddr_init(&dram_timing);
  30. }
  31. #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
  32. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  33. struct i2c_pads_info i2c_pad_info1 = {
  34. .scl = {
  35. .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
  36. .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
  37. .gp = IMX_GPIO_NR(5, 14),
  38. },
  39. .sda = {
  40. .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
  41. .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
  42. .gp = IMX_GPIO_NR(5, 15),
  43. },
  44. };
  45. int board_mmc_getcd(struct mmc *mmc)
  46. {
  47. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  48. switch (cfg->esdhc_base) {
  49. case USDHC1_BASE_ADDR:
  50. return 1;
  51. case USDHC2_BASE_ADDR:
  52. return 1;
  53. }
  54. return 0;
  55. }
  56. #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
  57. PAD_CTL_FSEL2)
  58. #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
  59. #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
  60. #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
  61. #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
  62. static iomux_v3_cfg_t const init_pads[] = {
  63. #define GP_I2C1_PCA9546_RESET IMX_GPIO_NR(1, 4)
  64. IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(0x46),
  65. IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  66. IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  67. IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  68. IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  69. IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  70. IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  71. IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  72. IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  73. IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  74. IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75. #define GP_EMMC_RESET IMX_GPIO_NR(2, 10)
  76. IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  77. IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  78. IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  79. IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  80. IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  81. IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
  82. IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  83. IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
  84. IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
  85. };
  86. static struct fsl_esdhc_cfg usdhc_cfg[] = {
  87. {.esdhc_base = USDHC1_BASE_ADDR, .bus_width = 8,
  88. .gp_reset = GP_EMMC_RESET},
  89. {.esdhc_base = USDHC2_BASE_ADDR, .bus_width = 1,
  90. .gp_reset = USDHC2_PWR_GPIO},
  91. };
  92. int board_mmc_init(bd_t *bis)
  93. {
  94. int i, ret;
  95. /*
  96. * According to the board_mmc_init() the following map is done:
  97. * (U-Boot device node) (Physical Port)
  98. * mmc0 USDHC1
  99. * mmc1 USDHC2
  100. */
  101. for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  102. switch (i) {
  103. case 0:
  104. usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
  105. gpio_request(GP_EMMC_RESET, "usdhc1_reset");
  106. gpio_direction_output(GP_EMMC_RESET, 0);
  107. udelay(500);
  108. gpio_direction_output(GP_EMMC_RESET, 1);
  109. break;
  110. case 1:
  111. usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
  112. gpio_request(GP_EMMC_RESET, "usdhc2_reset");
  113. gpio_direction_output(USDHC2_PWR_GPIO, 0);
  114. udelay(500);
  115. gpio_direction_output(USDHC2_PWR_GPIO, 1);
  116. break;
  117. default:
  118. printf("Warning: you configured more USDHC controllers"
  119. "(%d) than supported by the board\n", i + 1);
  120. return -EINVAL;
  121. }
  122. printf("board_mmc_init: %d\n",i);
  123. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  124. if (ret)
  125. return ret;
  126. }
  127. return 0;
  128. }
  129. #define GP_ARM_DRAM_VSEL IMX_GPIO_NR(3, 24)
  130. #define GP_DRAM_1P1_VSEL IMX_GPIO_NR(2, 11)
  131. #define GP_SOC_GPU_VPU_VSEL IMX_GPIO_NR(2, 20)
  132. #define I2C_MUX_ADDR 0x70
  133. #define I2C_FAN53555_ADDR 0x60
  134. void ddr_voltage_init(void)
  135. {
  136. u8 val8;
  137. gpio_set_value(GP_I2C1_PCA9546_RESET, 1);
  138. gpio_set_value(GP_ARM_DRAM_VSEL, 0);
  139. gpio_set_value(GP_DRAM_1P1_VSEL, 0);
  140. gpio_set_value(GP_SOC_GPU_VPU_VSEL, 0);
  141. printf("Setting voltages\n");
  142. /*
  143. * 9e (1e = 30) default .9 V
  144. * 0.6V to 1.23V in 10 MV steps
  145. */
  146. /* Enable I2C1A, ARM/DRAM */
  147. i2c_write(I2C_MUX_ADDR, 1, 1, NULL, 0);
  148. /*
  149. * .6 + .40 = 1.00
  150. */
  151. val8 = 0x80 + 40;
  152. i2c_write(I2C_FAN53555_ADDR, 0, 1, &val8, 1);
  153. i2c_write(I2C_FAN53555_ADDR, 1, 1, &val8, 1);
  154. /* Enable I2C1B, DRAM 1.1V */
  155. i2c_write(I2C_MUX_ADDR, 2, 1, NULL, 0);
  156. /*
  157. * .6 + .50 = 1.10
  158. */
  159. val8 = 0x80 + 50;
  160. i2c_write(I2C_FAN53555_ADDR, 0, 1, &val8, 1);
  161. i2c_write(I2C_FAN53555_ADDR, 1, 1, &val8, 1);
  162. /* Enable I2C1C, soc/gpu/vpu */
  163. i2c_write(I2C_MUX_ADDR, 4, 1, NULL, 0);
  164. /*
  165. * .6 + .30 = .90
  166. */
  167. val8 = 0x80 + 30;
  168. i2c_write(I2C_FAN53555_ADDR, 0, 1, &val8, 1);
  169. i2c_write(I2C_FAN53555_ADDR, 1, 1, &val8, 1);
  170. /* Enable I2C1D */
  171. i2c_write(I2C_MUX_ADDR, 8, 1, NULL, 0);
  172. }
  173. int power_init_board(void)
  174. {
  175. /* nitrogen8m_som I2C write */
  176. ddr_voltage_init();
  177. return 0;
  178. }
  179. void spl_board_init(void)
  180. {
  181. #ifndef CONFIG_SPL_USB_SDP_SUPPORT
  182. /* Serial download mode */
  183. if (is_usb_boot()) {
  184. puts("Back to ROM, SDP\n");
  185. restore_boot_params();
  186. }
  187. #endif
  188. puts("Normal Boot\n");
  189. }
  190. #ifdef CONFIG_SPL_LOAD_FIT
  191. int board_fit_config_name_match(const char *name)
  192. {
  193. /* Just empty function now - can't decide what to choose */
  194. debug("%s: %s\n", __func__, name);
  195. return 0;
  196. }
  197. #endif
  198. static void hexdump(unsigned char *buf, int len)
  199. {
  200. int i;
  201. for (i = 0; i < len; i++) {
  202. if ((i % 16) == 0)
  203. printf("%s%08x: ", i ? "\n" : "",
  204. (unsigned int)&buf[i]);
  205. printf("%02x ", buf[i]);
  206. }
  207. printf("\n");
  208. }
  209. int mx8mq_showclocks();
  210. void board_init_f(ulong dummy)
  211. {
  212. int ret;
  213. /* Clear global data */
  214. memset((void *)gd, 0, sizeof(gd_t));
  215. arch_cpu_init();
  216. // without this, no uart output
  217. board_early_init_f();
  218. init_uart_clk(0);
  219. timer_init();
  220. preloader_console_init();
  221. /* Clear the BSS. */
  222. memset(__bss_start, 0, __bss_end - __bss_start);
  223. //ret = spl_init();
  224. if (ret) {
  225. printf("spl_init() failed: %d\n", ret);
  226. hang();
  227. }
  228. enable_tzc380();
  229. // without this, no uart output
  230. imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
  231. /* Adjust pmic voltage to 1.0V for 800M */
  232. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  233. power_init_board();
  234. /* DDR initialization */
  235. spl_dram_init();
  236. mx8mq_showclocks();
  237. // FIXME: quick DDR test
  238. for (int i=0; i<256; i++) {
  239. *((uint8_t*)0x42000000+i) = i;
  240. }
  241. hexdump(0x42000000, 512);
  242. board_init_r(NULL, 0);
  243. }