Fork of the vendor (Boundary Devices) u-boot for Reform 2, with minor tweaks. The goal is to migrate to mainstream u-boot or barebox ASAP. The main impediment so far is the 4GB RAM config.
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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017 NXP
  4. *
  5. * Peng Fan <peng.fan@nxp.com>
  6. */
  7. #include <common.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <errno.h>
  13. #include <linux/iopoll.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
  16. #ifdef CONFIG_SECURE_BOOT
  17. void hab_caam_clock_enable(unsigned char enable)
  18. {
  19. /* The CAAM clock is always on for iMX8M */
  20. }
  21. #endif
  22. static u32 decode_frac_pll(enum clk_root_src frac_pll)
  23. {
  24. u32 pll_cfg0, pll_cfg1, pllout;
  25. u32 pll_refclk_sel, pll_refclk;
  26. u32 divr_val, divq_val, divf_val, divff, divfi;
  27. u32 pllout_div_shift, pllout_div_mask, pllout_div;
  28. switch (frac_pll) {
  29. case ARM_PLL_CLK:
  30. pll_cfg0 = readl(&ana_pll->arm_pll_cfg0);
  31. pll_cfg1 = readl(&ana_pll->arm_pll_cfg1);
  32. pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
  33. pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK;
  34. break;
  35. default:
  36. printf("Frac PLL %d not supporte\n", frac_pll);
  37. return 0;
  38. }
  39. pllout_div = readl(&ana_pll->frac_pllout_div_cfg);
  40. pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
  41. /* Power down */
  42. if (pll_cfg0 & FRAC_PLL_PD_MASK)
  43. return 0;
  44. /* output not enabled */
  45. if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0)
  46. return 0;
  47. pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK;
  48. if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M)
  49. pll_refclk = 25000000u;
  50. else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M)
  51. pll_refclk = 27000000u;
  52. else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M)
  53. pll_refclk = 27000000u;
  54. else
  55. pll_refclk = 0;
  56. if (pll_cfg0 & FRAC_PLL_BYPASS_MASK)
  57. return pll_refclk;
  58. divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >>
  59. FRAC_PLL_REFCLK_DIV_VAL_SHIFT;
  60. divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK;
  61. divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >>
  62. FRAC_PLL_FRAC_DIV_CTL_SHIFT;
  63. divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK;
  64. divf_val = 1 + divfi + divff / (1 << 24);
  65. pllout = pll_refclk / (divr_val + 1) * 8 * divf_val /
  66. ((divq_val + 1) * 2);
  67. return pllout / (pllout_div + 1);
  68. }
  69. static u32 decode_sscg_pll(enum clk_root_src sscg_pll)
  70. {
  71. u32 pll_cfg0, pll_cfg1, pll_cfg2;
  72. u32 pll_refclk_sel, pll_refclk;
  73. u32 divr1, divr2, divf1, divf2, divq, div;
  74. u32 sse;
  75. u32 pll_clke;
  76. u32 pllout_div_shift, pllout_div_mask, pllout_div;
  77. u32 pllout;
  78. switch (sscg_pll) {
  79. case SYSTEM_PLL1_800M_CLK:
  80. case SYSTEM_PLL1_400M_CLK:
  81. case SYSTEM_PLL1_266M_CLK:
  82. case SYSTEM_PLL1_200M_CLK:
  83. case SYSTEM_PLL1_160M_CLK:
  84. case SYSTEM_PLL1_133M_CLK:
  85. case SYSTEM_PLL1_100M_CLK:
  86. case SYSTEM_PLL1_80M_CLK:
  87. case SYSTEM_PLL1_40M_CLK:
  88. pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0);
  89. pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1);
  90. pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2);
  91. pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT;
  92. pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK;
  93. break;
  94. case SYSTEM_PLL2_1000M_CLK:
  95. case SYSTEM_PLL2_500M_CLK:
  96. case SYSTEM_PLL2_333M_CLK:
  97. case SYSTEM_PLL2_250M_CLK:
  98. case SYSTEM_PLL2_200M_CLK:
  99. case SYSTEM_PLL2_166M_CLK:
  100. case SYSTEM_PLL2_125M_CLK:
  101. case SYSTEM_PLL2_100M_CLK:
  102. case SYSTEM_PLL2_50M_CLK:
  103. pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0);
  104. pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1);
  105. pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2);
  106. pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT;
  107. pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK;
  108. break;
  109. case SYSTEM_PLL3_CLK:
  110. pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0);
  111. pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1);
  112. pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2);
  113. pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT;
  114. pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK;
  115. break;
  116. case DRAM_PLL1_CLK:
  117. pll_cfg0 = readl(&ana_pll->dram_pll_cfg0);
  118. pll_cfg1 = readl(&ana_pll->dram_pll_cfg1);
  119. pll_cfg2 = readl(&ana_pll->dram_pll_cfg2);
  120. pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT;
  121. pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK;
  122. break;
  123. default:
  124. printf("sscg pll %d not supporte\n", sscg_pll);
  125. return 0;
  126. }
  127. switch (sscg_pll) {
  128. case DRAM_PLL1_CLK:
  129. pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
  130. div = 1;
  131. break;
  132. case SYSTEM_PLL3_CLK:
  133. pll_clke = SSCG_PLL_PLL3_CLKE_MASK;
  134. div = 1;
  135. break;
  136. case SYSTEM_PLL2_1000M_CLK:
  137. case SYSTEM_PLL1_800M_CLK:
  138. pll_clke = SSCG_PLL_CLKE_MASK;
  139. div = 1;
  140. break;
  141. case SYSTEM_PLL2_500M_CLK:
  142. case SYSTEM_PLL1_400M_CLK:
  143. pll_clke = SSCG_PLL_DIV2_CLKE_MASK;
  144. div = 2;
  145. break;
  146. case SYSTEM_PLL2_333M_CLK:
  147. case SYSTEM_PLL1_266M_CLK:
  148. pll_clke = SSCG_PLL_DIV3_CLKE_MASK;
  149. div = 3;
  150. break;
  151. case SYSTEM_PLL2_250M_CLK:
  152. case SYSTEM_PLL1_200M_CLK:
  153. pll_clke = SSCG_PLL_DIV4_CLKE_MASK;
  154. div = 4;
  155. break;
  156. case SYSTEM_PLL2_200M_CLK:
  157. case SYSTEM_PLL1_160M_CLK:
  158. pll_clke = SSCG_PLL_DIV5_CLKE_MASK;
  159. div = 5;
  160. break;
  161. case SYSTEM_PLL2_166M_CLK:
  162. case SYSTEM_PLL1_133M_CLK:
  163. pll_clke = SSCG_PLL_DIV6_CLKE_MASK;
  164. div = 6;
  165. break;
  166. case SYSTEM_PLL2_125M_CLK:
  167. case SYSTEM_PLL1_100M_CLK:
  168. pll_clke = SSCG_PLL_DIV8_CLKE_MASK;
  169. div = 8;
  170. break;
  171. case SYSTEM_PLL2_100M_CLK:
  172. case SYSTEM_PLL1_80M_CLK:
  173. pll_clke = SSCG_PLL_DIV10_CLKE_MASK;
  174. div = 10;
  175. break;
  176. case SYSTEM_PLL2_50M_CLK:
  177. case SYSTEM_PLL1_40M_CLK:
  178. pll_clke = SSCG_PLL_DIV20_CLKE_MASK;
  179. div = 20;
  180. break;
  181. default:
  182. printf("sscg pll %d not supporte\n", sscg_pll);
  183. return 0;
  184. }
  185. /* Power down */
  186. if (pll_cfg0 & SSCG_PLL_PD_MASK)
  187. return 0;
  188. /* output not enabled */
  189. if ((pll_cfg0 & pll_clke) == 0)
  190. return 0;
  191. pllout_div = readl(&ana_pll->sscg_pllout_div_cfg);
  192. pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
  193. pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK;
  194. if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M)
  195. pll_refclk = 25000000u;
  196. else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M)
  197. pll_refclk = 27000000u;
  198. else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M)
  199. pll_refclk = 27000000u;
  200. else
  201. pll_refclk = 0;
  202. /* If bypass1 and bypass2 not the same value? TODO */
  203. if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) ||
  204. (pll_cfg0 & SSCG_PLL_BYPASS2_MASK))
  205. return pll_refclk;
  206. divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >>
  207. SSCG_PLL_REF_DIVR1_SHIFT;
  208. divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >>
  209. SSCG_PLL_REF_DIVR2_SHIFT;
  210. divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >>
  211. SSCG_PLL_FEEDBACK_DIV_F1_SHIFT;
  212. divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >>
  213. SSCG_PLL_FEEDBACK_DIV_F2_SHIFT;
  214. divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >>
  215. SSCG_PLL_OUTPUT_DIV_VAL_SHIFT;
  216. sse = pll_cfg1 & SSCG_PLL_SSE_MASK;
  217. if (sse)
  218. sse = 8;
  219. else
  220. sse = 2;
  221. pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) /
  222. (divr2 + 1) * (divf2 + 1) / (divq + 1);
  223. return pllout / (pllout_div + 1) / div;
  224. }
  225. static u32 get_root_src_clk(enum clk_root_src root_src)
  226. {
  227. switch (root_src) {
  228. case OSC_25M_CLK:
  229. return 25000000;
  230. case OSC_27M_CLK:
  231. return 27000000;
  232. case OSC_32K_CLK:
  233. return 32768;
  234. case ARM_PLL_CLK:
  235. return decode_frac_pll(root_src);
  236. case SYSTEM_PLL1_800M_CLK:
  237. case SYSTEM_PLL1_400M_CLK:
  238. case SYSTEM_PLL1_266M_CLK:
  239. case SYSTEM_PLL1_200M_CLK:
  240. case SYSTEM_PLL1_160M_CLK:
  241. case SYSTEM_PLL1_133M_CLK:
  242. case SYSTEM_PLL1_100M_CLK:
  243. case SYSTEM_PLL1_80M_CLK:
  244. case SYSTEM_PLL1_40M_CLK:
  245. case SYSTEM_PLL2_1000M_CLK:
  246. case SYSTEM_PLL2_500M_CLK:
  247. case SYSTEM_PLL2_333M_CLK:
  248. case SYSTEM_PLL2_250M_CLK:
  249. case SYSTEM_PLL2_200M_CLK:
  250. case SYSTEM_PLL2_166M_CLK:
  251. case SYSTEM_PLL2_125M_CLK:
  252. case SYSTEM_PLL2_100M_CLK:
  253. case SYSTEM_PLL2_50M_CLK:
  254. case SYSTEM_PLL3_CLK:
  255. return decode_sscg_pll(root_src);
  256. default:
  257. return 0;
  258. }
  259. return 0;
  260. }
  261. static u32 get_root_clk(enum clk_root_index clock_id)
  262. {
  263. enum clk_root_src root_src;
  264. u32 post_podf, pre_podf, root_src_clk;
  265. if (clock_root_enabled(clock_id) <= 0)
  266. return 0;
  267. if (clock_get_prediv(clock_id, &pre_podf) < 0)
  268. return 0;
  269. if (clock_get_postdiv(clock_id, &post_podf) < 0)
  270. return 0;
  271. if (clock_get_src(clock_id, &root_src) < 0)
  272. return 0;
  273. root_src_clk = get_root_src_clk(root_src);
  274. return root_src_clk / (post_podf + 1) / (pre_podf + 1);
  275. }
  276. #ifdef CONFIG_MXC_OCOTP
  277. void enable_ocotp_clk(unsigned char enable)
  278. {
  279. clock_enable(CCGR_OCOTP, !!enable);
  280. }
  281. #endif
  282. int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
  283. {
  284. /* 0 - 3 is valid i2c num */
  285. if (i2c_num > 3)
  286. return -EINVAL;
  287. clock_enable(CCGR_I2C1 + i2c_num, !!enable);
  288. return 0;
  289. }
  290. unsigned int mxc_get_clock(enum clk_root_index clk)
  291. {
  292. u32 val;
  293. if (clk >= CLK_ROOT_MAX)
  294. return 0;
  295. if (clk == MXC_ARM_CLK)
  296. return get_root_clk(ARM_A53_CLK_ROOT);
  297. if (clk == MXC_IPG_CLK) {
  298. clock_get_target_val(IPG_CLK_ROOT, &val);
  299. val = val & 0x3;
  300. return get_root_clk(AHB_CLK_ROOT) / (val + 1);
  301. }
  302. return get_root_clk(clk);
  303. }
  304. u32 imx_get_uartclk(void)
  305. {
  306. return mxc_get_clock(UART1_CLK_ROOT);
  307. }
  308. struct dram_bypass_clk_setting {
  309. ulong clk;
  310. int alt_root_sel;
  311. enum root_pre_div alt_pre_div;
  312. int apb_root_sel;
  313. enum root_pre_div apb_pre_div;
  314. };
  315. #define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \
  316. { \
  317. .clk = (_rate), \
  318. .alt_root_sel = (_m), \
  319. .alt_pre_div = (_p), \
  320. .apb_root_sel = (_s), \
  321. .apb_pre_div = (_k), \
  322. }
  323. static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = {
  324. DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2, CLK_ROOT_PRE_DIV2),
  325. DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2, CLK_ROOT_PRE_DIV2),
  326. DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3, CLK_ROOT_PRE_DIV2),
  327. };
  328. void dram_enable_bypass(ulong clk_val)
  329. {
  330. int i = 0;
  331. struct dram_bypass_clk_setting *config;
  332. while (1) {
  333. config = &imx8mq_dram_bypass_tbl[i];
  334. if (clk_val == config->clk)
  335. break;
  336. i++;
  337. if (i >= ARRAY_SIZE(imx8mq_dram_bypass_tbl)) {
  338. printf("No matched freq table %lu\n", clk_val);
  339. return;
  340. }
  341. }
  342. clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(config->alt_root_sel) | CLK_ROOT_PRE_DIV(config->alt_pre_div));
  343. clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(config->apb_root_sel) | CLK_ROOT_PRE_DIV(config->apb_pre_div));
  344. clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));
  345. }
  346. void dram_disable_bypass(void)
  347. {
  348. clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
  349. clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
  350. }
  351. void mxs_set_lcdclk(u32 base_addr, u32 freq)
  352. {
  353. /*
  354. * LCDIF_PIXEL_CLK: select 800MHz root clock,
  355. * select pre divider 8, output is 100 MHz
  356. */
  357. clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON |
  358. CLK_ROOT_SOURCE_SEL(4) |
  359. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8));
  360. }
  361. void init_wdog_clk(void)
  362. {
  363. clock_enable(CCGR_WDOG1, 0);
  364. clock_enable(CCGR_WDOG2, 0);
  365. clock_enable(CCGR_WDOG3, 0);
  366. clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
  367. CLK_ROOT_SOURCE_SEL(0));
  368. clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
  369. CLK_ROOT_SOURCE_SEL(0));
  370. clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
  371. CLK_ROOT_SOURCE_SEL(0));
  372. clock_enable(CCGR_WDOG1, 1);
  373. clock_enable(CCGR_WDOG2, 1);
  374. clock_enable(CCGR_WDOG3, 1);
  375. }
  376. void init_usb_clk(int usbno)
  377. {
  378. if (!usbno) {
  379. if (!is_usb_boot()) {
  380. clock_enable(CCGR_USB_CTRL1, 0);
  381. clock_enable(CCGR_USB_PHY1, 0);
  382. clock_enable(CCGR_USB_CTRL2, 0);
  383. clock_enable(CCGR_USB_PHY2, 0);
  384. /* 500MHz */
  385. clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON |
  386. CLK_ROOT_SOURCE_SEL(1));
  387. /* 100MHz */
  388. clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON |
  389. CLK_ROOT_SOURCE_SEL(1));
  390. /* 100MHz */
  391. clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON |
  392. CLK_ROOT_SOURCE_SEL(1));
  393. }
  394. clock_enable(CCGR_USB_CTRL1, 1);
  395. clock_enable(CCGR_USB_PHY1, 1);
  396. } else {
  397. clock_enable(CCGR_USB_CTRL2, 1);
  398. clock_enable(CCGR_USB_PHY2, 1);
  399. }
  400. }
  401. void init_uart_clk(u32 index)
  402. {
  403. /* Set uart clock root 25M OSC */
  404. switch (index) {
  405. case 0:
  406. clock_enable(CCGR_UART1, 0);
  407. clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
  408. CLK_ROOT_SOURCE_SEL(0));
  409. clock_enable(CCGR_UART1, 1);
  410. return;
  411. case 1:
  412. clock_enable(CCGR_UART2, 0);
  413. clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
  414. CLK_ROOT_SOURCE_SEL(0));
  415. clock_enable(CCGR_UART2, 1);
  416. return;
  417. case 2:
  418. clock_enable(CCGR_UART3, 0);
  419. clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
  420. CLK_ROOT_SOURCE_SEL(0));
  421. clock_enable(CCGR_UART3, 1);
  422. return;
  423. case 3:
  424. clock_enable(CCGR_UART4, 0);
  425. clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
  426. CLK_ROOT_SOURCE_SEL(0));
  427. clock_enable(CCGR_UART4, 1);
  428. return;
  429. default:
  430. printf("Invalid uart index\n");
  431. return;
  432. }
  433. }
  434. void init_clk_usdhc(u32 index)
  435. {
  436. /*
  437. * set usdhc clock root
  438. * sys pll1 400M
  439. */
  440. switch (index) {
  441. case 0:
  442. clock_enable(CCGR_USDHC1, 0);
  443. clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
  444. CLK_ROOT_SOURCE_SEL(1) |
  445. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
  446. clock_enable(CCGR_USDHC1, 1);
  447. return;
  448. case 1:
  449. clock_enable(CCGR_USDHC2, 0);
  450. clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
  451. CLK_ROOT_SOURCE_SEL(1) |
  452. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
  453. clock_enable(CCGR_USDHC2, 1);
  454. return;
  455. default:
  456. printf("Invalid usdhc index\n");
  457. return;
  458. }
  459. }
  460. int set_clk_qspi(void)
  461. {
  462. /*
  463. * set qspi root
  464. * sys pll1 100M
  465. */
  466. clock_enable(CCGR_QSPI, 0);
  467. clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
  468. CLK_ROOT_SOURCE_SEL(7));
  469. clock_enable(CCGR_QSPI, 1);
  470. return 0;
  471. }
  472. #ifdef CONFIG_FEC_MXC
  473. int set_clk_enet(enum enet_freq type)
  474. {
  475. u32 target;
  476. u32 enet1_ref;
  477. switch (type) {
  478. case ENET_125MHZ:
  479. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
  480. break;
  481. case ENET_50MHZ:
  482. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
  483. break;
  484. case ENET_25MHZ:
  485. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
  486. break;
  487. default:
  488. return -EINVAL;
  489. }
  490. /* disable the clock first */
  491. clock_enable(CCGR_ENET1, 0);
  492. clock_enable(CCGR_SIM_ENET, 0);
  493. /* set enet axi clock 266Mhz */
  494. target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
  495. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  496. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  497. clock_set_target_val(ENET_AXI_CLK_ROOT, target);
  498. target = CLK_ROOT_ON | enet1_ref |
  499. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  500. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  501. clock_set_target_val(ENET_REF_CLK_ROOT, target);
  502. target = CLK_ROOT_ON |
  503. ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
  504. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  505. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  506. clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
  507. #ifdef CONFIG_FEC_MXC_25M_REF_CLK
  508. target = CLK_ROOT_ON |
  509. ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK |
  510. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  511. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  512. clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);
  513. #endif
  514. /* enable clock */
  515. clock_enable(CCGR_SIM_ENET, 1);
  516. clock_enable(CCGR_ENET1, 1);
  517. return 0;
  518. }
  519. #endif
  520. u32 imx_get_fecclk(void)
  521. {
  522. return get_root_clk(ENET_AXI_CLK_ROOT);
  523. }
  524. #ifdef CONFIG_SPL_BUILD
  525. /*
  526. * 27-25 PLL_REF_DIVR1- SSCG_PLL_REF_DIVR1_VAL
  527. * 24-19 PLL_REF_DIVR2 - SSCG_PLL_REF_DIVR2_VAL
  528. * 18-13 PLL_FEEDBACK_DIVF1 - SSCG_PLL_FEEDBACK_DIV_F1_VAL
  529. * 12-7 PLL_FEEDBACK_DIVF2 - SSCG_PLL_FEEDBACK_DIV_F2_VAL
  530. * 6-1 PLL_OUTPUT_DIV_VAL - SSCG_PLL_OUTPUT_DIV_VAL
  531. * 0 PLL_FILTER_RANGE, 0 - 25-35 MHz, 1 - 35 to 54 MHz
  532. *
  533. * 700 0x00ec4580
  534. *
  535. */
  536. unsigned dram_cfg2[] = {
  537. /* 25/44*48*22/12= 100/2 (DDR) */
  538. /* 0x015dea96: 0000 000 101011 101111 010101 001011 0 */
  539. MHZ(100), SSCG_PLL_REF_DIVR2_VAL(43) | SSCG_PLL_FEEDBACK_DIV_F1_VAL(47) | SSCG_PLL_FEEDBACK_DIV_F2_VAL(21) | SSCG_PLL_OUTPUT_DIV_VAL(11),
  540. /* 25/31*46*9/4= 166.93/2 (DDR) */
  541. /* 0x00f5a406: 0000 000 011110 101101 001000 000011 0 */
  542. MHZ(167), SSCG_PLL_REF_DIVR2_VAL(30) | SSCG_PLL_FEEDBACK_DIV_F1_VAL(45) | SSCG_PLL_FEEDBACK_DIV_F2_VAL(8) | SSCG_PLL_OUTPUT_DIV_VAL(3),
  543. /* 25/30*45*8/3= 200/2 (DDR) */
  544. /* 0x00f5a406: 0000 000 011110 101101 001000 000011 0 */
  545. MHZ(200), SSCG_PLL_REF_DIVR2_VAL(30) | SSCG_PLL_FEEDBACK_DIV_F1_VAL(45) | SSCG_PLL_FEEDBACK_DIV_F2_VAL(8) | SSCG_PLL_OUTPUT_DIV_VAL(3),
  546. /* 25/30*40*12/3= 266.6/2 */
  547. MHZ(266), SSCG_PLL_REF_DIVR2_VAL(29) | SSCG_PLL_FEEDBACK_DIV_F1_VAL(39) | SSCG_PLL_FEEDBACK_DIV_F2_VAL(11) | SSCG_PLL_OUTPUT_DIV_VAL(2),
  548. /* 25/30*36*20/3= 400/2 (DDR) */
  549. /* 0x00ec6984: 0000 000 011101 100011 010011 000010 0 */
  550. MHZ(400), SSCG_PLL_REF_DIVR2_VAL(29) | SSCG_PLL_FEEDBACK_DIV_F1_VAL(35) | SSCG_PLL_FEEDBACK_DIV_F2_VAL(19) | SSCG_PLL_OUTPUT_DIV_VAL(2),
  551. /* 25/30*40*9= 600M/2 (DDR) */
  552. /* 0x00ece400: 0000 000 011101 100111 001000 000000 0 */
  553. MHZ(600), SSCG_PLL_REF_DIVR2_VAL(29) | SSCG_PLL_FEEDBACK_DIV_F1_VAL(39) | SSCG_PLL_FEEDBACK_DIV_F2_VAL(8) | SSCG_PLL_OUTPUT_DIV_VAL(0),
  554. /* 25/30*40*10= 667M/2 (DDR) */
  555. /* 0x00ece480: 0000 000 011101 100111 001001 000000 0 */
  556. MHZ(667), SSCG_PLL_REF_DIVR2_VAL(29) | SSCG_PLL_FEEDBACK_DIV_F1_VAL(39) | SSCG_PLL_FEEDBACK_DIV_F2_VAL(9) | SSCG_PLL_OUTPUT_DIV_VAL(0),
  557. /* 25/30*36*25/2= 750/2 */
  558. MHZ(750), SSCG_PLL_REF_DIVR2_VAL(29) | SSCG_PLL_FEEDBACK_DIV_F1_VAL(35) | SSCG_PLL_FEEDBACK_DIV_F2_VAL(24) | SSCG_PLL_OUTPUT_DIV_VAL(1),
  559. /* 25/30*40*12= 800M/2 (DDR) */
  560. /* 0x00ece580: 0000 000 011101 100111 001011 000000 0 */
  561. MHZ(800), SSCG_PLL_REF_DIVR2_VAL(29) | SSCG_PLL_FEEDBACK_DIV_F1_VAL(39) | SSCG_PLL_FEEDBACK_DIV_F2_VAL(11) | SSCG_PLL_OUTPUT_DIV_VAL(0),
  562. };
  563. void dram_pll_init(ulong pll_val)
  564. {
  565. struct src *src = (struct src *)SRC_BASE_ADDR;
  566. void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
  567. void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2;
  568. u32 pwdn_mask = 0, pll_clke = 0, bypass1 = 0, bypass2 = 0;
  569. u32 val;
  570. int ret;
  571. int i = 0;
  572. unsigned cfg2;
  573. while (1) {
  574. if (i >= ARRAY_SIZE(dram_cfg2)) {
  575. printf("%s: unsupported %ld\n", __func__, pll_val);
  576. return;
  577. }
  578. if (pll_val == dram_cfg2[i]) {
  579. cfg2 = dram_cfg2[i + 1];
  580. break;
  581. }
  582. i += 2;
  583. }
  584. setbits_le32(GPC_BASE_ADDR + 0xEC, BIT(7));
  585. setbits_le32(GPC_BASE_ADDR + 0xF8, BIT(5));
  586. pwdn_mask = SSCG_PLL_PD_MASK;
  587. pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
  588. bypass1 = SSCG_PLL_BYPASS1_MASK;
  589. bypass2 = SSCG_PLL_BYPASS2_MASK;
  590. /* Enable DDR1 and DDR2 domain */
  591. writel(SRC_DDR1_ENABLE_MASK, &src->ddr1_rcr);
  592. writel(SRC_DDR1_ENABLE_MASK, &src->ddr2_rcr);
  593. /* Bypass */
  594. setbits_le32(pll_control_reg, bypass2);
  595. setbits_le32(pll_control_reg, bypass1);
  596. val = readl(pll_cfg_reg2);
  597. val &= ~(SSCG_PLL_REF_DIVR2_MASK | SSCG_PLL_FEEDBACK_DIV_F1_MASK |
  598. SSCG_PLL_FEEDBACK_DIV_F2_MASK | SSCG_PLL_OUTPUT_DIV_VAL_MASK);
  599. val |= cfg2;
  600. writel(val, pll_cfg_reg2);
  601. /* Clear power down bit */
  602. clrbits_le32(pll_control_reg, pwdn_mask);
  603. /* Enable ARM_PLL/SYS_PLL */
  604. setbits_le32(pll_control_reg, pll_clke);
  605. /* Clear bypass */
  606. clrbits_le32(pll_control_reg, bypass1);
  607. __udelay(100);
  608. clrbits_le32(pll_control_reg, bypass2);
  609. /* Wait lock */
  610. ret = readl_poll_timeout(pll_control_reg, val,
  611. val & SSCG_PLL_LOCK_MASK, 10);
  612. if (ret)
  613. printf("%s timeout\n", __func__);
  614. }
  615. int frac_pll_init(u32 pll, enum frac_pll_out_val val)
  616. {
  617. void __iomem *pll_cfg0, __iomem *pll_cfg1;
  618. uint32_t val_cfg0, val_cfg1;
  619. int ret;
  620. switch (pll) {
  621. case ANATOP_ARM_PLL:
  622. pll_cfg0 = &ana_pll->arm_pll_cfg0;
  623. pll_cfg1 = &ana_pll->arm_pll_cfg1;
  624. if (val == FRAC_PLL_OUT_1000M)
  625. val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49);
  626. else
  627. val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79);
  628. val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M |
  629. FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK |
  630. FRAC_PLL_REFCLK_DIV_VAL(4) |
  631. FRAC_PLL_OUTPUT_DIV_VAL(0);
  632. break;
  633. default:
  634. return -EINVAL;
  635. }
  636. /* bypass the clock */
  637. setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
  638. /* Set the value */
  639. writel(val_cfg1, pll_cfg1);
  640. writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0);
  641. val_cfg0 = readl(pll_cfg0);
  642. /* unbypass the clock */
  643. clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
  644. ret = readl_poll_timeout(pll_cfg0, val_cfg0,
  645. val_cfg0 & FRAC_PLL_LOCK_MASK, 1);
  646. if (ret)
  647. printf("%s timeout\n", __func__);
  648. clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK);
  649. return 0;
  650. }
  651. int sscg_pll_init(u32 pll)
  652. {
  653. void __iomem *pll_cfg0, __iomem *pll_cfg1, __iomem *pll_cfg2;
  654. uint32_t val_cfg0, val_cfg1, val_cfg2, val;
  655. uint32_t bypass1_mask = 0x20, bypass2_mask = 0x10;
  656. int ret;
  657. switch (pll) {
  658. case ANATOP_SYSTEM_PLL1:
  659. pll_cfg0 = &ana_pll->sys_pll1_cfg0;
  660. pll_cfg1 = &ana_pll->sys_pll1_cfg1;
  661. pll_cfg2 = &ana_pll->sys_pll1_cfg2;
  662. /* 800MHz */
  663. val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
  664. SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
  665. val_cfg1 = 0;
  666. val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
  667. SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
  668. SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
  669. SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
  670. SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
  671. SSCG_PLL_REFCLK_SEL_OSC_25M;
  672. break;
  673. case ANATOP_SYSTEM_PLL2:
  674. pll_cfg0 = &ana_pll->sys_pll2_cfg0;
  675. pll_cfg1 = &ana_pll->sys_pll2_cfg1;
  676. pll_cfg2 = &ana_pll->sys_pll2_cfg2;
  677. /* 1000MHz */
  678. val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
  679. SSCG_PLL_FEEDBACK_DIV_F2_VAL(4);
  680. val_cfg1 = 0;
  681. val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
  682. SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
  683. SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
  684. SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
  685. SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
  686. SSCG_PLL_REFCLK_SEL_OSC_25M;
  687. break;
  688. case ANATOP_SYSTEM_PLL3:
  689. pll_cfg0 = &ana_pll->sys_pll3_cfg0;
  690. pll_cfg1 = &ana_pll->sys_pll3_cfg1;
  691. pll_cfg2 = &ana_pll->sys_pll3_cfg2;
  692. /* 800MHz */
  693. val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
  694. SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
  695. val_cfg1 = 0;
  696. val_cfg0 = SSCG_PLL_PLL3_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
  697. SSCG_PLL_REFCLK_SEL_OSC_25M;
  698. break;
  699. default:
  700. return -EINVAL;
  701. }
  702. /*bypass*/
  703. setbits_le32(pll_cfg0, bypass1_mask | bypass2_mask);
  704. /* set value */
  705. writel(val_cfg2, pll_cfg2);
  706. writel(val_cfg1, pll_cfg1);
  707. /*unbypass1 and wait 70us */
  708. writel(val_cfg0 | bypass2_mask, pll_cfg1);
  709. __udelay(70);
  710. /* unbypass2 and wait lock */
  711. writel(val_cfg0, pll_cfg1);
  712. ret = readl_poll_timeout(pll_cfg0, val, val & SSCG_PLL_LOCK_MASK, 1);
  713. if (ret)
  714. printf("%s timeout\n", __func__);
  715. return ret;
  716. }
  717. int clock_init(void)
  718. {
  719. u32 grade;
  720. clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
  721. CLK_ROOT_SOURCE_SEL(0));
  722. /*
  723. * 8MQ only supports two grades: consumer and industrial.
  724. * We set ARM clock to 1Ghz for consumer, 800Mhz for industrial
  725. */
  726. grade = get_cpu_temp_grade(NULL, NULL);
  727. if (!grade) {
  728. frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M);
  729. clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
  730. CLK_ROOT_SOURCE_SEL(1) |
  731. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
  732. } else {
  733. frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1600M);
  734. clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
  735. CLK_ROOT_SOURCE_SEL(1) |
  736. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
  737. }
  738. /*
  739. * According to ANAMIX SPEC
  740. * sys pll1 fixed at 800MHz
  741. * sys pll2 fixed at 1GHz
  742. * Here we only enable the outputs.
  743. */
  744. setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK |
  745. SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
  746. SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
  747. SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
  748. SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
  749. setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK |
  750. SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
  751. SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
  752. SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
  753. SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
  754. clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
  755. CLK_ROOT_SOURCE_SEL(1));
  756. init_wdog_clk();
  757. clock_enable(CCGR_TSENSOR, 1);
  758. clock_enable(CCGR_OCOTP, 1);
  759. return 0;
  760. }
  761. #endif
  762. /*
  763. * Dump some clockes.
  764. */
  765. #ifndef CONFIG_SPL_BUILD
  766. static int do_mx8mq_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
  767. char * const argv[])
  768. {
  769. u32 freq;
  770. freq = decode_frac_pll(ARM_PLL_CLK);
  771. printf("ARM_PLL %8d MHz\n", freq / 1000000);
  772. freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
  773. printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
  774. freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
  775. printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
  776. freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK);
  777. printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
  778. freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK);
  779. printf("SYS_PLL1_200 %8d MHz\n", freq / 1000000);
  780. freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK);
  781. printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
  782. freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK);
  783. printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
  784. freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK);
  785. printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
  786. freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK);
  787. printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
  788. freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK);
  789. printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
  790. freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK);
  791. printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
  792. freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK);
  793. printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
  794. freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK);
  795. printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
  796. freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK);
  797. printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
  798. freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK);
  799. printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
  800. freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK);
  801. printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
  802. freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK);
  803. printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
  804. freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK);
  805. printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
  806. freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK);
  807. printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
  808. freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
  809. printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
  810. freq = mxc_get_clock(UART1_CLK_ROOT);
  811. printf("UART1 %8d MHz\n", freq / 1000000);
  812. freq = mxc_get_clock(USDHC1_CLK_ROOT);
  813. printf("USDHC1 %8d MHz\n", freq / 1000000);
  814. freq = mxc_get_clock(QSPI_CLK_ROOT);
  815. printf("QSPI %8d MHz\n", freq / 1000000);
  816. return 0;
  817. }
  818. U_BOOT_CMD(
  819. clocks, CONFIG_SYS_MAXARGS, 1, do_mx8mq_showclocks,
  820. "display clocks",
  821. ""
  822. );
  823. #endif
  824. int mx8mq_showclocks() {
  825. u32 freq;
  826. freq = decode_frac_pll(ARM_PLL_CLK);
  827. printf("ARM_PLL %8d MHz\n", freq / 1000000);
  828. freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
  829. printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
  830. freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
  831. printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
  832. freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK);
  833. printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
  834. freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK);
  835. printf("SYS_PLL1_200 %8d MHz\n", freq / 1000000);
  836. freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK);
  837. printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
  838. freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK);
  839. printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
  840. freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK);
  841. printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
  842. freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK);
  843. printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
  844. freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK);
  845. printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
  846. freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK);
  847. printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
  848. freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK);
  849. printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
  850. freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK);
  851. printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
  852. freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK);
  853. printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
  854. freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK);
  855. printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
  856. freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK);
  857. printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
  858. freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK);
  859. printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
  860. freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK);
  861. printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
  862. freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK);
  863. printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
  864. freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
  865. printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
  866. freq = mxc_get_clock(UART1_CLK_ROOT);
  867. printf("UART1 %8d MHz\n", freq / 1000000);
  868. freq = mxc_get_clock(USDHC1_CLK_ROOT);
  869. printf("USDHC1 %8d MHz\n", freq / 1000000);
  870. freq = mxc_get_clock(QSPI_CLK_ROOT);
  871. printf("QSPI %8d MHz\n", freq / 1000000);
  872. return 0;
  873. }