Fork of the vendor (Boundary Devices) u-boot for Reform 2, with minor tweaks. The goal is to migrate to mainstream u-boot or barebox ASAP. The main impediment so far is the 4GB RAM config.
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 
 
 
 
 
 

64 lines
1.5 KiB

  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
  4. */
  5. #include <common.h>
  6. #include <mmc.h>
  7. #include <pci_ids.h>
  8. #include <asm/irq.h>
  9. #include <asm/mrccache.h>
  10. #include <asm/post.h>
  11. #include <asm/arch/iomap.h>
  12. /* GPIO SUS */
  13. #define GPIO_SUS_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS)
  14. #define GPIO_SUS_DFX5_CONF0 0x150
  15. #define BYT_TRIG_LVL BIT(24)
  16. #define BYT_TRIG_POS BIT(25)
  17. int arch_cpu_init(void)
  18. {
  19. post_code(POST_CPU_INIT);
  20. return x86_cpu_init_f();
  21. }
  22. int arch_misc_init(void)
  23. {
  24. if (!ll_boot_init())
  25. return 0;
  26. #ifdef CONFIG_ENABLE_MRC_CACHE
  27. /*
  28. * We intend not to check any return value here, as even MRC cache
  29. * is not saved successfully, it is not a severe error that will
  30. * prevent system from continuing to boot.
  31. */
  32. mrccache_save();
  33. #endif
  34. /*
  35. * For some unknown reason, FSP (gold4) for BayTrail configures
  36. * the GPIO DFX5 PAD to enable level interrupt (bit 24 and 25).
  37. * This does not cause any issue when Linux kernel runs w/ or w/o
  38. * the pinctrl driver for BayTrail. However this causes unstable
  39. * S3 resume if the pinctrl driver is included in the kernel build.
  40. * As this pin keeps generating interrupts during an S3 resume,
  41. * and there is no IRQ requester in the kernel to handle it, the
  42. * kernel seems to hang and does not continue resuming.
  43. *
  44. * Clear the mysterious interrupt bits for this pin.
  45. */
  46. clrbits_le32(GPIO_SUS_PAD_BASE + GPIO_SUS_DFX5_CONF0,
  47. BYT_TRIG_LVL | BYT_TRIG_POS);
  48. return 0;
  49. }
  50. void reset_cpu(ulong addr)
  51. {
  52. /* cold reset */
  53. x86_full_reset();
  54. }