Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

This reverts commit 308ca269d0.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

nw2 seems to need this change. Data sheet says 104 ns. This
is a little more.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

This seems to fix the flicker issue on i.MX8MM

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

This seems to fix the flicker issue on i.MX8MM

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

Support pinctrl/clk/sdhc, include ddr4 timing data.

Log:
U-Boot SPL 2019.10-rc3-00356-g497c500423-dirty (Sep 16 2019 - 10:54:58 +0800)
Normal Boot
Trying to boot from BOOTROM
image offset 0x8000, pagesize 0x200, ivt offset 0x0

U-Boot 2019.10-rc3-00356-g497c500423-dirty (Sep 16 2019 - 10:54:58 +0800)

CPU:   Freescale i.MX8MNano rev1.0 at 24 MHz
Reset cause: POR
Model: NXP i.MX8MNano DDR4 EVK board
DRAM:  2 GiB
MMC:   FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... *** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   No ethernet found.
Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <peng.fan@nxp.com>

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

SPL/TPL also need use sysreset for some feature like panic callback.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

Introduce DDR driver for i.MX8M. The driver will be used by SPL to
initialze DDR PHY and DDR Controller.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

ddr: imx8m: Fix ddr4 driver build issue

Since the parameter of dram_pll_init is changed, update to use new.
Also remove non-existed header file.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

Add dtsi for i.MX8MN

Signed-off-by: Peng Fan <peng.fan@nxp.com>

Make reset_cpu only visible when CONFIG_SYSRESET not defined
or CONFIG_SPL_BUILD.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

Add cfg file for i.MX8MN DDR4

Signed-off-by: Peng Fan <peng.fan@nxp.com>

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

some boards use ddr4, not lpddr4, so we need to check ddr4 firmware.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

Support i.MX8MN in imx8m pinctrl driver

Signed-off-by: Peng Fan <peng.fan@nxp.com>

The IVT offset is changed on i.MX8MN. Use ROM_VERSION to pass the
v1 or v2 to mkimage.
v1 is for iMX8MQ and iMX8MM
v2 is for iMX8M Nano (iMX8MN)

Signed-off-by: Peng Fan <peng.fan@nxp.com>

No ROM INFO structure on iMX8MN, use new ROM API to get boot device
from ROM.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

i.MX8MN has its own get_boot_device, so restrict with i.MX8MQ and
i.MX8MM.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

i.MX8MN support loading images with rom api, so we implement
reuse board_return_to_bootrom to let ROM loading images.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

Add pin header for i.MX8MN

Signed-off-by: Peng Fan <peng.fan@nxp.com>

i.MX8MN does not have LVTTL, it has a PE property

Signed-off-by: Peng Fan <peng.fan@nxp.com>

Set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to
generated AXI bus errors with TZC380 enabled.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

i.MX8MN has similar architecture with i.MX8MM, so it could reuse
the clock code of i.MX8MM, but i.MX8MN has different CCM root
configurations, so need a separate root entry.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

Add a dummy cpu type and support get_cpu_rev for i.MX8MN

Signed-off-by: Peng Fan <peng.fan@nxp.com>

The i.MX8MQ B1 uses OCOTP_HW_OCOTP_READ_FUSE_DATA register for chip id.
It returns a magic number 0xff0055aa. update get_cpu_rev to support it,
and enable ocotp clock to access ocotp.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

Introduce CHIP_REV_2_1 macro.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

There are several variants based on i.MX8MM, add the support in
get_cpu_rev

Signed-off-by: Peng Fan <peng.fan@nxp.com>