Browse Source

Xilinx fixes for v2018.07-rc2

Zynq:
 - Fix missing watchdog header
 - DT fixes
 
 ZynqMP:
 - emmc configuration split
 - Enable SPD
 - Fix PMUFW_INIT_FILE logic
 - Coverity fixes in SoC code
 
 timer
 - Add timer_get_boot_us
 
 mmc:
 - Fix MMC HS200 tuning command
 
 serial:
 - Fix scrabled chars with OF_LIVE
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Merge tag 'xilinx-for-v2018.07-rc2' of git://git.denx.de/u-boot-microblaze

Xilinx fixes for v2018.07-rc2

Zynq:
- Fix missing watchdog header
- DT fixes

ZynqMP:
- emmc configuration split
- Enable SPD
- Fix PMUFW_INIT_FILE logic
- Coverity fixes in SoC code

timer
- Add timer_get_boot_us

mmc:
- Fix MMC HS200 tuning command

serial:
- Fix scrabled chars with OF_LIVE
tags/2020-06-01
Tom Rini 2 years ago
parent
commit
d94e89c765
25 changed files with 196 additions and 49 deletions
  1. +5
    -1
      arch/arm/cpu/armv8/zynqmp/cpu.c
  2. +2
    -1
      arch/arm/dts/Makefile
  3. +0
    -2
      arch/arm/dts/zynq-zc702.dts
  4. +0
    -2
      arch/arm/dts/zynq-zturn.dts
  5. +6
    -14
      arch/arm/dts/zynqmp-mini-emmc0.dts
  6. +67
    -0
      arch/arm/dts/zynqmp-mini-emmc1.dts
  7. +0
    -2
      arch/arm/dts/zynqmp-zcu100-revC.dts
  8. +0
    -2
      arch/arm/dts/zynqmp-zcu102-revA.dts
  9. +0
    -2
      arch/arm/dts/zynqmp-zcu106-revA.dts
  10. +0
    -2
      arch/arm/dts/zynqmp-zcu111-revA.dts
  11. +1
    -0
      board/xilinx/zynq/board.c
  12. +2
    -0
      board/xilinx/zynqmp/zynqmp.c
  13. +2
    -1
      configs/xilinx_zynqmp_mini_emmc0_defconfig
  14. +49
    -0
      configs/xilinx_zynqmp_mini_emmc1_defconfig
  15. +2
    -0
      configs/xilinx_zynqmp_r5_defconfig
  16. +1
    -0
      configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
  17. +1
    -0
      configs/xilinx_zynqmp_zcu102_revA_defconfig
  18. +1
    -0
      configs/xilinx_zynqmp_zcu102_revB_defconfig
  19. +5
    -5
      drivers/gpio/zynq_gpio.c
  20. +4
    -4
      drivers/mmc/sdhci.c
  21. +1
    -1
      drivers/mmc/zynq_sdhci.c
  22. +15
    -9
      drivers/serial/serial_zynq.c
  23. +22
    -0
      drivers/timer/cadence-ttc.c
  24. +3
    -0
      include/configs/xilinx_zynqmp_zcu102.h
  25. +7
    -1
      scripts/Makefile.spl

+ 5
- 1
arch/arm/cpu/armv8/zynqmp/cpu.c View File

@@ -212,8 +212,12 @@ static int zynqmp_mmio_rawwrite(const u32 address,
{
u32 data;
u32 value_local = value;
int ret;

ret = zynqmp_mmio_read(address, &data);
if (ret)
return ret;

zynqmp_mmio_read(address, &data);
data &= ~mask;
value_local &= mask;
value_local |= data;


+ 2
- 1
arch/arm/dts/Makefile View File

@@ -147,7 +147,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zturn.dtb \
zynq-zybo.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-mini-emmc.dtb \
zynqmp-mini-emmc0.dtb \
zynqmp-mini-emmc1.dtb \
zynqmp-mini-nand.dtb \
zynqmp-zcu100-revC.dtb \
zynqmp-zcu102-revA.dtb \


+ 0
- 2
arch/arm/dts/zynq-zc702.dts View File

@@ -30,8 +30,6 @@

gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
sw14 {
label = "sw14";


+ 0
- 2
arch/arm/dts/zynq-zturn.dts View File

@@ -49,8 +49,6 @@

gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
K1 {
label = "K1";


arch/arm/dts/zynqmp-mini-emmc.dts → arch/arm/dts/zynqmp-mini-emmc0.dts View File

@@ -18,7 +18,6 @@
aliases {
serial0 = &dcc;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
};

chosen {
@@ -36,6 +35,12 @@
u-boot,dm-pre-reloc;
};

clk_xin: clk_xin {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};

amba: amba {
compatible = "simple-bus";
#address-cells = <2>;
@@ -50,15 +55,6 @@
clock-names = "clk_xin", "clk_ahb";
xlnx,device_id = <0>;
};

sdhci1: sdhci@ff170000 {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
reg = <0x0 0xff170000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
xlnx,device_id = <1>;
};
};
};

@@ -69,7 +65,3 @@
&sdhci0 {
status = "okay";
};

&sdhci1 {
status = "okay";
};

+ 67
- 0
arch/arm/dts/zynqmp-mini-emmc1.dts View File

@@ -0,0 +1,67 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP Mini Configuration
*
* (C) Copyright 2018, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
*/

/dts-v1/;

/ {
model = "ZynqMP MINI EMMC";
compatible = "xlnx,zynqmp";
#address-cells = <2>;
#size-cells = <2>;

aliases {
serial0 = &dcc;
mmc0 = &sdhci1;
};

chosen {
stdout-path = "serial0:115200n8";
};

memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x20000000>;
};

dcc: dcc {
compatible = "arm,dcc";
status = "disabled";
u-boot,dm-pre-reloc;
};

clk_xin: clk_xin {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};

amba: amba {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;

sdhci1: sdhci@ff170000 {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
reg = <0x0 0xff170000 0x0 0x1000>;
clock-names = "clk_xin", "clk_xin";
xlnx,device_id = <1>;
};
};
};

&dcc {
status = "okay";
};

&sdhci1 {
status = "okay";
};

+ 0
- 2
arch/arm/dts/zynqmp-zcu100-revC.dts View File

@@ -48,8 +48,6 @@

gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
sw4 {
label = "sw4";


+ 0
- 2
arch/arm/dts/zynqmp-zcu102-revA.dts View File

@@ -45,8 +45,6 @@

gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
sw19 {
label = "sw19";


+ 0
- 2
arch/arm/dts/zynqmp-zcu106-revA.dts View File

@@ -45,8 +45,6 @@

gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
sw19 {
label = "sw19";


+ 0
- 2
arch/arm/dts/zynqmp-zcu111-revA.dts View File

@@ -45,8 +45,6 @@

gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
sw19 {
label = "sw19";


+ 1
- 0
board/xilinx/zynq/board.c View File

@@ -9,6 +9,7 @@
#include <fdtdec.h>
#include <fpga.h>
#include <mmc.h>
#include <watchdog.h>
#include <wdt.h>
#include <zynqpl.h>
#include <asm/arch/hardware.h>


+ 2
- 0
board/xilinx/zynqmp/zynqmp.c View File

@@ -596,6 +596,8 @@ int board_late_init(void)

new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
bootseq_len);
if (!new_targets)
return -ENOMEM;

if (bootseq >= 0)
sprintf(new_targets, "%s%x %s", mode, bootseq,


configs/xilinx_zynqmp_mini_emmc_defconfig → configs/xilinx_zynqmp_mini_emmc0_defconfig View File

@@ -3,7 +3,7 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_emmc"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x10000
# CONFIG_CMD_ZYNQMP is not set
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc"
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc0"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=-1
@@ -45,4 +45,5 @@ CONFIG_OF_EMBED=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
# CONFIG_EFI_LOADER is not set

+ 49
- 0
configs/xilinx_zynqmp_mini_emmc1_defconfig View File

@@ -0,0 +1,49 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_emmc"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x10000
# CONFIG_CMD_ZYNQMP is not set
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc1"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=-1
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_BOOTI is not set
# CONFIG_CMD_GO is not set
# CONFIG_CMD_RUN is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_SAVEENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
# CONFIG_CMD_CRC32 is not set
# CONFIG_CMD_DM is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_ECHO is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
# CONFIG_NET is not set
# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
# CONFIG_EFI_LOADER is not set

+ 2
- 0
configs/xilinx_zynqmp_r5_defconfig View File

@@ -5,10 +5,12 @@ CONFIG_DEBUG_UART_BASE=0xff010000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-r5"
CONFIG_DEBUG_UART=y
CONFIG_BOOTSTAGE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="ZynqMP r5> "
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_BOOTSTAGE=y
CONFIG_OF_EMBED=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_ZYNQ_SERIAL=y


+ 1
- 0
configs/xilinx_zynqmp_zcu102_rev1_0_defconfig View File

@@ -35,6 +35,7 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TIME=y


+ 1
- 0
configs/xilinx_zynqmp_zcu102_revA_defconfig View File

@@ -34,6 +34,7 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TIME=y


+ 1
- 0
configs/xilinx_zynqmp_zcu102_revB_defconfig View File

@@ -34,6 +34,7 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TIME=y


+ 5
- 5
drivers/gpio/zynq_gpio.c View File

@@ -111,9 +111,9 @@ struct zynq_gpio_privdata {
struct zynq_platform_data {
const char *label;
u16 ngpio;
int max_bank;
int bank_min[ZYNQMP_GPIO_MAX_BANK];
int bank_max[ZYNQMP_GPIO_MAX_BANK];
u32 max_bank;
u32 bank_min[ZYNQMP_GPIO_MAX_BANK];
u32 bank_max[ZYNQMP_GPIO_MAX_BANK];
};

static const struct zynq_platform_data zynqmp_gpio_def = {
@@ -165,7 +165,7 @@ static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
struct udevice *dev)
{
struct zynq_gpio_privdata *priv = dev_get_priv(dev);
int bank;
u32 bank;

for (bank = 0; bank < priv->p_data->max_bank; bank++) {
if ((pin_num >= priv->p_data->bank_min[bank]) &&
@@ -188,7 +188,7 @@ static int gpio_is_valid(unsigned gpio, struct udevice *dev)
{
struct zynq_gpio_privdata *priv = dev_get_priv(dev);

return (gpio >= 0) && (gpio < priv->p_data->ngpio);
return gpio < priv->p_data->ngpio;
}

static int check_gpio(unsigned gpio, struct udevice *dev)


+ 4
- 4
drivers/mmc/sdhci.c View File

@@ -161,8 +161,8 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
/* We shouldn't wait for data inihibit for stop commands, even
though they might use busy signaling */
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
mask &= ~SDHCI_DATA_INHIBIT;

while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
@@ -184,8 +184,8 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);

mask = SDHCI_INT_RESPONSE;
if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
mask = SDHCI_INT_DATA_AVAIL;

if (!(cmd->resp_type & MMC_RSP_PRESENT))


+ 1
- 1
drivers/mmc/zynq_sdhci.c View File

@@ -92,7 +92,7 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
u32 ctrl;
struct sdhci_host *host;
struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
u8 tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
u8 deviceid;

debug("%s\n", __func__);


+ 15
- 9
drivers/serial/serial_zynq.c View File

@@ -15,14 +15,16 @@
#include <linux/compiler.h>
#include <serial.h>

#define ZYNQ_UART_SR_TXEMPTY (1 << 3) /* TX FIFO empty */
#define ZYNQ_UART_SR_TXACTIVE (1 << 11) /* TX active */
#define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
DECLARE_GLOBAL_DATA_PTR;

#define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */
#define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */
#define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */
#define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */
#define ZYNQ_UART_SR_TXACTIVE BIT(11) /* TX active */
#define ZYNQ_UART_SR_TXFULL BIT(4) /* TX FIFO full */
#define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */

#define ZYNQ_UART_CR_TX_EN BIT(4) /* TX enabled */
#define ZYNQ_UART_CR_RX_EN BIT(2) /* RX enabled */
#define ZYNQ_UART_CR_TXRST BIT(1) /* TX logic reset */
#define ZYNQ_UART_CR_RXRST BIT(0) /* RX logic reset */

#define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */

@@ -93,7 +95,7 @@ static void _uart_zynq_serial_init(struct uart_zynq *regs)

static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
{
if (!(readl(&regs->channel_sts) & ZYNQ_UART_SR_TXEMPTY))
if (readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL)
return -EAGAIN;

writel(c, &regs->tx_rx_fifo);
@@ -101,7 +103,7 @@ static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
return 0;
}

int zynq_serial_setbrg(struct udevice *dev, int baudrate)
static int zynq_serial_setbrg(struct udevice *dev, int baudrate)
{
struct zynq_uart_priv *priv = dev_get_priv(dev);
unsigned long clock;
@@ -137,6 +139,10 @@ static int zynq_serial_probe(struct udevice *dev)
{
struct zynq_uart_priv *priv = dev_get_priv(dev);

/* No need to reinitialize the UART after relocation */
if (gd->flags & GD_FLG_RELOC)
return 0;

_uart_zynq_serial_init(priv->regs);

return 0;


+ 22
- 0
drivers/timer/cadence-ttc.c View File

@@ -31,6 +31,28 @@ struct cadence_ttc_priv {
struct cadence_ttc_regs *regs;
};

#if CONFIG_IS_ENABLED(BOOTSTAGE)
ulong timer_get_boot_us(void)
{
u64 ticks = 0;
u32 rate = 1;
u64 us;
int ret;

ret = dm_timer_init();
if (!ret) {
/* The timer is available */
rate = timer_get_rate(gd->timer);
timer_get_count(gd->timer, &ticks);
} else {
return 0;
}

us = (ticks * 1000) / rate;
return us;
}
#endif

static int cadence_ttc_get_count(struct udevice *dev, u64 *count)
{
struct cadence_ttc_priv *priv = dev_get_priv(dev);


+ 3
- 0
include/configs/xilinx_zynqmp_zcu102.h View File

@@ -39,6 +39,9 @@
#define CONFIG_ZYNQ_EEPROM_BUS 5
#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54

#define CONFIG_SPD_EEPROM
#define CONFIG_DDR_SPD

#include <configs/xilinx_zynqmp.h>

#endif /* __CONFIG_ZYNQMP_ZCU102_H */

+ 7
- 1
scripts/Makefile.spl View File

@@ -167,8 +167,14 @@ ifdef CONFIG_ARCH_ZYNQ
MKIMAGEFLAGS_boot.bin = -T zynqimage -R $(srctree)/$(CONFIG_BOOT_INIT_FILE)
endif
ifdef CONFIG_ARCH_ZYNQMP
ifneq ($(CONFIG_PMUFW_INIT_FILE),"")
spl/boot.bin: zynqmp-check-pmufw
zynqmp-check-pmufw: FORCE
( cd $(srctree) && test -r $(CONFIG_PMUFW_INIT_FILE) ) \
|| ( echo "Cannot read $(CONFIG_PMUFW_INIT_FILE)" && false )
endif
MKIMAGEFLAGS_boot.bin = -T zynqmpimage -R $(srctree)/$(CONFIG_BOOT_INIT_FILE) \
-n $(srctree)/$(CONFIG_PMUFW_INIT_FILE)
-n "$(shell cd $(srctree); readlink -f $(CONFIG_PMUFW_INIT_FILE))"
endif

spl/boot.bin: $(obj)/u-boot-spl.bin FORCE


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