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@@ -54,6 +54,8 @@ int board_mmc_getcd(struct mmc *mmc) |
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switch (cfg->esdhc_base) { |
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case USDHC1_BASE_ADDR: |
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return 1; |
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case USDHC2_BASE_ADDR: |
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return 1; |
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} |
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return 0; |
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} |
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@@ -62,6 +64,10 @@ int board_mmc_getcd(struct mmc *mmc) |
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PAD_CTL_FSEL2) |
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#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) |
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#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) |
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#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) |
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#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) |
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static iomux_v3_cfg_t const init_pads[] = { |
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#define GP_I2C1_PCA9546_RESET IMX_GPIO_NR(1, 4) |
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IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(0x46), |
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@@ -78,11 +84,22 @@ static iomux_v3_cfg_t const init_pads[] = { |
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IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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#define GP_EMMC_RESET IMX_GPIO_NR(2, 10) |
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IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ |
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IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ |
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IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ |
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IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ |
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IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ |
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IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ |
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IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), |
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IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), |
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}; |
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static struct fsl_esdhc_cfg usdhc_cfg[] = { |
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{.esdhc_base = USDHC1_BASE_ADDR, .bus_width = 8, |
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.gp_reset = GP_EMMC_RESET}, |
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{.esdhc_base = USDHC2_BASE_ADDR, .bus_width = 1, |
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.gp_reset = USDHC2_PWR_GPIO}, |
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}; |
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int board_mmc_init(bd_t *bis) |
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@@ -103,12 +120,20 @@ int board_mmc_init(bd_t *bis) |
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udelay(500); |
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gpio_direction_output(GP_EMMC_RESET, 1); |
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break; |
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case 1: |
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); |
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gpio_request(GP_EMMC_RESET, "usdhc2_reset"); |
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gpio_direction_output(USDHC2_PWR_GPIO, 0); |
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udelay(500); |
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gpio_direction_output(USDHC2_PWR_GPIO, 1); |
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break; |
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default: |
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printf("Warning: you configured more USDHC controllers" |
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"(%d) than supported by the board\n", i + 1); |
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return -EINVAL; |
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} |
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printf("board_mmc_init: %d\n",i); |
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); |
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if (ret) |
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return ret; |
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@@ -192,11 +217,25 @@ int board_fit_config_name_match(const char *name) |
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{ |
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/* Just empty function now - can't decide what to choose */ |
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debug("%s: %s\n", __func__, name); |
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return 0; |
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return 0; |
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} |
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#endif |
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static void hexdump(unsigned char *buf, int len) |
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{ |
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int i; |
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for (i = 0; i < len; i++) { |
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if ((i % 16) == 0) |
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printf("%s%08x: ", i ? "\n" : "", |
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(unsigned int)&buf[i]); |
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printf("%02x ", buf[i]); |
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} |
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printf("\n"); |
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} |
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int mx8mq_showclocks(); |
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void board_init_f(ulong dummy) |
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{ |
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int ret; |
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@@ -206,6 +245,7 @@ void board_init_f(ulong dummy) |
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arch_cpu_init(); |
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// without this, no uart output |
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board_early_init_f(); |
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init_uart_clk(0); |
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timer_init(); |
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@@ -215,13 +255,14 @@ void board_init_f(ulong dummy) |
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/* Clear the BSS. */ |
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memset(__bss_start, 0, __bss_end - __bss_start); |
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ret = spl_init(); |
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//ret = spl_init(); |
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if (ret) { |
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printf("spl_init() failed: %d\n", ret); |
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hang(); |
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} |
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enable_tzc380(); |
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// without this, no uart output |
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imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads)); |
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/* Adjust pmic voltage to 1.0V for 800M */ |
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@@ -232,5 +273,13 @@ void board_init_f(ulong dummy) |
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/* DDR initialization */ |
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spl_dram_init(); |
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mx8mq_showclocks(); |
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// FIXME: quick DDR test |
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for (int i=0; i<256; i++) { |
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*((uint8_t*)0x42000000+i) = i; |
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} |
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hexdump(0x42000000, 512); |
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board_init_r(NULL, 0); |
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} |