Browse Source

son: initial addition, Boundary Devices board

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
master
Troy Kisky 7 months ago
parent
commit
5e63b20ab8
9 changed files with 3607 additions and 0 deletions
  1. +1372
    -0
      arch/arm/dts/imx8mq-son.dts
  2. +6
    -0
      arch/arm/mach-imx/imx8m/Kconfig
  3. +18
    -0
      board/boundary/son/Kconfig
  4. +12
    -0
      board/boundary/son/Makefile
  5. +1258
    -0
      board/boundary/son/lpddr4_timing.c
  6. +336
    -0
      board/boundary/son/son.c
  7. +242
    -0
      board/boundary/son/spl.c
  8. +106
    -0
      configs/son_2g_defconfig
  9. +257
    -0
      include/configs/son.h

+ 1372
- 0
arch/arm/dts/imx8mq-son.dts
File diff suppressed because it is too large
View File


+ 6
- 0
arch/arm/mach-imx/imx8m/Kconfig View File

@@ -55,6 +55,11 @@ config TARGET_NITROGEN8MM_SOM
select IMX8MM
select SUPPORT_SPL

config TARGET_SON
bool "son"
select IMX8MQ
select SUPPORT_SPL

config TARGET_IMX8MM_EVK
bool "imx8mm_evk"
select IMX8MM
@@ -85,5 +90,6 @@ source "board/boundary/nitrogen8m/Kconfig"
source "board/boundary/nitrogen8m_som/Kconfig"
source "board/boundary/nitrogen8mm/Kconfig"
source "board/boundary/nitrogen8mm_som/Kconfig"
source "board/boundary/son/Kconfig"
source "board/freescale/imx8mm_evk/Kconfig"
endif

+ 18
- 0
board/boundary/son/Kconfig View File

@@ -0,0 +1,18 @@
if TARGET_SON

config SYS_BOARD
default "son"

config SYS_VENDOR
default "boundary"

config SYS_CONFIG_NAME
default "son"

config DDR_RANK_BITS
int "ddr rank bits"
default 1

source "board/boundary/common/Kconfig"

endif

+ 12
- 0
board/boundary/son/Makefile View File

@@ -0,0 +1,12 @@
#
# Copyright 2016 Freescale Semiconductor
#
# SPDX-License-Identifier: GPL-2.0+
#

obj-y += son.o

ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-y += lpddr4_timing.o
endif

+ 1258
- 0
board/boundary/son/lpddr4_timing.c
File diff suppressed because it is too large
View File


+ 336
- 0
board/boundary/son/son.c View File

@@ -0,0 +1,336 @@
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/

#include <common.h>
#include <malloc.h>
#include <errno.h>
#include <asm/io.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/fbpanel.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm-generic/gpio.h>
#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/video.h>
#include <video_fb.h>
#include <spl.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include <dm.h>
#include <usb.h>
#include <dwc3-uboot.h>
#include <linux/usb/dwc3.h>
#include "../common/padctrl.h"
#include "../common/bd_common.h"

DECLARE_GLOBAL_DATA_PTR;

static iomux_v3_cfg_t const init_pads[] = {
IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),

#define GP_BACKLIGHT_EN IMX_GPIO_NR(3, 24)
IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24 | MUX_PAD_CTRL(0x03),

#define GP_FASTBOOT_KEY IMX_GPIO_NR(1, 7)
IMX8MQ_PAD_GPIO1_IO07__GPIO1_IO7 | MUX_PAD_CTRL(WEAK_PULLUP),

#define GP_I2C2_PCA9546_RESET IMX_GPIO_NR(3, 18)
IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18 | MUX_PAD_CTRL(0x49),

#define GP_I2C2A_SN65DSI83_EN IMX_GPIO_NR(3, 15)
IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(0x6),

#define GP_EMMC_RESET IMX_GPIO_NR(2, 10)
IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(0x41),

#ifdef CONFIG_FEC_MXC
/* PHY - AR8035 */
IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, PAD_CTRL_ENET_MDIO),
IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, PAD_CTRL_ENET_MDC),
IOMUX_PAD_CTRL(ENET_TX_CTL__ENET_RGMII_TX_CTL, PAD_CTRL_ENET_TX),
IOMUX_PAD_CTRL(ENET_TD0__ENET_RGMII_TD0, PAD_CTRL_ENET_TX),
IOMUX_PAD_CTRL(ENET_TD1__ENET_RGMII_TD1, PAD_CTRL_ENET_TX),
IOMUX_PAD_CTRL(ENET_TD2__ENET_RGMII_TD2, PAD_CTRL_ENET_TX),
IOMUX_PAD_CTRL(ENET_TD3__ENET_RGMII_TD3, PAD_CTRL_ENET_TX),
IOMUX_PAD_CTRL(ENET_TXC__ENET_RGMII_TXC, PAD_CTRL_ENET_TX),
#endif
#define GP_RGMII_PHY_RESET IMX_GPIO_NR(1, 9)
IOMUX_PAD_CTRL(GPIO1_IO09__GPIO1_IO9, WEAK_PULLUP),
#define GPIRQ_ENET_PHY IMX_GPIO_NR(1, 11)
IOMUX_PAD_CTRL(GPIO1_IO11__GPIO1_IO11, WEAK_PULLUP),
};

int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;

imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
set_wdog_reset(wdog);

gpio_direction_output(GP_EMMC_RESET, 1);
gpio_direction_output(GP_I2C2_PCA9546_RESET, 0);
gpio_direction_output(GP_I2C2A_SN65DSI83_EN, 0);

return 0;
}

#ifdef CONFIG_BOARD_POSTCLK_INIT
int board_postclk_init(void)
{
/* TODO */
return 0;
}
#endif

#define MAX_LOW_SIZE (0x100000000ULL - CONFIG_SYS_SDRAM_BASE)
#define SDRAM_SIZE ((1ULL * CONFIG_DDR_MB) << 20)

#if SDRAM_SIZE > MAX_LOW_SIZE
#define MEM_SIZE MAX_LOW_SIZE
#else
#define MEM_SIZE SDRAM_SIZE
#endif

int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = SDRAM_SIZE;
return 0;
}

int dram_init(void)
{
/* rom_pointer[1] contains the size of TEE occupies */
gd->ram_size = MEM_SIZE - rom_pointer[1];
return 0;
}

#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
return 0;
}
#endif


#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)

#define USB_PHY_CTRL0 0xF0040
#define USB_PHY_CTRL0_REF_SSP_EN BIT(2)

#define USB_PHY_CTRL1 0xF0044
#define USB_PHY_CTRL1_RESET BIT(0)
#define USB_PHY_CTRL1_COMMONONN BIT(1)
#define USB_PHY_CTRL1_ATERESET BIT(3)
#define USB_PHY_CTRL1_VDATSRCENB0 BIT(19)
#define USB_PHY_CTRL1_VDATDETENB0 BIT(20)

#define USB_PHY_CTRL2 0xF0048
#define USB_PHY_CTRL2_TXENABLEN0 BIT(8)

static struct dwc3_device dwc3_device_data = {
.maximum_speed = USB_SPEED_SUPER,
.base = USB1_BASE_ADDR,
.dr_mode = USB_DR_MODE_PERIPHERAL,
.index = 0,
// .power_down_scale = 2,
};

int usb_gadget_handle_interrupts(void)
{
dwc3_uboot_handle_interrupt(0);
return 0;
}

static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
{
struct dwc3 *dwc3_reg = (struct dwc3 *)(dwc3->base + DWC3_REG_OFFSET);
u32 val;

val = readl(dwc3->base + USB_PHY_CTRL1);
val &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
USB_PHY_CTRL1_COMMONONN);
val |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
writel(val, dwc3->base + USB_PHY_CTRL1);

val = readl(dwc3->base + USB_PHY_CTRL0);
val |= USB_PHY_CTRL0_REF_SSP_EN;
writel(val, dwc3->base + USB_PHY_CTRL0);

val = readl(dwc3->base + USB_PHY_CTRL2);
val |= USB_PHY_CTRL2_TXENABLEN0;
writel(val, dwc3->base + USB_PHY_CTRL2);

val = readl(dwc3->base + USB_PHY_CTRL1);
val &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
writel(val, dwc3->base + USB_PHY_CTRL1);

val = readl(&dwc3_reg->g_ctl);
val &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
val |= DWC3_GCTL_PWRDNSCALE(2);

writel(val, &dwc3_reg->g_ctl);
}
#endif

#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
int board_usb_init(int index, enum usb_init_type init)
{
int ret = 0;
imx8m_usb_power(index, true);

if (index == 0 && init == USB_INIT_DEVICE) {
dwc3_nxp_usb_phy_init(&dwc3_device_data);
return dwc3_uboot_init(&dwc3_device_data);
} else if (index == 0 && init == USB_INIT_HOST) {
return ret;
}

if (index == 1) {
/* Release HUB reset */
#define GP_USB1_HUB_RESET IMX_GPIO_NR(1, 14)
imx_iomux_v3_setup_pad(IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 |
MUX_PAD_CTRL(WEAK_PULLUP));
gpio_request(GP_USB1_HUB_RESET, "usb1_rst");
gpio_direction_output(GP_USB1_HUB_RESET, 1);
}

return 0;
}

int board_usb_cleanup(int index, enum usb_init_type init)
{
int ret = 0;
if (index == 0 && init == USB_INIT_DEVICE)
dwc3_uboot_exit(index);

imx8m_usb_power(index, false);

return ret;
}
#endif

#ifdef CONFIG_CMD_FBPANEL

int board_detect_hdmi(struct display_info_t const *di)
{
return hdmi_hpd_status() ? 1 : 0;
}

static const struct display_info_t displays[] = {
/* hdmi */
VD_1920_1080M_60(HDMI, board_detect_hdmi, 0, 0x50),
VD_1280_720M_60(HDMI, NULL, 0, 0x50),
VD_1024_768M_60(HDMI, NULL, 0, 0x50),

VD_MIPI_M101NWWB(MIPI, NULL, fbp_bus_gp(3, GP_I2C2A_SN65DSI83_EN, 0, 0), 0x2c),
};

#define display_cnt ARRAY_SIZE(displays)
#else
#define displays NULL
#define display_cnt 0
#endif

int board_init(void)
{
gpio_request(GP_I2C2A_SN65DSI83_EN, "sn65dsi83_enable");
#ifdef CONFIG_DM_ETH
board_eth_init(gd->bd);
#endif
#ifdef CONFIG_CMD_FBPANEL
fbp_setup_display(displays, display_cnt);
#endif

return 0;
}

int board_mmc_get_env_dev(int devno)
{
return 0;
}

#if defined(CONFIG_CMD_FASTBOOT) || defined(CONFIG_CMD_DFU)
extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
static void addserial_env(const char* env_var)
{
unsigned char mac_address[8];
char serialbuf[20];

if (!env_get(env_var)) {
imx_get_mac_from_fuse(0, mac_address);
snprintf(serialbuf, sizeof(serialbuf), "%02x%02x%02x%02x%02x%02x",
mac_address[0], mac_address[1], mac_address[2],
mac_address[3], mac_address[4], mac_address[5]);
env_set(env_var, serialbuf);
}
}
#endif

#ifdef CONFIG_CMD_BMODE
const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */
{"emmc0", MAKE_CFGVAL(0x22, 0x20, 0x00, 0x10)},
{NULL, 0},
};
#endif

static int fastboot_key_pressed(void)
{
gpio_request(GP_FASTBOOT_KEY, "fastboot_key");
gpio_direction_input(GP_FASTBOOT_KEY);
return !gpio_get_value(GP_FASTBOOT_KEY);
}

void init_usb_clk(int usbno);

static void set_env_vars(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
if (!env_get("board"))
env_set("board", "son");
env_set("soc", "imx8mq");
env_set("imx_cpu", get_imx_type((get_cpu_rev() & 0xFF000) >> 12));
env_set("uboot_defconfig", CONFIG_DEFCONFIG);
#endif
}

void board_set_default_env(void)
{
set_env_vars();
#ifdef CONFIG_CMD_FBPANEL
fbp_setup_env_cmds();
#endif
board_eth_addresses();
}

int board_late_init(void)
{
set_env_vars();
#if defined(CONFIG_USB_FUNCTION_FASTBOOT) || defined(CONFIG_CMD_DFU)
addserial_env("serial#");
if (fastboot_key_pressed()) {
printf("Starting fastboot...\n");
env_set("preboot", "fastboot 0");
}
#endif
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
init_usb_clk(0);
init_usb_clk(1);
return 0;
}

+ 242
- 0
board/boundary/son/spl.c View File

@@ -0,0 +1,242 @@
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/

#include <common.h>
#include <spl.h>
#include <asm/io.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <asm/arch/ddr.h>
#ifdef CONFIG_IMX8M_LPDDR4
#include <asm/arch/imx8m_ddr.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

void spl_dram_init(void)
{
/* ddr init */
ddr_init(&dram_timing);
}

#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
.gp = IMX_GPIO_NR(5, 14),
},
.sda = {
.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
.gp = IMX_GPIO_NR(5, 15),
},
};

#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
PAD_CTL_FSEL2)
#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)

static iomux_v3_cfg_t const init_pads[] = {
#define GP_I2C1_PCA9546_RESET IMX_GPIO_NR(1, 8)
IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(0x49),

IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
#define GP_EMMC_RESET IMX_GPIO_NR(2, 10)
IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),

IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
#define GP_USDHC2_CD IMX_GPIO_NR(2, 12)
IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
#define GP_USDHC2_VSEL IMX_GPIO_NR(3, 20)
IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20 | MUX_PAD_CTRL(0x16),
};

static struct fsl_esdhc_cfg usdhc_cfg[] = {
{.esdhc_base = USDHC1_BASE_ADDR, .bus_width = 8,
.gp_reset = GP_EMMC_RESET},
{.esdhc_base = USDHC2_BASE_ADDR, .bus_width = 4,},
};

int board_mmc_init(bd_t *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-Boot device node) (Physical Port)
* mmc0 USDHC1
* mmc1 USDHC2
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
gpio_request(GP_EMMC_RESET, "usdhc1_reset");
gpio_direction_output(GP_EMMC_RESET, 0);
udelay(500);
gpio_direction_output(GP_EMMC_RESET, 1);
break;
case 1:
usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
gpio_request(GP_USDHC2_CD, "usdhc2 cd");
gpio_direction_input(GP_USDHC2_CD);
break;
default:
printf("Warning: you configured more USDHC controllers"
"(%d) than supported by the board\n", i + 1);
return -EINVAL;
}

ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}

return 0;
}

int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;

switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
return 1;
case USDHC2_BASE_ADDR:
ret = gpio_get_value(GP_USDHC2_CD);
return ret ? 0 : 1;
}

return 0;
}

int power_init_boundary(void)
{
int ret;
unsigned char buf[4];

i2c_set_bus_num(0);
#define PF8100 0x08
#define SW2_VOLT 0x59
#define SW3_CONFIG2 0x5e
#define SW3_VOLT 0x61
#define SW4_CONFIG2 0x66
#define SW4_VOLT 0x69
#define SW5_VOLT 0x71

buf[0] = 0x50; /* (.90-.4)*160=.50*160=80=0x50 80/160+.4=.90 gpu/dram/arm */
ret = i2c_write(PF8100, SW2_VOLT, 1, buf, 1);
if (ret)
return ret;
ret = i2c_write(PF8100, SW4_VOLT, 1, buf, 1);
if (ret)
return ret;
ret = i2c_write(PF8100, SW3_VOLT, 1, buf, 1);
if (ret)
return ret;
/*
* Make sw3 a 180 phase shift from sw4,
* in case pmic not programmed for dual mode
*/
ret = i2c_read(PF8100, SW4_CONFIG2, 1, buf, 1);
if (!ret) {
buf[0] ^= 4; /* 180 degree phase */
ret = i2c_write(PF8100, SW3_CONFIG2, 1, buf, 1);
}

buf[0] = 0x40; /* (.80-.4)*160=.40*160=64=0x40 64/160+.4=.80 vpu */
ret = i2c_write(PF8100, SW5_VOLT, 1, buf, 1);

gpio_request(GP_USDHC2_VSEL, "usdhc2_vsel");
gpio_direction_output(GP_USDHC2_VSEL, 0);
return ret;
}

void spl_board_init(void)
{
#ifndef CONFIG_SPL_USB_SDP_SUPPORT
/* Serial download mode */
if (is_usb_boot()) {
puts("Back to ROM, SDP\n");
restore_boot_params();
}
#endif
puts("Normal Boot\n");
}

#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);

return 0;
}
#endif

void board_init_f(ulong dummy)
{
int ret;

/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));

arch_cpu_init();

board_early_init_f();
init_uart_clk(0);
timer_init();

preloader_console_init();

/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);

ret = spl_init();
if (ret) {
printf("spl_init() failed: %d\n", ret);
hang();
}

enable_tzc380();
imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));

/* Adjust pmic voltage to 1.0V for 800M */
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);

power_init_boundary();

/* DDR initialization */
spl_dram_init();

board_init_r(NULL, 0);
}

+ 106
- 0
configs/son_2g_defconfig View File

@@ -0,0 +1,106 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SON=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x30860000
CONFIG_DEBUG_UART_CLOCK=25000000
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-son"
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg,DDR_MB=2048,DEFCONFIG=\"son_2g\""
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET_SUPPORT=y
CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_IMX8M_LPDDR4=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x40480000
CONFIG_FASTBOOT_BUF_SIZE=0x20000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
CONFIG_DM_MMC=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_NETDEVICES=y
CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DEBUG_UART_MXC=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Boundary"
CONFIG_USB_GADGET_VENDOR_NUM=0x3016
CONFIG_USB_GADGET_PRODUCT_NUM=0x0001
CONFIG_USB_GADGET_SPL_SPD_PRODUCT_NUM=0x1001
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
CONFIG_USBNET_DEVADDR="00:19:b8:00:00:02"
CONFIG_USBNET_HOST_ADDR="00:19:b8:00:00:01"
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_VIDEO=y
CONFIG_VIDEO_IMXDCSS=y
CONFIG_VIDEO_IMX8_HDMI=y

+ 257
- 0
include/configs/son.h View File

@@ -0,0 +1,257 @@
/*
* Copyright 2018 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*/

#ifndef __SON_H
#define __SON_H

#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>

#ifdef CONFIG_SECURE_BOOT
#define CONFIG_CSF_SIZE 0x2000 /* 8K region */
#endif

#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1

#ifdef CONFIG_SPL_BUILD

/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x00187FF0
#define CONFIG_SPL_BSS_START_ADDR 0x00180000
#define CONFIG_SPL_BSS_MAX_SIZE 0x00002000 /* 8 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 /* 512 KB */
#define CONFIG_MALLOC_F_ADDR 0x00182000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF

#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */

#undef CONFIG_BLK
#undef CONFIG_DM_MMC
#undef CONFIG_DM_PMIC
#undef CONFIG_DM_PMIC_PFUZE100

#define CONFIG_SYS_I2C

#endif

#define CONFIG_PREBOOT

#define CONFIG_REMAKE_ELF

#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_POSTCLK_INIT
#define CONFIG_BOARD_LATE_INIT

/* Flat Device Tree Definitions */
#define CONFIG_OF_BOARD_SETUP

#undef CONFIG_CMD_EXPORTENV
#undef CONFIG_CMD_IMPORTENV
#undef CONFIG_CMD_IMLS

/* #define CONFIG_CMD_BMODE */
#undef CONFIG_CMD_CRC32
#undef CONFIG_BOOTM_NETBSD

/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_MII
#define CONFIG_ETHPRIME "FEC"

#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 4
#define FEC_QUIRK_ENET_MAC
#define GP_RGMII_PHY_RESET IMX_GPIO_NR(1, 9)

#define CONFIG_PHY_GIGE
#define IMX_FEC_BASE 0x30BE0000

#endif

/* Link Definitions */
#define CONFIG_LOADADDR 0x40480000
#define CONFIG_SYS_TEXT_BASE 0x40200000

#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR

#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
#define CONFIG_SYS_MMC_ENV_PART 1 /* mmcblk0boot0 */

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024)

#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000

#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x40000000u)

#define CONFIG_BAUDRATE 115200

#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR

/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 2048
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)

#define CONFIG_IMX_BOOTAUX

#define CONFIG_FSL_USDHC

#define CONFIG_SYS_FSL_USDHC_NUM 1
#define CONFIG_SYS_FSL_ESDHC_ADDR 0

#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_SUPPORT_EMMC_RPMB
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1

#define CONFIG_MXC_GPIO

#define CONFIG_MXC_OCOTP
#define CONFIG_CMD_FUSE

/* I2C Configs */
#define CONFIG_SYS_I2C_SPEED 100000

/* USB configs */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_USBD_HS

#define CONFIG_USB_GADGET_MASS_STORAGE

#endif

#define CONFIG_USB_GADGET_VBUS_DRAW 2

#define CONFIG_USB_MAX_CONTROLLER_COUNT 2

#define CONFIG_OF_SYSTEM_SETUP

/* Framebuffer */
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#endif

#ifndef BD_CONSOLE
#if CONFIG_MXC_UART_BASE == UART2_BASE_ADDR
#define BD_CONSOLE "ttymxc1"
#elif CONFIG_MXC_UART_BASE == UART1_BASE_ADDR
#define BD_CONSOLE "ttymxc0"
#endif
#endif

#ifdef CONFIG_CMD_MMC
#if (CONFIG_SYS_FSL_USDHC_NUM == 1)
#define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0)
#elif (CONFIG_SYS_FSL_USDHC_NUM == 2)
#define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
#else
#define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) func(MMC, mmc, 2)
#endif
#else
#define DISTRO_BOOT_DEV_MMC(func)
#endif

#ifdef CONFIG_USB_STORAGE
#define DISTRO_BOOT_DEV_USB(func) func(USB, usb, 0)
#else
#define DISTRO_BOOT_DEV_USB(func)
#endif

#ifndef BOOT_TARGET_DEVICES
#define BOOT_TARGET_DEVICES(func) \
DISTRO_BOOT_DEV_USB(func) \
DISTRO_BOOT_DEV_MMC(func)
#endif

#include <config_distro_bootcmd.h>
#define CONFIG_CMD_FBPANEL

#define BD_RAM_BASE 0x80000000
#define BD_RAM_SCRIPT "40020000"
#define BD_RAM_KERNEL "40800000"
#define BD_RAM_RAMDISK "42800000"
#define BD_RAM_FDT "43000000"

/* M4 specific */
#define SYS_AUXCORE_BOOTDATA_DDR 0x80000000
#define SYS_AUXCORE_BOOTDATA_TCM 0x007E0000

#define CONFIG_EXTRA_ENV_SETTINGS \
"console=" BD_CONSOLE "\0" \
"env_dev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"env_part=" __stringify(CONFIG_SYS_MMC_ENV_PART) "\0" \
"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
"fdt_addr=0x43000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
"m4boot=load ${devtype} ${devnum}:1 ${m4loadaddr} ${m4image}; " \
"dcache flush; bootaux ${m4loadaddr}\0" \
"m4image=m4_fw.bin\0" \
"m4loadaddr="__stringify(SYS_AUXCORE_BOOTDATA_TCM)"\0" \
"netargs=setenv bootargs console=${console},115200 root=/dev/nfs rw " \
"ip=dhcp nfsroot=${tftpserverip}:${nfsroot},v3,tcp\0" \
"netboot=run netargs; " \
"if test -z \"${fdt_file}\" -a -n \"${soc}\"; then " \
"setenv fdt_file ${soc}-${board}${boardver}.dtb; " \
"fi; " \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"${get_cmd} ${loadaddr} ${tftpserverip}:Image; " \
"if ${get_cmd} ${fdt_addr} ${tftpserverip}:${fdt_file}; then " \
"booti ${loadaddr} - ${fdt_addr}; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi;\0" \
"net_upgradeu=dhcp " BD_RAM_SCRIPT " net_upgradeu.scr && source " BD_RAM_SCRIPT "\0" \
"otg_upgradeu=run usbnetwork; tftp " BD_RAM_SCRIPT " net_upgradeu.scr && source " BD_RAM_SCRIPT "\0" \
"upgradeu=setenv boot_scripts upgrade.scr; boot;" \
"echo Upgrade failed!; setenv boot_scripts boot.scr\0" \
"usbnet_devaddr=00:19:b8:00:00:02\0" \
"usbnet_hostaddr=00:19:b8:00:00:01\0" \
"usbnetwork=setenv ethact usb_ether; " \
"setenv ipaddr 10.0.0.2; " \
"setenv netmask 255.255.255.0; " \
"setenv serverip 10.0.0.1;\0" \
BOOTENV

/*
* PCI express
*/
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_PCIE_IMX
#endif
#endif

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