Browse Source

powerpc, 8xx: remove support for 8xx

There was for long time no activity in the 8xx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in 8xx,
so remove it (with a heavy heart, knowing that I remove
here the root of U-Boot).

Signed-off-by: Heiko Schocher <hs@denx.de>
tags/2020-06-01
Heiko Schocher 4 years ago
committed by Tom Rini
parent
commit
5b8e76c35e
100 changed files with 41 additions and 13887 deletions
  1. +0
    -2
      .travis.yml
  2. +8
    -80
      README
  3. +1
    -1
      api/api_platform-powerpc.c
  4. +0
    -4
      arch/powerpc/Kconfig
  5. +0
    -51
      arch/powerpc/cpu/mpc8xx/Kconfig
  6. +0
    -25
      arch/powerpc/cpu/mpc8xx/Makefile
  7. +0
    -314
      arch/powerpc/cpu/mpc8xx/bedbug_860.c
  8. +0
    -8
      arch/powerpc/cpu/mpc8xx/config.mk
  9. +0
    -580
      arch/powerpc/cpu/mpc8xx/cpu.c
  10. +0
    -218
      arch/powerpc/cpu/mpc8xx/cpu_init.c
  11. +0
    -27
      arch/powerpc/cpu/mpc8xx/fdt.c
  12. +0
    -933
      arch/powerpc/cpu/mpc8xx/fec.c
  13. +0
    -12
      arch/powerpc/cpu/mpc8xx/fec.h
  14. +0
    -278
      arch/powerpc/cpu/mpc8xx/interrupts.c
  15. +0
    -54
      arch/powerpc/cpu/mpc8xx/kgdb.S
  16. +0
    -119
      arch/powerpc/cpu/mpc8xx/plprcr_write.S
  17. +0
    -472
      arch/powerpc/cpu/mpc8xx/scc.c
  18. +0
    -676
      arch/powerpc/cpu/mpc8xx/serial.c
  19. +0
    -403
      arch/powerpc/cpu/mpc8xx/speed.c
  20. +0
    -533
      arch/powerpc/cpu/mpc8xx/spi.c
  21. +0
    -650
      arch/powerpc/cpu/mpc8xx/start.S
  22. +0
    -216
      arch/powerpc/cpu/mpc8xx/traps.c
  23. +0
    -194
      arch/powerpc/cpu/mpc8xx/upatch.c
  24. +0
    -1123
      arch/powerpc/cpu/mpc8xx/video.c
  25. +0
    -1
      arch/powerpc/cpu/ppc4xx/4xx_uart.c
  26. +0
    -1
      arch/powerpc/cpu/ppc4xx/interrupts.c
  27. +0
    -1
      arch/powerpc/cpu/ppc4xx/miiphy.c
  28. +0
    -1
      arch/powerpc/cpu/ppc4xx/uic.c
  29. +0
    -1
      arch/powerpc/cpu/ppc4xx/xilinx_irq.c
  30. +0
    -515
      arch/powerpc/include/asm/8xx_immap.h
  31. +1
    -40
      arch/powerpc/include/asm/cache.h
  32. +0
    -3
      arch/powerpc/include/asm/global_data.h
  33. +0
    -379
      arch/powerpc/include/asm/iopin_8xx.h
  34. +2
    -36
      arch/powerpc/include/asm/ppc.h
  35. +1
    -4
      arch/powerpc/include/asm/processor.h
  36. +1
    -3
      arch/powerpc/include/asm/status_led.h
  37. +0
    -1
      arch/powerpc/lib/Makefile
  38. +0
    -184
      arch/powerpc/lib/ide.c
  39. +0
    -15
      arch/powerpc/lib/ide.h
  40. +16
    -90
      arch/powerpc/lib/immap.c
  41. +2
    -2
      arch/powerpc/lib/time.c
  42. +0
    -155
      board/tqc/tqm8xx/Kconfig
  43. +0
    -31
      board/tqc/tqm8xx/MAINTAINERS
  44. +0
    -8
      board/tqc/tqm8xx/Makefile
  45. +0
    -89
      board/tqc/tqm8xx/load_sernum_ethaddr.c
  46. +0
    -677
      board/tqc/tqm8xx/tqm8xx.c
  47. +0
    -94
      board/tqc/tqm8xx/u-boot.lds
  48. +1
    -1
      cmd/bdinfo.c
  49. +0
    -4
      cmd/bedbug.c
  50. +2
    -7
      cmd/ide.c
  51. +0
    -4
      cmd/pcmcia.c
  52. +2
    -57
      cmd/reginfo.c
  53. +0
    -3
      cmd/source.c
  54. +2
    -2
      common/board_f.c
  55. +0
    -14
      common/board_r.c
  56. +1
    -13
      common/bootm_os.c
  57. +0
    -4
      common/lcd.c
  58. +0
    -24
      configs/TQM823L_LCD_defconfig
  59. +0
    -27
      configs/TQM823L_defconfig
  60. +0
    -27
      configs/TQM823M_defconfig
  61. +0
    -27
      configs/TQM850L_defconfig
  62. +0
    -27
      configs/TQM850M_defconfig
  63. +0
    -27
      configs/TQM855L_defconfig
  64. +0
    -28
      configs/TQM855M_defconfig
  65. +0
    -27
      configs/TQM860L_defconfig
  66. +0
    -27
      configs/TQM860M_defconfig
  67. +0
    -27
      configs/TQM862L_defconfig
  68. +0
    -27
      configs/TQM862M_defconfig
  69. +0
    -27
      configs/TQM866M_defconfig
  70. +0
    -30
      configs/TQM885D_defconfig
  71. +0
    -24
      configs/TTTech_defconfig
  72. +0
    -24
      configs/wtk_defconfig
  73. +0
    -1
      doc/README.LED
  74. +0
    -24
      doc/README.MPC866
  75. +0
    -6
      doc/README.fsl-clk
  76. +0
    -1
      doc/README.scrapyard
  77. +0
    -11
      drivers/block/ide.c
  78. +0
    -1
      drivers/block/sil680.c
  79. +0
    -5
      drivers/bootcount/bootcount.c
  80. +0
    -11
      drivers/i2c/i2c_core.c
  81. +0
    -3
      drivers/i2c/soft_i2c.c
  82. +0
    -1
      drivers/net/4xx_enet.c
  83. +0
    -2
      drivers/pcmcia/Makefile
  84. +0
    -258
      drivers/pcmcia/mpc8xx_pcmcia.c
  85. +0
    -254
      drivers/pcmcia/tqm8xx_pcmcia.c
  86. +0
    -1
      drivers/rtc/Makefile
  87. +0
    -60
      drivers/rtc/mpc8xx.c
  88. +0
    -1
      drivers/usb/gadget/Makefile
  89. +0
    -1386
      drivers/usb/gadget/mpc8xx_udc.c
  90. +0
    -1
      drivers/video/Makefile
  91. +0
    -400
      drivers/video/mpc8xx_lcd.c
  92. +0
    -2
      examples/standalone/Makefile
  93. +0
    -284
      examples/standalone/test_burst.c
  94. +0
    -22
      examples/standalone/test_burst.h
  95. +0
    -154
      examples/standalone/test_burst_lib.S
  96. +0
    -333
      examples/standalone/timer.c
  97. +1
    -1
      include/asm-generic/u-boot.h
  98. +0
    -849
      include/commproc.h
  99. +0
    -1
      include/configs/CPCI4052.h
  100. +0
    -1
      include/configs/MIP405.h

+ 0
- 2
.travis.yml View File

@@ -218,8 +218,6 @@ matrix:
- env:
- BUILDMAN="mpc86xx"
- env:
- BUILDMAN="mpc8xx"
- env:
- BUILDMAN="siemens"
- env:
- BUILDMAN="tegra"


+ 8
- 80
README View File

@@ -328,34 +328,6 @@ The following options need to be configured:
multiple fs option at one time
for marvell soc family

- 8xx CPU Options: (if using an MPC8xx CPU)
CONFIG_8xx_GCLK_FREQ - deprecated: CPU clock if
get_gclk_freq() cannot work
e.g. if there is no 32KHz
reference PIT/RTC clock
CONFIG_8xx_OSCLK - PLL input clock (either EXTCLK
or XTAL/EXTAL)

- 859/866/885 CPU options: (if using a MPC859 or MPC866 or MPC885 CPU):
CONFIG_SYS_8xx_CPUCLK_MIN
CONFIG_SYS_8xx_CPUCLK_MAX
CONFIG_8xx_CPUCLK_DEFAULT
See doc/README.MPC866

CONFIG_SYS_MEASURE_CPUCLK

Define this to measure the actual CPU clock instead
of relying on the correctness of the configured
values. Mostly useful for board bringup to make sure
the PLL is locked at the intended frequency. Note
that this requires a (stable) reference clock (32 kHz
RTC clock or CONFIG_SYS_8XX_XIN)

CONFIG_SYS_DELAYED_ICACHE

Define this option if you want to enable the
ICache only when Code runs from RAM.

- 85xx CPU Options:
CONFIG_SYS_PPC64

@@ -723,26 +695,15 @@ The following options need to be configured:
Define this variable to enable hw flow control in serial driver.
Current user of this option is drivers/serial/nsl16550.c driver

- Console Interface:
Depending on board, define exactly one serial port
(like CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2,
CONFIG_8xx_CONS_SCC1, ...), or switch off the serial
console by defining CONFIG_8xx_CONS_NONE

Note: if CONFIG_8xx_CONS_NONE is defined, the serial
port routines must be defined elsewhere
(i.e. serial_init(), serial_getc(), ...)

- Console Baudrate:
CONFIG_BAUDRATE - in bps
Select one of the baudrates listed in
CONFIG_SYS_BAUDRATE_TABLE, see below.
CONFIG_SYS_BRGCLK_PRESCALE, baudrate prescale

- Console Rx buffer length
With CONFIG_SYS_SMC_RXBUFLEN it is possible to define
the maximum receive buffer length for the SMC.
This option is actual only for 82xx and 8xx possible.
This option is actual only for 82xx possible.
If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE
must be defined, to setup the maximum idle timeout for
the SMC.
@@ -912,7 +873,7 @@ The following options need to be configured:
Note: Don't enable the "icache" and "dcache" commands
(configuration option CONFIG_CMD_CACHE) unless you know
what you (and your U-Boot users) are doing. Data
cache cannot be enabled on systems like the 8xx or
cache cannot be enabled on systems like the
8260 (where accesses to the IMMR region must be
uncached), and it cannot be disabled on all other
systems where we (mis-) use the data cache to hold an
@@ -976,7 +937,7 @@ The following options need to be configured:
CONFIG_WATCHDOG
If this variable is defined, it enables watchdog
support for the SoC. There must be support in the SoC
specific code for a watchdog. For the 8xx and 8260
specific code for a watchdog. For the 8260
CPUs, the SIU Watchdog feature is enabled in the SYPCR
register. When supported for a specific SoC is
available, then no further board specific code should
@@ -1004,7 +965,6 @@ The following options need to be configured:
has to be selected, too. Define exactly one of the
following options:

CONFIG_RTC_MPC8xx - use internal RTC of MPC8xx
CONFIG_RTC_PCF8563 - use Philips PCF8563 RTC
CONFIG_RTC_MC13XXX - use MC13783 or MC13892 RTC
CONFIG_RTC_MC146818 - use MC146818 RTC
@@ -1345,11 +1305,6 @@ The following options need to be configured:
Define this if you want stdin, stdout &/or stderr to
be set to usbtty.

mpc8xx:
CONFIG_SYS_USB_EXTC_CLK 0xBLAH
Derive USB clock from external clock "blah"
- CONFIG_SYS_USB_EXTC_CLK 0x02

If you have a USB-IF assigned VendorID then you may wish to
define your own vendor specific values either in BoardName.h
or directly in usbd_vendor_info.h. If you don't define
@@ -1953,7 +1908,7 @@ The following options need to be configured:

Defining CONFIG_CAN_DRIVER enables CAN driver support
on those systems that support this (optional)
feature, like the TQM8xxL modules.
feature.

- I2C Support: CONFIG_SYS_I2C

@@ -2445,7 +2400,7 @@ The following options need to be configured:
following board configurations are known to be
"pRAM-clean":

IVMS8, IVML24, SPD8xx, TQM8xxL,
IVMS8, IVML24, SPD8xx,
HERMES, IP860, RPXlite, LWMON,
FLAGADM, TQM8260

@@ -4048,7 +4003,7 @@ Low Level (hardware related) configuration options:

- CONFIG_SYS_IMMR: Physical address of the Internal Memory.
DO NOT CHANGE unless you know exactly what you're
doing! (11-4) [MPC8xx/82xx systems only]
doing! (11-4) [82xx systems only]

- CONFIG_SYS_INIT_RAM_ADDR:

@@ -4061,7 +4016,7 @@ Low Level (hardware related) configuration options:
sequences.

U-Boot uses the following memory types:
- MPC8xx and MPC8260: IMMR (internal memory of the CPU)
- MPC8260: IMMR (internal memory of the CPU)
- MPC824X: data cache
- PPC4xx: data cache

@@ -4119,19 +4074,7 @@ Low Level (hardware related) configuration options:
Machine Mode Register and Memory Periodic Timer
Prescaler definitions (SDRAM timing)

- CONFIG_SYS_I2C_UCODE_PATCH, CONFIG_SYS_I2C_DPMEM_OFFSET [0x1FC0]:
enable I2C microcode relocation patch (MPC8xx);
define relocation offset in DPRAM [DSP2]

- CONFIG_SYS_SMC_UCODE_PATCH, CONFIG_SYS_SMC_DPMEM_OFFSET [0x1FC0]:
enable SMC microcode relocation patch (MPC8xx);
define relocation offset in DPRAM [SMC1]

- CONFIG_SYS_SPI_UCODE_PATCH, CONFIG_SYS_SPI_DPMEM_OFFSET [0x1FC0]:
enable SPI microcode relocation patch (MPC8xx);
define relocation offset in DPRAM [SCC4]

- CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only)
- CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8260 only)
Offset of the bootmode word in DPRAM used by post
(Power On Self Tests). This definition overrides
#define'd default value in commproc.h resp.
@@ -4225,21 +4168,6 @@ Low Level (hardware related) configuration options:
Only for 83xx systems. If specified, then DDR should
be configured using CS0 and CS1 instead of CS2 and CS3.

- CONFIG_ETHER_ON_FEC[12]
Define to enable FEC[12] on a 8xx series processor.

- CONFIG_FEC[12]_PHY
Define to the hardcoded PHY address which corresponds
to the given FEC; i. e.
#define CONFIG_FEC1_PHY 4
means that the PHY with address 4 is connected to FEC1

When set to -1, means to probe for first available.

- CONFIG_FEC[12]_PHY_NORXERR
The PHY does not have a RXERR line (RMII only).
(so program the FEC to ignore it).

- CONFIG_RMII
Enable RMII mode for all FECs.
Note that this is a global option, we can't


+ 1
- 1
api/api_platform-powerpc.c View File

@@ -30,7 +30,7 @@ int platform_sys_info(struct sys_info *si)
si->clk_bus = gd->bus_clk;
si->clk_cpu = gd->cpu_clk;

#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || \
#if defined(CONFIG_5xx) || defined(CONFIG_MPC8260) || \
defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
#define bi_bar bi_immr_base
#elif defined(CONFIG_MPC5xxx)


+ 0
- 4
arch/powerpc/Kconfig View File

@@ -41,9 +41,6 @@ config MPC86xx
select SYS_FSL_DDR
select SYS_FSL_DDR_BE

config 8xx
bool "MPC8xx"

config 4xx
bool "PPC4xx"
select CREATE_ARCH_SYMLINK
@@ -60,7 +57,6 @@ source "arch/powerpc/cpu/mpc8260/Kconfig"
source "arch/powerpc/cpu/mpc83xx/Kconfig"
source "arch/powerpc/cpu/mpc85xx/Kconfig"
source "arch/powerpc/cpu/mpc86xx/Kconfig"
source "arch/powerpc/cpu/mpc8xx/Kconfig"
source "arch/powerpc/cpu/ppc4xx/Kconfig"

endmenu

+ 0
- 51
arch/powerpc/cpu/mpc8xx/Kconfig View File

@@ -1,51 +0,0 @@
menu "mpc8xx CPU"
depends on 8xx

config SYS_CPU
default "mpc8xx"

choice
prompt "Target select"
optional

config TARGET_TQM823L
bool "Support TQM823L"

config TARGET_TQM823M
bool "Support TQM823M"

config TARGET_TQM850L
bool "Support TQM850L"

config TARGET_TQM850M
bool "Support TQM850M"

config TARGET_TQM855L
bool "Support TQM855L"

config TARGET_TQM855M
bool "Support TQM855M"

config TARGET_TQM860L
bool "Support TQM860L"

config TARGET_TQM860M
bool "Support TQM860M"

config TARGET_TQM862L
bool "Support TQM862L"

config TARGET_TQM862M
bool "Support TQM862M"

config TARGET_TQM866M
bool "Support TQM866M"

config TARGET_TQM885D
bool "Support TQM885D"

endchoice

source "board/tqc/tqm8xx/Kconfig"

endmenu

+ 0
- 25
arch/powerpc/cpu/mpc8xx/Makefile View File

@@ -1,25 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#

# ccflags-y += -DET_DEBUG

extra-y += start.o
extra-y += traps.o
obj-y += bedbug_860.o
obj-y += cpu.o
obj-y += cpu_init.o
obj-y += fec.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-y += interrupts.o
obj-y += scc.o
obj-y += serial.o
obj-y += speed.o
obj-y += spi.o
obj-y += upatch.o
obj-y += video.o
obj-y += kgdb.o
obj-y += plprcr_write.o

+ 0
- 314
arch/powerpc/cpu/mpc8xx/bedbug_860.c View File

@@ -1,314 +0,0 @@
/*
* Bedbug Functions specific to the MPC860 chip
*/

#include <common.h>
#include <command.h>
#include <linux/ctype.h>
#include <bedbug/bedbug.h>
#include <bedbug/regs.h>
#include <bedbug/ppc.h>
#include <bedbug/type.h>

#if defined(CONFIG_CMD_BEDBUG) && defined(CONFIG_8xx)

#define MAX_BREAK_POINTS 2

extern CPU_DEBUG_CTX bug_ctx;

void bedbug860_init __P((void));
void bedbug860_do_break __P((cmd_tbl_t*,int,int,char*const[]));
void bedbug860_break_isr __P((struct pt_regs*));
int bedbug860_find_empty __P((void));
int bedbug860_set __P((int,unsigned long));
int bedbug860_clear __P((int));

/* ======================================================================
* Initialize the global bug_ctx structure for the MPC860. Clear all
* of the breakpoints.
* ====================================================================== */

void bedbug860_init( void )
{
int i;
/* -------------------------------------------------- */

bug_ctx.hw_debug_enabled = 0;
bug_ctx.stopped = 0;
bug_ctx.current_bp = 0;
bug_ctx.regs = NULL;

bug_ctx.do_break = bedbug860_do_break;
bug_ctx.break_isr = bedbug860_break_isr;
bug_ctx.find_empty = bedbug860_find_empty;
bug_ctx.set = bedbug860_set;
bug_ctx.clear = bedbug860_clear;

for( i = 1; i <= MAX_BREAK_POINTS; ++i )
(*bug_ctx.clear)( i );

puts ("BEDBUG:ready\n");
return;
} /* bedbug_init_breakpoints */


/* ======================================================================
* Set/clear/show one of the hardware breakpoints for the 860. The "off"
* string will disable a specific breakpoint. The "show" string will
* display the current breakpoints. Otherwise an address will set a
* breakpoint at that address. Setting a breakpoint uses the CPU-specific
* set routine which will assign a breakpoint number.
* ====================================================================== */

void bedbug860_do_break (cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
long addr = 0; /* Address to break at */
int which_bp; /* Breakpoint number */
/* -------------------------------------------------- */

if (argc < 2) {
cmd_usage(cmdtp);
return;
}

/* Turn off a breakpoint */

if( strcmp( argv[ 1 ], "off" ) == 0 )
{
if( bug_ctx.hw_debug_enabled == 0 )
{
printf( "No breakpoints enabled\n" );
return;
}

which_bp = simple_strtoul( argv[ 2 ], NULL, 10 );

if( bug_ctx.clear )
(*bug_ctx.clear)( which_bp );

printf( "Breakpoint %d removed\n", which_bp );
return;
}

/* Show a list of breakpoints */

if( strcmp( argv[ 1 ], "show" ) == 0 )
{
for( which_bp = 1; which_bp <= MAX_BREAK_POINTS; ++which_bp )
{

switch( which_bp )
{
case 1: addr = GET_CMPA(); break;
case 2: addr = GET_CMPB(); break;
case 3: addr = GET_CMPC(); break;
case 4: addr = GET_CMPD(); break;
}

printf( "Breakpoint [%d]: ", which_bp );
if( addr == 0 )
printf( "NOT SET\n" );
else
disppc( (unsigned char *)addr, 0, 1, bedbug_puts, F_RADHEX );
}
return;
}

/* Set a breakpoint at the address */

if( !isdigit( argv[ 1 ][ 0 ])) {
cmd_usage(cmdtp);
return;
}

addr = simple_strtoul( argv[ 1 ], NULL, 16 ) & 0xfffffffc;

if(( bug_ctx.set ) && ( which_bp = (*bug_ctx.set)( 0, addr )) > 0 )
{
printf( "Breakpoint [%d]: ", which_bp );
disppc( (unsigned char *)addr, 0, 1, bedbug_puts, F_RADHEX );
}

return;
} /* bedbug860_do_break */


/* ======================================================================
* Handle a breakpoint. First determine which breakpoint was hit by
* looking at the DeBug Status Register (DBSR), clear the breakpoint
* and enter a mini main loop. Stay in the loop until the stopped flag
* in the debug context is cleared.
* ====================================================================== */

void bedbug860_break_isr( struct pt_regs *regs )
{
unsigned long addr; /* Address stopped at */
unsigned long cause; /* Address stopped at */
/* -------------------------------------------------- */

cause = GET_ICR();

if( !(cause & 0x00000004)) {
printf( "Not an instruction breakpoint (ICR 0x%08lx)\n", cause );
return;
}

addr = regs->nip;

if( addr == GET_CMPA() )
{
bug_ctx.current_bp = 1;
}
else if( addr == GET_CMPB() )
{
bug_ctx.current_bp = 2;
}
else if( addr == GET_CMPC() )
{
bug_ctx.current_bp = 3;
}
else if( addr == GET_CMPD() )
{
bug_ctx.current_bp = 4;
}

bedbug_main_loop( addr, regs );
return;
} /* bedbug860_break_isr */


/* ======================================================================
* Look through all of the hardware breakpoints available to see if one
* is unused.
* ====================================================================== */

int bedbug860_find_empty( void )
{
/* -------------------------------------------------- */

if( GET_CMPA() == 0 )
return 1;

if( GET_CMPB() == 0 )
return 2;

if( GET_CMPC() == 0 )
return 3;

if( GET_CMPD() == 0 )
return 4;

return 0;
} /* bedbug860_find_empty */


/* ======================================================================
* Set a breakpoint. If 'which_bp' is zero then find an unused breakpoint
* number, otherwise reassign the given breakpoint. If hardware debugging
* is not enabled, then turn it on via the MSR and DBCR0. Set the break
* address in the appropriate IACx register and enable proper address
* beakpoint in DBCR0.
* ====================================================================== */

int bedbug860_set( int which_bp, unsigned long addr )
{
/* -------------------------------------------------- */

/* Only look if which_bp == 0, else use which_bp */
if(( bug_ctx.find_empty ) && ( !which_bp ) &&
( which_bp = (*bug_ctx.find_empty)()) == 0 )
{
printf( "All breakpoints in use\n" );
return 0;
}

if( which_bp < 1 || which_bp > MAX_BREAK_POINTS )
{
printf( "Invalid break point # %d\n", which_bp );
return 0;
}

if( ! bug_ctx.hw_debug_enabled )
{
bug_ctx.hw_debug_enabled = 1;
SET_DER( GET_DER() | 0x00000004 );
}

switch( which_bp )
{
case 1:
SET_CMPA( addr );
SET_ICTRL( GET_ICTRL() | 0x80080800 ); /* CTA=Equal,IW0=Match A,SIW0EN */
break;

case 2:
SET_CMPB( addr );
SET_ICTRL( GET_ICTRL() | 0x10020400 ); /* CTB=Equal,IW1=Match B,SIW1EN */
break;

case 3:
SET_CMPC( addr );
SET_ICTRL( GET_ICTRL() | 0x02008200 ); /* CTC=Equal,IW2=Match C,SIW2EN */
break;

case 4:
SET_CMPD( addr );
SET_ICTRL( GET_ICTRL() | 0x00404100 ); /* CTD=Equal,IW3=Match D,SIW3EN */
break;
}

return which_bp;
} /* bedbug860_set */


/* ======================================================================
* Disable a specific breakoint by setting the appropriate IACx register
* to zero and claring the instruction address breakpoint in DBCR0.
* ====================================================================== */

int bedbug860_clear( int which_bp )
{
/* -------------------------------------------------- */

if( which_bp < 1 || which_bp > MAX_BREAK_POINTS )
{
printf( "Invalid break point # (%d)\n", which_bp );
return -1;
}

switch( which_bp )
{
case 1:
SET_CMPA( 0 );
SET_ICTRL( GET_ICTRL() & ~0x80080800 ); /* CTA=Equal,IW0=Match A,SIW0EN */
break;

case 2:
SET_CMPB( 0 );
SET_ICTRL( GET_ICTRL() & ~0x10020400 ); /* CTB=Equal,IW1=Match B,SIW1EN */
break;

case 3:
SET_CMPC( 0 );
SET_ICTRL( GET_ICTRL() & ~0x02008200 ); /* CTC=Equal,IW2=Match C,SIW2EN */
break;

case 4:
SET_CMPD( 0 );
SET_ICTRL( GET_ICTRL() & ~0x00404100 ); /* CTD=Equal,IW3=Match D,SIW3EN */
break;
}

return 0;
} /* bedbug860_clear */


/* ====================================================================== */
#endif

+ 0
- 8
arch/powerpc/cpu/mpc8xx/config.mk View File

@@ -1,8 +0,0 @@
#
# (C) Copyright 2000-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#

PLATFORM_CPPFLAGS += -mstring -mcpu=860 -msoft-float

+ 0
- 580
arch/powerpc/cpu/mpc8xx/cpu.c View File

@@ -1,580 +0,0 @@
/*
* (C) Copyright 2000-2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/

/*
* m8xx.c
*
* CPU specific code
*
* written or collected and sometimes rewritten by
* Magnus Damm <damm@bitsmart.com>
*
* minor modifications by
* Wolfgang Denk <wd@denx.de>
*/

#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <mpc8xx.h>
#include <commproc.h>
#include <netdev.h>
#include <asm/cache.h>
#include <linux/compiler.h>
#include <asm/io.h>

#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <fdt_support.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

static char *cpu_warning = "\n " \
"*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";

#if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \
!defined(CONFIG_MPC862))

static int check_CPU (long clock, uint pvr, uint immr)
{
char *id_str =
# if defined(CONFIG_MPC855)
"PC855";
# elif defined(CONFIG_MPC860P)
"PC860P";
# else
NULL;
# endif
volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
uint k, m;
char buf[32];
char pre = 'X';
char *mid = "xx";
char *suf;

/* the highest 16 bits should be 0x0050 for a 860 */

if ((pvr >> 16) != 0x0050)
return -1;

k = (immr << 16) |
immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)];
m = 0;
suf = "";

/*
* Some boards use sockets so different CPUs can be used.
* We have to check chip version in run time.
*/
switch (k) {
case 0x00020001: pre = 'P'; break;
case 0x00030001: break;
case 0x00120003: suf = "A"; break;
case 0x00130003: suf = "A3"; break;

case 0x00200004: suf = "B"; break;

case 0x00300004: suf = "C"; break;
case 0x00310004: suf = "C1"; m = 1; break;

case 0x00200064: mid = "SR"; suf = "B"; break;
case 0x00300065: mid = "SR"; suf = "C"; break;
case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break;
case 0x05010000: suf = "D3"; m = 1; break;
case 0x05020000: suf = "D4"; m = 1; break;
/* this value is not documented anywhere */
case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
/* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
case 0x08010004: /* Rev. A.0 */
suf = "A";
/* fall through */
case 0x08000003: /* Rev. 0.3 */
pre = 'M'; m = 1;
if (id_str == NULL)
id_str =
# if defined(CONFIG_MPC859T)
"PC859T";
# else
"PC866x"; /* Unknown chip from MPC866 family */
# endif
break;
case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;
if (id_str == NULL)
id_str = "PC885"; /* 870/875/880/885 */
break;

default: suf = NULL; break;
}

if (id_str == NULL)
id_str = "PC86x"; /* Unknown 86x chip */
if (suf)
printf ("%c%s%sZPnn%s", pre, id_str, mid, suf);
else
printf ("unknown M%s (0x%08x)", id_str, k);


#if defined(CONFIG_SYS_8xx_CPUCLK_MIN) && defined(CONFIG_SYS_8xx_CPUCLK_MAX)
printf (" at %s MHz [%d.%d...%d.%d MHz]\n ",
strmhz (buf, clock),
CONFIG_SYS_8xx_CPUCLK_MIN / 1000000,
((CONFIG_SYS_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000,
CONFIG_SYS_8xx_CPUCLK_MAX / 1000000,
((CONFIG_SYS_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000
);
#else
printf (" at %s MHz: ", strmhz (buf, clock));
#endif
print_size(checkicache(), " I-Cache ");
print_size(checkdcache(), " D-Cache");

/* do we have a FEC (860T/P or 852/859/866/885)? */

immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
printf (" FEC present");
}

if (!m) {
puts (cpu_warning);
}

putc ('\n');

#ifdef DEBUG
if(clock != measure_gclk()) {
printf ("clock %ldHz != %dHz\n", clock, measure_gclk());
}
#endif

return 0;
}

#elif defined(CONFIG_MPC862)

static int check_CPU (long clock, uint pvr, uint immr)
{
volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
uint k, m;
char buf[32];
char pre = 'X';
__maybe_unused char *mid = "xx";
char *suf;

/* the highest 16 bits should be 0x0050 for a 8xx */

if ((pvr >> 16) != 0x0050)
return -1;

k = (immr << 16) |
immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)];
m = 0;

switch (k) {

/* this value is not documented anywhere */
case 0x06000000: mid = "P"; suf = "0"; break;
case 0x06010001: mid = "P"; suf = "A"; m = 1; break;
case 0x07000003: mid = "P"; suf = "B"; m = 1; break;
default: suf = NULL; break;
}

#ifndef CONFIG_MPC857
if (suf)
printf ("%cPC862%sZPnn%s", pre, mid, suf);
else
printf ("unknown MPC862 (0x%08x)", k);
#else
if (suf)
printf ("%cPC857TZPnn%s", pre, suf); /* only 857T tested right now! */
else
printf ("unknown MPC857 (0x%08x)", k);
#endif

printf(" at %s MHz: ", strmhz(buf, clock));

print_size(checkicache(), " I-Cache ");
print_size(checkdcache(), " D-Cache");

/* lets check and see if we're running on a 862T (or P?) */

immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
printf (" FEC present");
}

if (!m) {
puts (cpu_warning);
}

putc ('\n');

return 0;
}

#elif defined(CONFIG_MPC823)

static int check_CPU (long clock, uint pvr, uint immr)
{
volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
uint k, m;
char buf[32];
char *suf;

/* the highest 16 bits should be 0x0050 for a 8xx */

if ((pvr >> 16) != 0x0050)
return -1;

k = (immr << 16) |
in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]);
m = 0;

switch (k) {
/* MPC823 */
case 0x20000000: suf = "0"; break;
case 0x20010000: suf = "0.1"; break;
case 0x20020000: suf = "Z2/3"; break;
case 0x20020001: suf = "Z3"; break;
case 0x21000000: suf = "A"; break;
case 0x21010000: suf = "B"; m = 1; break;
case 0x21010001: suf = "B2"; m = 1; break;
/* MPC823E */
case 0x24010000: suf = NULL;
puts ("PPC823EZTnnB2");
m = 1;
break;
default:
suf = NULL;
printf ("unknown MPC823 (0x%08x)", k);
break;
}
if (suf)
printf ("PPC823ZTnn%s", suf);

printf(" at %s MHz: ", strmhz(buf, clock));

print_size(checkicache(), " I-Cache ");
print_size(checkdcache(), " D-Cache");

/* lets check and see if we're running on a 860T (or P?) */

immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
puts (" FEC present");
}

if (!m) {
puts (cpu_warning);
}

putc ('\n');

return 0;
}

#elif defined(CONFIG_MPC850)

static int check_CPU (long clock, uint pvr, uint immr)
{
volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
uint k, m;
char buf[32];

/* the highest 16 bits should be 0x0050 for a 8xx */

if ((pvr >> 16) != 0x0050)
return -1;

k = (immr << 16) |
immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)];
m = 0;

switch (k) {
case 0x20020001:
printf ("XPC850xxZT");
break;
case 0x21000065:
printf ("XPC850xxZTA");
break;
case 0x21010067:
printf ("XPC850xxZTB");
m = 1;
break;
case 0x21020068:
printf ("XPC850xxZTC");
m = 1;
break;
default:
printf ("unknown MPC850 (0x%08x)", k);
}
printf(" at %s MHz: ", strmhz(buf, clock));

print_size(checkicache(), " I-Cache ");
print_size(checkdcache(), " D-Cache");

/* lets check and see if we're running on a 850T (or P?) */

immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
printf (" FEC present");
}

if (!m) {
puts (cpu_warning);
}

putc ('\n');

return 0;
}
#else
#error CPU undefined
#endif
/* ------------------------------------------------------------------------- */

int checkcpu (void)
{
ulong clock = gd->cpu_clk;
uint immr = get_immr (0); /* Return full IMMR contents */
uint pvr = get_pvr ();

puts ("CPU: ");

/* 850 has PARTNUM 20 */
/* 801 has PARTNUM 10 */
return check_CPU (clock, pvr, immr);
}

/* ------------------------------------------------------------------------- */
/* L1 i-cache */
/* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
/* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */

int checkicache (void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
u32 cacheon = rd_ic_cst () & IDC_ENABLED;

#ifdef CONFIG_IP86x
u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
#else
u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
#endif
u32 m;
u32 lines = -1;

wr_ic_cst (IDC_UNALL);
wr_ic_cst (IDC_INVALL);
wr_ic_cst (IDC_DISABLE);
__asm__ volatile ("isync");

while (!((m = rd_ic_cst ()) & IDC_CERR2)) {
wr_ic_adr (k);
wr_ic_cst (IDC_LDLCK);
__asm__ volatile ("isync");

lines++;
k += 0x10; /* the number of bytes in a cacheline */
}

wr_ic_cst (IDC_UNALL);
wr_ic_cst (IDC_INVALL);

if (cacheon)
wr_ic_cst (IDC_ENABLE);
else
wr_ic_cst (IDC_DISABLE);

__asm__ volatile ("isync");

return lines << 4;
};

/* ------------------------------------------------------------------------- */
/* L1 d-cache */
/* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
/* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */
/* call with cache disabled */

int checkdcache (void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
u32 cacheon = rd_dc_cst () & IDC_ENABLED;

#ifdef CONFIG_IP86x
u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
#else
u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
#endif
u32 m;
u32 lines = -1;

wr_dc_cst (IDC_UNALL);
wr_dc_cst (IDC_INVALL);
wr_dc_cst (IDC_DISABLE);

while (!((m = rd_dc_cst ()) & IDC_CERR2)) {
wr_dc_adr (k);
wr_dc_cst (IDC_LDLCK);
lines++;
k += 0x10; /* the number of bytes in a cacheline */
}

wr_dc_cst (IDC_UNALL);
wr_dc_cst (IDC_INVALL);

if (cacheon)
wr_dc_cst (IDC_ENABLE);
else
wr_dc_cst (IDC_DISABLE);

return lines << 4;
};

/* ------------------------------------------------------------------------- */

void upmconfig (uint upm, uint * table, uint size)
{
uint i;
uint addr = 0;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;

for (i = 0; i < size; i++) {
memctl->memc_mdr = table[i]; /* (16-15) */
memctl->memc_mcr = addr | upm; /* (16-16) */
addr++;
}
}

/* ------------------------------------------------------------------------- */

int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong msr, addr;

volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;

immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */

/* Interrupts and MMU off */
__asm__ volatile ("mtspr 81, 0");
__asm__ volatile ("mfmsr %0":"=r" (msr));

msr &= ~0x1030;
__asm__ volatile ("mtmsr %0"::"r" (msr));

/*
* Trying to execute the next instruction at a non-existing address
* should cause a machine check, resulting in reset
*/
#ifdef CONFIG_SYS_RESET_ADDRESS
addr = CONFIG_SYS_RESET_ADDRESS;
#else
/*
* note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
* - sizeof (ulong) is usually a valid address. Better pick an address
* known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
* "(ulong)-1" used to be a good choice for many systems...
*/
addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
#endif
((void (*)(void)) addr) ();
return 1;
}

/* ------------------------------------------------------------------------- */

/*
* Get timebase clock frequency (like cpu_clk in Hz)
*
* See sections 14.2 and 14.6 of the User's Manual
*/
unsigned long get_tbclk (void)
{
uint immr = get_immr (0); /* Return full IMMR contents */
volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000);
ulong oscclk, factor, pll;

if (immap->im_clkrst.car_sccr & SCCR_TBS) {
return (gd->cpu_clk / 16);
}

pll = immap->im_clkrst.car_plprcr;

#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)

/*
* For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
* factor is calculated as follows:
*
* MFN
* MFI + -------
* MFD + 1
* factor = -----------------
* (PDF + 1) * 2^S
*
* For older chips, it's just MF field of PLPRCR plus one.
*/
if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
(PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
} else {
factor = PLPRCR_val(MF)+1;
}

oscclk = gd->cpu_clk / factor;

if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) {
return (oscclk / 4);
}
return (oscclk / 16);
}

/* ------------------------------------------------------------------------- */

#if defined(CONFIG_WATCHDOG)
void watchdog_reset (void)
{
int re_enable = disable_interrupts ();

reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
if (re_enable)
enable_interrupts ();
}
#endif /* CONFIG_WATCHDOG */

#if defined(CONFIG_WATCHDOG)

void reset_8xx_watchdog (volatile immap_t * immr)
{
/*
* All other boards use the MPC8xx Internal Watchdog
*/
immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */
immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */
}
#endif /* CONFIG_WATCHDOG */

/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
int cpu_eth_init(bd_t *bis)
{
#if defined(SCC_ENET) && defined(CONFIG_CMD_NET)
scc_initialize(bis);
#endif
#if defined(FEC_ENET)
fec_initialize(bis);
#endif
return 0;
}

+ 0
- 218
arch/powerpc/cpu/mpc8xx/cpu_init.c View File

@@ -1,218 +0,0 @@
/*
* (C) Copyright 2000-2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/

#include <common.h>
#include <watchdog.h>

#include <mpc8xx.h>
#include <commproc.h>

#if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS)
DECLARE_GLOBAL_DATA_PTR;
#endif

#if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \
defined(CONFIG_SYS_SMC_UCODE_PATCH)
void cpm_load_patch (volatile immap_t * immr);
#endif

/*
* Breath some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers,
* initialize the UPM's
*/
void cpu_init_f (volatile immap_t * immr)
{
volatile memctl8xx_t *memctl = &immr->im_memctl;
# ifdef CONFIG_SYS_PLPRCR
ulong mfmask;
# endif
ulong reg;

/* SYPCR - contains watchdog control (11-9) */

immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR;

#if defined(CONFIG_WATCHDOG)
reset_8xx_watchdog (immr);
#endif /* CONFIG_WATCHDOG */

/* SIUMCR - contains debug pin configuration (11-6) */
immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR;
/* initialize timebase status and control register (11-26) */
/* unlock TBSCRK */

immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR;

/* initialize the PIT (11-31) */

immr->im_sitk.sitk_piscrk = KAPWR_KEY;
immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;

/* System integration timers. Don't change EBDF! (15-27) */

immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
reg = immr->im_clkrst.car_sccr;
reg &= SCCR_MASK;
reg |= CONFIG_SYS_SCCR;
immr->im_clkrst.car_sccr = reg;

/* PLL (CPU clock) settings (15-30) */

immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;

/* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
* set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
* otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF
* field value.
*
* For newer (starting MPC866) chips PLPRCR layout is different.
*/
#ifdef CONFIG_SYS_PLPRCR
if (get_immr(0xFFFF) >= MPC8xx_NEW_CLK)
mfmask = PLPRCR_MFACT_MSK;
else
mfmask = PLPRCR_MF_MSK;

if ((CONFIG_SYS_PLPRCR & mfmask) != 0)
reg = CONFIG_SYS_PLPRCR; /* reset control bits */
else {
reg = immr->im_clkrst.car_plprcr;
reg &= mfmask; /* isolate MF-related fields */
reg |= CONFIG_SYS_PLPRCR; /* reset control bits */
}
immr->im_clkrst.car_plprcr = reg;
#endif

/*
* Memory Controller:
*/

/* perform BR0 reset that MPC850 Rev. A can't guarantee */
reg = memctl->memc_br0;
reg &= BR_PS_MSK; /* Clear everything except Port Size bits */
reg |= BR_V; /* then add just the "Bank Valid" bit */
memctl->memc_br0 = reg;

/* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
* preliminary addresses - these have to be modified later
* when FLASH size has been determined
*
* Depending on the size of the memory region defined by
* CONFIG_SYS_OR0_REMAP some boards (wide address mask) allow to map the
* CONFIG_SYS_MONITOR_BASE, while others (narrower address mask) can't
* map CONFIG_SYS_MONITOR_BASE.
*
* For example, for CONFIG_IVMS8, the CONFIG_SYS_MONITOR_BASE is
* 0xff000000, but CONFIG_SYS_OR0_REMAP's address mask is 0xfff80000.
*
* If BR0 wasn't loaded with address base 0xff000000, then BR0's
* base address remains as 0x00000000. However, the address mask
* have been narrowed to 512Kb, so CONFIG_SYS_MONITOR_BASE wasn't mapped
* into the Bank0.
*
* This is why CONFIG_IVMS8 and similar boards must load BR0 with
* CONFIG_SYS_BR0_PRELIM in advance.
*
* [Thanks to Michael Liao for this explanation.
* I owe him a free beer. - wd]
*/

#if defined(CONFIG_SYS_OR0_REMAP)
memctl->memc_or0 = CONFIG_SYS_OR0_REMAP;
#endif
#if defined(CONFIG_SYS_OR1_REMAP)
memctl->memc_or1 = CONFIG_SYS_OR1_REMAP;
#endif
#if defined(CONFIG_SYS_OR5_REMAP)
memctl->memc_or5 = CONFIG_SYS_OR5_REMAP;
#endif

/* now restrict to preliminary range */
memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;

#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
#endif

#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
#endif

#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
#endif

#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
#endif

#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
#endif

#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM;
memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM;
#endif

#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM;
memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM;
#endif

/*
* Reset CPM
*/
immr->im_cpm.cp_cpcr = CPM_CR_RST | CPM_CR_FLG;
do { /* Spin until command processed */
__asm__ ("eieio");
} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);

#ifdef CONFIG_SYS_RCCR /* must be done before cpm_load_patch() */
/* write config value */
immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR;
#endif

#if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \
defined(CONFIG_SYS_SMC_UCODE_PATCH)
cpm_load_patch (immr); /* load mpc8xx microcode patch */
#endif
}

/*
* initialize higher level parts of CPU like timers
*/
int cpu_init_r (void)
{
#if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS)
bd_t *bd = gd->bd;
volatile immap_t *immr = (volatile immap_t *) (bd->bi_immr_base);
#endif

#ifdef CONFIG_SYS_RTCSC
/* Unlock RTSC register */
immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
/* write config value */
immr->im_sit.sit_rtcsc = CONFIG_SYS_RTCSC;
#endif

#ifdef CONFIG_SYS_RMDS
/* write config value */
immr->im_cpm.cp_rmds = CONFIG_SYS_RMDS;
#endif
return (0);
}

+ 0
- 27
arch/powerpc/cpu/mpc8xx/fdt.c View File

@@ -1,27 +0,0 @@
/*
* Copyright 2008 (C) Bryan O'Donoghue
*
* Code copied & edited from Freescale mpc85xx stuff.
*
* SPDX-License-Identifier: GPL-2.0+
*/

#include <common.h>
#include <libfdt.h>
#include <fdt_support.h>

DECLARE_GLOBAL_DATA_PTR;

void ft_cpu_setup(void *blob, bd_t *bd)
{
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"timebase-frequency", get_tbclk(), 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"bus-frequency", bd->bi_busfreq, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"clock-frequency", bd->bi_intfreq, 1);
do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency",
gd->arch.brg_clk, 1);

fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}

+ 0
- 933
arch/powerpc/cpu/mpc8xx/fec.c View File

@@ -1,933 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/

#include <common.h>
#include <command.h>
#include <commproc.h>
#include <malloc.h>
#include <net.h>

#include <phy.h>

DECLARE_GLOBAL_DATA_PTR;

#undef ET_DEBUG

#if defined(CONFIG_CMD_NET) && \
(defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2))

/* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */
#if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2)
#define CONFIG_ETHER_ON_FEC1 1
#endif

/* define WANT_MII when MII support is required */
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
#define WANT_MII
#else
#undef WANT_MII
#endif

#if defined(WANT_MII)
#include <miiphy.h>

#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
#error "CONFIG_MII has to be defined!"
#endif

#endif

#if defined(CONFIG_RMII) && !defined(WANT_MII)
#error RMII support is unusable without a working PHY.
#endif

#ifdef CONFIG_SYS_DISCOVER_PHY
static int mii_discover_phy(struct eth_device *dev);
#endif

int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg);
int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
u16 value);

static struct ether_fcc_info_s
{
int ether_index;
int fecp_offset;
int phy_addr;
int actual_phy_addr;
int initialized;
}
ether_fcc_info[] = {
#if defined(CONFIG_ETHER_ON_FEC1)
{
0,
offsetof(immap_t, im_cpm.cp_fec1),
#if defined(CONFIG_FEC1_PHY)
CONFIG_FEC1_PHY,
#else
-1, /* discover */
#endif
-1,
0,

},
#endif
#if defined(CONFIG_ETHER_ON_FEC2)
{
1,
offsetof(immap_t, im_cpm.cp_fec2),
#if defined(CONFIG_FEC2_PHY)
CONFIG_FEC2_PHY,
#else
-1,
#endif
-1,
0,
},
#endif
};

/* Ethernet Transmit and Receive Buffers */
#define DBUF_LENGTH 1520

#define TX_BUF_CNT 2

#define TOUT_LOOP 100

#define PKT_MAXBUF_SIZE 1518
#define PKT_MINBUF_SIZE 64
#define PKT_MAXBLR_SIZE 1520

#ifdef __GNUC__
static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8)));
#else
#error txbuf must be aligned.
#endif

static uint rxIdx; /* index of the current RX buffer */
static uint txIdx; /* index of the current TX buffer */

/*
* FEC Ethernet Tx and Rx buffer descriptors allocated at the
* immr->udata_bd address on Dual-Port RAM
* Provide for Double Buffering
*/

typedef volatile struct CommonBufferDescriptor {
cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
} RTXBD;

static RTXBD *rtx = NULL;

static int fec_send(struct eth_device *dev, void *packet, int length);
static int fec_recv(struct eth_device* dev);
static int fec_init(struct eth_device* dev, bd_t * bd);
static void fec_halt(struct eth_device* dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
static void __mii_init(void);
#endif

int fec_initialize(bd_t *bis)
{
struct eth_device* dev;
struct ether_fcc_info_s *efis;
int i;

for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) {

dev = malloc(sizeof(*dev));
if (dev == NULL)
hang();

memset(dev, 0, sizeof(*dev));

/* for FEC1 make sure that the name of the interface is the same
as the old one for compatibility reasons */
if (i == 0) {
strcpy(dev->name, "FEC");
} else {
sprintf (dev->name, "FEC%d",
ether_fcc_info[i].ether_index + 1);
}

efis = &ether_fcc_info[i];

/*
* reset actual phy addr
*/
efis->actual_phy_addr = -1;

dev->priv = efis;
dev->init = fec_init;
dev->halt = fec_halt;
dev->send = fec_send;
dev->recv = fec_recv;

eth_register(dev);

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
int retval;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
mdiodev->read = fec8xx_miiphy_read;
mdiodev->write = fec8xx_miiphy_write;

retval = mdio_register(mdiodev);
if (retval < 0)
return retval;
#endif
}
return 1;
}

static int fec_send(struct eth_device *dev, void *packet, int length)
{
int j, rc;
struct ether_fcc_info_s *efis = dev->priv;
volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);

/* section 16.9.23.3
* Wait for ready
*/
j = 0;
while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
udelay(1);
j++;
}
if (j>=TOUT_LOOP) {
printf("TX not ready\n");
}

rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
rtx->txbd[txIdx].cbd_datlen = length;
rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
__asm__ ("eieio");

/* Activate transmit Buffer Descriptor polling */
fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */

j = 0;
while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
udelay(1);
j++;
}
if (j>=TOUT_LOOP) {
printf("TX timeout\n");
}
#ifdef ET_DEBUG
printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
__FILE__,__LINE__,__FUNCTION__,j,rtx->txbd[txIdx].cbd_sc,
(rtx->txbd[txIdx].cbd_sc & 0x003C)>>2);
#endif
/* return only status bits */;
rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);

txIdx = (txIdx + 1) % TX_BUF_CNT;

return rc;
}

static int fec_recv (struct eth_device *dev)
{
struct ether_fcc_info_s *efis = dev->priv;
volatile fec_t *fecp =
(volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
int length;

for (;;) {
/* section 16.9.23.2 */
if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
length = -1;
break; /* nothing received - leave for() loop */
}

length = rtx->rxbd[rxIdx].cbd_datlen;

if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
#ifdef ET_DEBUG
printf ("%s[%d] err: %x\n",
__FUNCTION__, __LINE__,
rtx->rxbd[rxIdx].cbd_sc);
#endif
} else {
uchar *rx = net_rx_packets[rxIdx];

length -= 4;

#if defined(CONFIG_CMD_CDP)
if ((rx[0] & 1) != 0 &&
memcmp((uchar *)rx, net_bcast_ethaddr, 6) != 0 &&
!is_cdp_packet((uchar *)rx))
rx = NULL;
#endif
/*
* Pass the packet up to the protocol layers.
*/
if (rx != NULL)
net_process_received_packet(rx, length);
}

/* Give the buffer back to the FEC. */
rtx->rxbd[rxIdx].cbd_datlen = 0;

/* wrap around buffer index when necessary */
if ((rxIdx + 1) >= PKTBUFSRX) {
rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
(BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
rxIdx = 0;
} else {
rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
rxIdx++;
}

__asm__ ("eieio");

/* Try to fill Buffer Descriptors */
fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
}

return length;
}

/**************************************************************
*
* FEC Ethernet Initialization Routine
*
*************************************************************/

#define FEC_ECNTRL_PINMUX 0x00000004
#define FEC_ECNTRL_ETHER_EN 0x00000002
#define FEC_ECNTRL_RESET 0x00000001

#define FEC_RCNTRL_BC_REJ 0x00000010
#define FEC_RCNTRL_PROM 0x00000008
#define FEC_RCNTRL_MII_MODE 0x00000004
#define FEC_RCNTRL_DRT 0x00000002
#define FEC_RCNTRL_LOOP 0x00000001

#define FEC_TCNTRL_FDEN 0x00000004
#define FEC_TCNTRL_HBC 0x00000002
#define FEC_TCNTRL_GTS 0x00000001

#define FEC_RESET_DELAY 50

#if defined(CONFIG_RMII)

static inline void fec_10Mbps(struct eth_device *dev)
{
struct ether_fcc_info_s *efis = dev->priv;
int fecidx = efis->ether_index;
uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;

if ((unsigned int)fecidx >= 2)
hang();

((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr |= mask;
}

static inline void fec_100Mbps(struct eth_device *dev)
{
struct ether_fcc_info_s *efis = dev->priv;
int fecidx = efis->ether_index;
uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;

if ((unsigned int)fecidx >= 2)
hang();

((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr &= ~mask;
}

#endif

static inline void fec_full_duplex(struct eth_device *dev)
{
struct ether_fcc_info_s *efis = dev->priv;
volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);

fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT;
fecp->fec_x_cntrl |= FEC_TCNTRL_FDEN; /* FD enable */
}

static inline void fec_half_duplex(struct eth_device *dev)
{
struct ether_fcc_info_s *efis = dev->priv;
volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);

fecp->fec_r_cntrl |= FEC_RCNTRL_DRT;
fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN; /* FD disable */
}

static void fec_pin_init(int fecidx)
{
bd_t *bd = gd->bd;
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;

/*
* Set MII speed to 2.5 MHz or slightly below.
*
* According to the MPC860T (Rev. D) Fast ethernet controller user
* manual (6.2.14),
* the MII management interface clock must be less than or equal
* to 2.5 MHz.
* This MDC frequency is equal to system clock / (2 * MII_SPEED).
* Then MII_SPEED = system_clock / 2 * 2,5 MHz.
*
* All MII configuration is done via FEC1 registers:
*/
immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;

#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
/* use MDC for MII */
immr->im_ioport.iop_pdpar |= 0x0080;
immr->im_ioport.iop_pddir &= ~0x0080;
#endif

if (fecidx == 0) {
#if defined(CONFIG_ETHER_ON_FEC1)

#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */

#if !defined(CONFIG_RMII)

immr->im_ioport.iop_papar |= 0xf830;
immr->im_ioport.iop_padir |= 0x0830;
immr->im_ioport.iop_padir &= ~0xf000;

immr->im_cpm.cp_pbpar |= 0x00001001;
immr->im_cpm.cp_pbdir &= ~0x00001001;

immr->im_ioport.iop_pcpar |= 0x000c;
immr->im_ioport.iop_pcdir &= ~0x000c;

immr->im_cpm.cp_pepar |= 0x00000003;
immr->im_cpm.cp_pedir |= 0x00000003;
immr->im_cpm.cp_peso &= ~0x00000003;

immr->im_cpm.cp_cptr &= ~0x00000100;

#else

#if !defined(CONFIG_FEC1_PHY_NORXERR)
immr->im_ioport.iop_papar |= 0x1000;
immr->im_ioport.iop_padir &= ~0x1000;
#endif
immr->im_ioport.iop_papar |= 0xe810;
immr->im_ioport.iop_padir |= 0x0810;
immr->im_ioport.iop_padir &= ~0xe000;

immr->im_cpm.cp_pbpar |= 0x00000001;
immr->im_cpm.cp_pbdir &= ~0x00000001;

immr->im_cpm.cp_cptr |= 0x00000100;
immr->im_cpm.cp_cptr &= ~0x00000050;

#endif /* !CONFIG_RMII */

#else
/*
* Configure all of port D for MII.
*/
immr->im_ioport.iop_pdpar = 0x1fff;

/*
* Bits moved from Rev. D onward
*/
if ((get_immr(0) & 0xffff) < 0x0501)
immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
else
immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
#endif

#endif /* CONFIG_ETHER_ON_FEC1 */
} else if (fecidx == 1) {

#if defined(CONFIG_ETHER_ON_FEC2)

#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */

#if !defined(CONFIG_RMII)
immr->im_cpm.cp_pepar |= 0x0003fffc;
immr->im_cpm.cp_pedir |= 0x0003fffc;
immr->im_cpm.cp_peso &= ~0x000087fc;
immr->im_cpm.cp_peso |= 0x00037800;

immr->im_cpm.cp_cptr &= ~0x00000080;
#else

#if !defined(CONFIG_FEC2_PHY_NORXERR)
immr->im_cpm.cp_pepar |= 0x00000010;
immr->im_cpm.cp_pedir |= 0x00000010;
immr->im_cpm.cp_peso &= ~0x00000010;
#endif
immr->im_cpm.cp_pepar |= 0x00039620;
immr->im_cpm.cp_pedir |= 0x00039620;
immr->im_cpm.cp_peso |= 0x00031000;
immr->im_cpm.cp_peso &= ~0x00008620;

immr->im_cpm.cp_cptr |= 0x00000080;
immr->im_cpm.cp_cptr &= ~0x00000028;
#endif /* CONFIG_RMII */

#endif /* CONFIG_MPC885_FAMILY */

#endif /* CONFIG_ETHER_ON_FEC2 */

}
}

static int fec_reset(volatile fec_t *fecp)
{
int i;

/* Whack a reset.
* A delay is required between a reset of the FEC block and
* initialization of other FEC registers because the reset takes
* some time to complete. If you don't delay, subsequent writes
* to FEC registers might get killed by the reset routine which is
* still in progress.
*/

fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
for (i = 0;
(fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
++i) {
udelay (1);
}
if (i == FEC_RESET_DELAY)
return -1;

return 0;
}

static int fec_init (struct eth_device *dev, bd_t * bd)
{
struct ether_fcc_info_s *efis = dev->priv;
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile fec_t *fecp =
(volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
int i;

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
/* the MII interface is connected to FEC1
* so for the miiphy_xxx function to work we must
* call mii_init since fec_halt messes the thing up
*/
if (efis->ether_index != 0)
__mii_init();
#endif

if (fec_reset(fecp) < 0)
printf ("FEC_RESET_DELAY timeout\n");

/* We use strictly polling mode only
*/
fecp->fec_imask = 0;

/* Clear any pending interrupt
*/
fecp->fec_ievent = 0xffc0;

/* No need to set the IVEC register */

/* Set station address
*/
#define ea dev->enetaddr
fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
fecp->fec_addr_high = (ea[4] << 8) | (ea[5]);
#undef ea

#if defined(CONFIG_CMD_CDP)
/*
* Turn on multicast address hash table
*/
fecp->fec_hash_table_high = 0xffffffff;
fecp->fec_hash_table_low = 0xffffffff;
#else
/* Clear multicast address hash table
*/
fecp->fec_hash_table_high = 0;
fecp->fec_hash_table_low = 0;
#endif

/* Set maximum receive buffer size.
*/
fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;

/* Set maximum frame length
*/