Browse Source

powerpc, 8260: remove support for mpc8260

There was for long time no activity in the 8260 area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in 8260,
so remove it.

Signed-off-by: Heiko Schocher <hs@denx.de>
tags/2020-06-01
Heiko Schocher 4 years ago
committed by Tom Rini
parent
commit
2eb48ff7a2
61 changed files with 17 additions and 11051 deletions
  1. +0
    -2
      .travis.yml
  2. +7
    -66
      README
  3. +1
    -1
      api/api_platform-powerpc.c
  4. +0
    -6
      arch/powerpc/Kconfig
  5. +0
    -20
      arch/powerpc/cpu/mpc8260/Kconfig
  6. +0
    -13
      arch/powerpc/cpu/mpc8260/Makefile
  7. +0
    -236
      arch/powerpc/cpu/mpc8260/bedbug_603e.c
  8. +0
    -174
      arch/powerpc/cpu/mpc8260/commproc.c
  9. +0
    -9
      arch/powerpc/cpu/mpc8260/config.mk
  10. +0
    -323
      arch/powerpc/cpu/mpc8260/cpu.c
  11. +0
    -272
      arch/powerpc/cpu/mpc8260/cpu_init.c
  12. +0
    -1155
      arch/powerpc/cpu/mpc8260/ether_fcc.c
  13. +0
    -367
      arch/powerpc/cpu/mpc8260/ether_scc.c
  14. +0
    -255
      arch/powerpc/cpu/mpc8260/interrupts.c
  15. +0
    -52
      arch/powerpc/cpu/mpc8260/kgdb.S
  16. +0
    -382
      arch/powerpc/cpu/mpc8260/pci.c
  17. +0
    -492
      arch/powerpc/cpu/mpc8260/serial_scc.c
  18. +0
    -461
      arch/powerpc/cpu/mpc8260/serial_smc.c
  19. +0
    -228
      arch/powerpc/cpu/mpc8260/speed.c
  20. +0
    -408
      arch/powerpc/cpu/mpc8260/spi.c
  21. +0
    -901
      arch/powerpc/cpu/mpc8260/start.S
  22. +0
    -248
      arch/powerpc/cpu/mpc8260/traps.c
  23. +0
    -74
      arch/powerpc/cpu/mpc8260/u-boot.lds
  24. +1
    -1
      arch/powerpc/cpu/mpc83xx/start.S
  25. +0
    -795
      arch/powerpc/include/asm/cpm_8260.h
  26. +0
    -604
      arch/powerpc/include/asm/immap_8260.h
  27. +0
    -168
      arch/powerpc/include/asm/iopin_8260.h
  28. +0
    -165
      arch/powerpc/include/asm/m8260_pci.h
  29. +0
    -5
      arch/powerpc/include/asm/ppc.h
  30. +0
    -3
      arch/powerpc/include/asm/processor.h
  31. +1
    -3
      arch/powerpc/include/asm/status_led.h
  32. +0
    -8
      arch/powerpc/lib/Kconfig
  33. +0
    -1
      arch/powerpc/lib/Makefile
  34. +0
    -629
      arch/powerpc/lib/immap.c
  35. +0
    -52
      arch/powerpc/lib/kgdb.c
  36. +0
    -12
      board/keymile/km82xx/Kconfig
  37. +0
    -7
      board/keymile/km82xx/MAINTAINERS
  38. +0
    -8
      board/keymile/km82xx/Makefile
  39. +0
    -463
      board/keymile/km82xx/km82xx.c
  40. +1
    -1
      cmd/bdinfo.c
  41. +0
    -7
      cmd/bedbug.c
  42. +1
    -1
      common/board_f.c
  43. +1
    -1
      common/lynxkdi.c
  44. +0
    -25
      configs/mgcoge3ne_defconfig
  45. +0
    -25
      configs/mgcoge_defconfig
  46. +0
    -10
      doc/README.idma2intr
  47. +0
    -5
      drivers/bootcount/bootcount.c
  48. +0
    -9
      drivers/i2c/soft_i2c.c
  49. +1
    -16
      drivers/pci/pci_indirect.c
  50. +0
    -9
      drivers/usb/gadget/gadget_chips.h
  51. +0
    -1
      examples/standalone/Makefile
  52. +0
    -379
      examples/standalone/mem_to_mem_idma2intr.c
  53. +1
    -1
      include/asm-generic/u-boot.h
  54. +0
    -427
      include/configs/km82xx.h
  55. +1
    -3
      include/i2c.h
  56. +0
    -903
      include/mpc8260.h
  57. +0
    -48
      include/mpc8260_irq.h
  58. +0
    -4
      include/post.h
  59. +1
    -25
      include/ppc_asm.tmpl
  60. +0
    -7
      post/drivers/memory.c
  61. +0
    -75
      scripts/config_whitelist.txt

+ 0
- 2
.travis.yml View File

@@ -200,8 +200,6 @@ matrix:
- env:
- BUILDMAN="mpc5xxx"
- env:
- BUILDMAN="mpc8260"
- env:
- BUILDMAN="mpc83xx"
- env:
- BUILDMAN="mpc85xx -x freescale"


+ 7
- 66
README View File

@@ -700,14 +700,6 @@ The following options need to be configured:
Select one of the baudrates listed in
CONFIG_SYS_BAUDRATE_TABLE, see below.

- Console Rx buffer length
With CONFIG_SYS_SMC_RXBUFLEN it is possible to define
the maximum receive buffer length for the SMC.
This option is actual only for 82xx possible.
If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE
must be defined, to setup the maximum idle timeout for
the SMC.

- Autoboot Command:
CONFIG_BOOTCOMMAND
Only needed when CONFIG_BOOTDELAY is enabled;
@@ -937,11 +929,9 @@ The following options need to be configured:
CONFIG_WATCHDOG
If this variable is defined, it enables watchdog
support for the SoC. There must be support in the SoC
specific code for a watchdog. For the 8260
CPUs, the SIU Watchdog feature is enabled in the SYPCR
register. When supported for a specific SoC is
available, then no further board specific code should
be needed to use it.
specific code for a watchdog. When supported for a
specific SoC is available, then no further board specific
code should be needed to use it.

CONFIG_HW_WATCHDOG
When using a watchdog circuitry external to the used
@@ -2108,12 +2098,6 @@ The following options need to be configured:

eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)

I2C_PORT

(Only for MPC8260 CPU). The I/O port to use (the code
assumes both bits are on the same port). Valid values
are 0..3 for ports A..D.

I2C_ACTIVE

The code necessary to make the I2C data line active
@@ -2402,7 +2386,7 @@ The following options need to be configured:

IVMS8, IVML24, SPD8xx,
HERMES, IP860, RPXlite, LWMON,
FLAGADM, TQM8260
FLAGADM

- Access to physical memory region (> 4GB)
Some basic support is provided for operations on memory not
@@ -3860,16 +3844,6 @@ but it can not erase, write this NOR flash by SRIO or PCIE interface.
set. If this value is set, it must be set to the same value as
CONFIG_ENV_SIZE.

- CONFIG_SYS_SPI_INIT_OFFSET

Defines offset to the initial SPI buffer area in DPRAM. The
area is used at an early stage (ROM part) if the environment
is configured to reside in the SPI EEPROM: We need a 520 byte
scratch DPRAM area. It is used between the two initialization
calls (spi_init_f() and spi_init_r()). A value of 0xB00 seems
to be a good choice since it makes it far enough from the
start of the data area as well as from the stack pointer.

Please note that the environment is read-only until the monitor
has been relocated to RAM and a RAM copy of the environment has been
created; also, when using EEPROM you will have to use getenv_f()
@@ -3923,13 +3897,6 @@ Low Level (hardware related) configuration options:
- CONFIG_SYS_CACHELINE_SIZE:
Cache Line Size of the CPU.

- CONFIG_SYS_DEFAULT_IMMR:
Default address of the IMMR after system reset.

Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU,
and RPXsuper) to be able to adjust the position of
the IMMR register after a reset.

- CONFIG_SYS_CCSRBAR_DEFAULT:
Default (power-on reset) physical address of CCSR on Freescale
PowerPC SOCs.
@@ -3938,9 +3905,6 @@ Low Level (hardware related) configuration options:
Virtual address of CCSR. On a 32-bit build, this is typically
the same value as CONFIG_SYS_CCSRBAR_DEFAULT.

CONFIG_SYS_DEFAULT_IMMR must also be set to this value,
for cross-platform code that uses that macro instead.

- CONFIG_SYS_CCSRBAR_PHYS:
Physical address of CCSR. CCSR can be relocated to a new
physical address, if desired. In this case, this macro should
@@ -4016,8 +3980,6 @@ Low Level (hardware related) configuration options:
sequences.

U-Boot uses the following memory types:
- MPC8260: IMMR (internal memory of the CPU)
- MPC824X: data cache
- PPC4xx: data cache

- CONFIG_SYS_GBL_DATA_OFFSET:
@@ -4069,27 +4031,6 @@ Low Level (hardware related) configuration options:
CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM:
Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)

- CONFIG_SYS_MAMR_PTA, CONFIG_SYS_MPTPR_2BK_4K, CONFIG_SYS_MPTPR_1BK_4K, CONFIG_SYS_MPTPR_2BK_8K,
CONFIG_SYS_MPTPR_1BK_8K, CONFIG_SYS_MAMR_8COL, CONFIG_SYS_MAMR_9COL:
Machine Mode Register and Memory Periodic Timer
Prescaler definitions (SDRAM timing)

- CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8260 only)
Offset of the bootmode word in DPRAM used by post
(Power On Self Tests). This definition overrides
#define'd default value in commproc.h resp.
cpm_8260.h.

- CONFIG_SYS_PCI_SLV_MEM_LOCAL, CONFIG_SYS_PCI_SLV_MEM_BUS, CONFIG_SYS_PICMR0_MASK_ATTRIB,
CONFIG_SYS_PCI_MSTR0_LOCAL, CONFIG_SYS_PCIMSK0_MASK, CONFIG_SYS_PCI_MSTR1_LOCAL,
CONFIG_SYS_PCIMSK1_MASK, CONFIG_SYS_PCI_MSTR_MEM_LOCAL, CONFIG_SYS_PCI_MSTR_MEM_BUS,
CONFIG_SYS_CPU_PCI_MEM_START, CONFIG_SYS_PCI_MSTR_MEM_SIZE, CONFIG_SYS_POCMR0_MASK_ATTRIB,
CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL, CONFIG_SYS_PCI_MSTR_MEMIO_BUS, CPU_PCI_MEMIO_START,
CONFIG_SYS_PCI_MSTR_MEMIO_SIZE, CONFIG_SYS_POCMR1_MASK_ATTRIB, CONFIG_SYS_PCI_MSTR_IO_LOCAL,
CONFIG_SYS_PCI_MSTR_IO_BUS, CONFIG_SYS_CPU_PCI_IO_START, CONFIG_SYS_PCI_MSTR_IO_SIZE,
CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only)
Overrides the default PCI memory map in arch/powerpc/cpu/mpc8260/pci.c if set.

- CONFIG_PCI_DISABLE_PCIE:
Disable PCI-Express on systems where it is supported but not
required.
@@ -5710,9 +5651,9 @@ configuration for CS0# this is a mirror of the on board Flash memory.
To be able to re-map memory U-Boot then jumps to its link address.
To be able to implement the initialization code in C, a (small!)
initial stack is set up in the internal Dual Ported RAM (in case CPUs
which provide such a feature like MPC8xx or MPC8260), or in a locked
part of the data cache. After that, U-Boot initializes the CPU core,
the caches and the SIU.
which provide such a feature like), or in a locked part of the data
cache. After that, U-Boot initializes the CPU core, the caches and
the SIU.

Next, all (potentially) available memory banks are mapped using a
preliminary mapping. For example, we put them on 512 MB boundaries


+ 1
- 1
api/api_platform-powerpc.c View File

@@ -30,7 +30,7 @@ int platform_sys_info(struct sys_info *si)
si->clk_bus = gd->bus_clk;
si->clk_cpu = gd->cpu_clk;

#if defined(CONFIG_5xx) || defined(CONFIG_MPC8260) || \
#if defined(CONFIG_5xx) || \
defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
#define bi_bar bi_immr_base
#elif defined(CONFIG_MPC5xxx)


+ 0
- 6
arch/powerpc/Kconfig View File

@@ -17,9 +17,6 @@ config 5xx
config MPC5xxx
bool "MPC5xxx"

config MPC8260
bool "MPC8260"

config MPC83xx
bool "MPC83xx"
select CREATE_ARCH_SYMLINK
@@ -48,12 +45,9 @@ config 4xx

endchoice

source "arch/powerpc/lib/Kconfig"

source "arch/powerpc/cpu/mpc512x/Kconfig"
source "arch/powerpc/cpu/mpc5xx/Kconfig"
source "arch/powerpc/cpu/mpc5xxx/Kconfig"
source "arch/powerpc/cpu/mpc8260/Kconfig"
source "arch/powerpc/cpu/mpc83xx/Kconfig"
source "arch/powerpc/cpu/mpc85xx/Kconfig"
source "arch/powerpc/cpu/mpc86xx/Kconfig"


+ 0
- 20
arch/powerpc/cpu/mpc8260/Kconfig View File

@@ -1,20 +0,0 @@
menu "mpc8260 CPU"
depends on MPC8260

config SYS_CPU
default "mpc8260"

choice
prompt "Target select"
optional

config TARGET_KM82XX
bool "Support km82xx"
imply CMD_CRAMFS
imply FS_CRAMFS

endchoice

source "board/keymile/km82xx/Kconfig"

endmenu

+ 0
- 13
arch/powerpc/cpu/mpc8260/Makefile View File

@@ -1,13 +0,0 @@
#
# (C) Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#

extra-y = start.o
obj-y = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \
interrupts.o ether_fcc.o commproc.o \
bedbug_603e.o pci.o spi.o kgdb.o

obj-$(CONFIG_ETHER_ON_SCC) += ether_scc.o

+ 0
- 236
arch/powerpc/cpu/mpc8260/bedbug_603e.c View File

@@ -1,236 +0,0 @@
/*
* Bedbug Functions specific to the MPC603e core
*/

#include <common.h>
#include <command.h>
#include <linux/ctype.h>
#include <bedbug/type.h>
#include <bedbug/bedbug.h>
#include <bedbug/regs.h>
#include <bedbug/ppc.h>

#if defined(CONFIG_CMD_BEDBUG) \
&& (defined(CONFIG_MPC824X) || defined(CONFIG_MPC8260))

#define MAX_BREAK_POINTS 1

extern CPU_DEBUG_CTX bug_ctx;

void bedbug603e_init __P((void));
void bedbug603e_do_break __P((cmd_tbl_t*,int,int,char*const[]));
void bedbug603e_break_isr __P((struct pt_regs*));
int bedbug603e_find_empty __P((void));
int bedbug603e_set __P((int,unsigned long));
int bedbug603e_clear __P((int));

/* ======================================================================
* Initialize the global bug_ctx structure for the processor. Clear all
* of the breakpoints.
* ====================================================================== */

void bedbug603e_init( void )
{
int i;
/* -------------------------------------------------- */

bug_ctx.hw_debug_enabled = 0;
bug_ctx.stopped = 0;
bug_ctx.current_bp = 0;
bug_ctx.regs = NULL;

bug_ctx.do_break = bedbug603e_do_break;
bug_ctx.break_isr = bedbug603e_break_isr;
bug_ctx.find_empty = bedbug603e_find_empty;
bug_ctx.set = bedbug603e_set;
bug_ctx.clear = bedbug603e_clear;

for( i = 1; i <= MAX_BREAK_POINTS; ++i )
(*bug_ctx.clear)( i );

puts ("BEDBUG:ready\n");
return;
} /* bedbug_init_breakpoints */


/* ======================================================================
* Set/clear/show the hardware breakpoint for the 603e. The "off"
* string will disable a specific breakpoint. The "show" string will
* display the current breakpoints. Otherwise an address will set a
* breakpoint at that address. Setting a breakpoint uses the CPU-specific
* set routine which will assign a breakpoint number.
* ====================================================================== */

void bedbug603e_do_break (cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
long addr; /* Address to break at */
int which_bp; /* Breakpoint number */
/* -------------------------------------------------- */

if (argc < 2) {
cmd_usage(cmdtp);
return;
}

/* Turn off a breakpoint */

if( strcmp( argv[ 1 ], "off" ) == 0 )
{
if( bug_ctx.hw_debug_enabled == 0 )
{
puts ( "No breakpoints enabled\n" );
return;
}

which_bp = simple_strtoul( argv[ 2 ], NULL, 10 );

if( bug_ctx.clear )
(*bug_ctx.clear)( which_bp );

printf( "Breakpoint %d removed\n", which_bp );
return;
}

/* Show a list of breakpoints */

if( strcmp( argv[ 1 ], "show" ) == 0 )
{
for( which_bp = 1; which_bp <= MAX_BREAK_POINTS; ++which_bp )
{

addr = GET_IABR();

printf( "Breakpoint [%d]: ", which_bp );
if( (addr & 0x00000002) == 0 )
puts ( "NOT SET\n" );
else
disppc( (unsigned char *)(addr & 0xFFFFFFFC), 0, 1, bedbug_puts, F_RADHEX );
}
return;
}

/* Set a breakpoint at the address */

if(!(( isdigit( argv[ 1 ][ 0 ] )) ||
(( argv[ 1 ][ 0 ] >= 'a' ) && ( argv[ 1 ][ 0 ] <= 'f' )) ||
(( argv[ 1 ][ 0 ] >= 'A' ) && ( argv[ 1 ][ 0 ] <= 'F' )))) {
cmd_usage(cmdtp);
return;
}

addr = simple_strtoul( argv[ 1 ], NULL, 16 );

if(( bug_ctx.set ) && ( which_bp = (*bug_ctx.set)( 0, addr )) > 0 )
{
printf( "Breakpoint [%d]: ", which_bp );
disppc( (unsigned char *)addr, 0, 1, bedbug_puts, F_RADHEX );
}

return;
} /* bedbug603e_do_break */


/* ======================================================================
* Handle a breakpoint. Enter a mini main loop. Stay in the loop until
* the stopped flag in the debug context is cleared.
* ====================================================================== */

void bedbug603e_break_isr( struct pt_regs *regs )
{
unsigned long addr; /* Address stopped at */
/* -------------------------------------------------- */

bug_ctx.current_bp = 1;
addr = GET_IABR() & 0xFFFFFFFC;

bedbug_main_loop( addr, regs );
return;
} /* bedbug603e_break_isr */


/* ======================================================================
* See if the hardware breakpoint is available.
* ====================================================================== */

int bedbug603e_find_empty( void )
{
/* -------------------------------------------------- */

if( (GET_IABR() && 0x00000002) == 0 )
return 1;

return 0;
} /* bedbug603e_find_empty */


/* ======================================================================
* Set a breakpoint. If 'which_bp' is zero then find an unused breakpoint
* number, otherwise reassign the given breakpoint. If hardware debugging
* is not enabled, then turn it on via the MSR and DBCR0. Set the break
* address in the IABR register.
* ====================================================================== */

int bedbug603e_set( int which_bp, unsigned long addr )
{
/* -------------------------------------------------- */

if(( addr & 0x00000003 ) != 0 )
{
puts ( "Breakpoints must be on a 32 bit boundary\n" );
return 0;
}

/* Only look if which_bp == 0, else use which_bp */
if(( bug_ctx.find_empty ) && ( !which_bp ) &&
( which_bp = (*bug_ctx.find_empty)()) == 0 )
{
puts ( "All breakpoints in use\n" );
return 0;
}

if( which_bp < 1 || which_bp > MAX_BREAK_POINTS )
{
printf( "Invalid break point # %d\n", which_bp );
return 0;
}

if( ! bug_ctx.hw_debug_enabled )
{
bug_ctx.hw_debug_enabled = 1;
}

SET_IABR( addr | 0x00000002 );

return which_bp;
} /* bedbug603e_set */


/* ======================================================================
* Disable a specific breakoint by setting the IABR register to zero.
* ====================================================================== */

int bedbug603e_clear( int which_bp )
{
/* -------------------------------------------------- */

if( which_bp < 1 || which_bp > MAX_BREAK_POINTS )
{
printf( "Invalid break point # (%d)\n", which_bp );
return -1;
}

SET_IABR( 0 );

return 0;
} /* bedbug603e_clear */


/* ====================================================================== */
#endif

+ 0
- 174
arch/powerpc/cpu/mpc8260/commproc.c View File

@@ -1,174 +0,0 @@
/*
* This file is based on "arch/powerpc/8260_io/commproc.c" - here is it's
* copyright notice:
*
* General Purpose functions for the global management of the
* 8260 Communication Processor Module.
* Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
* Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
* 2.3.99 Updates
*
* In addition to the individual control of the communication
* channels, there are a few functions that globally affect the
* communication processor.
*
* Buffer descriptors must be allocated from the dual ported memory
* space. The allocator for that is here. When the communication
* process is reset, we reclaim the memory available. There is
* currently no deallocator for this memory.
*/
#include <common.h>
#include <asm/cpm_8260.h>

DECLARE_GLOBAL_DATA_PTR;

void
m8260_cpm_reset(void)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
volatile ulong count;

/* Reclaim the DP memory for our use.
*/
gd->arch.dp_alloc_base = CPM_DATAONLY_BASE;
gd->arch.dp_alloc_top = gd->arch.dp_alloc_base + CPM_DATAONLY_SIZE;

/*
* Reset CPM
*/
immr->im_cpm.cp_cpcr = CPM_CR_RST;
count = 0;
do { /* Spin until command processed */
__asm__ __volatile__ ("eieio");
} while ((immr->im_cpm.cp_cpcr & CPM_CR_FLG) && ++count < 1000000);
}

/* Allocate some memory from the dual ported ram.
* To help protocols with object alignment restrictions, we do that
* if they ask.
*/
uint
m8260_cpm_dpalloc(uint size, uint align)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
uint retloc;
uint align_mask, off;
uint savebase;

align_mask = align - 1;
savebase = gd->arch.dp_alloc_base;

off = gd->arch.dp_alloc_base & align_mask;
if (off != 0)
gd->arch.dp_alloc_base += (align - off);

if ((off = size & align_mask) != 0)
size += align - off;

if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top) {
gd->arch.dp_alloc_base = savebase;
panic("m8260_cpm_dpalloc: ran out of dual port ram!");
}

retloc = gd->arch.dp_alloc_base;
gd->arch.dp_alloc_base += size;

memset((void *)&immr->im_dprambase[retloc], 0, size);

return(retloc);
}

/* We also own one page of host buffer space for the allocation of
* UART "fifos" and the like.
*/
uint
m8260_cpm_hostalloc(uint size, uint align)
{
/* the host might not even have RAM yet - just use dual port RAM */
return (m8260_cpm_dpalloc(size, align));
}

/* Set a baud rate generator. This needs lots of work. There are
* eight BRGs, which can be connected to the CPM channels or output
* as clocks. The BRGs are in two different block of internal
* memory mapped space.
* The baud rate clock is the system clock divided by something.
* It was set up long ago during the initial boot phase and is
* is given to us.
* Baud rate clocks are zero-based in the driver code (as that maps
* to port numbers). Documentation uses 1-based numbering.
*/
#define BRG_INT_CLK gd->arch.brg_clk
#define BRG_UART_CLK (BRG_INT_CLK / 16)

/* This function is used by UARTs, or anything else that uses a 16x
* oversampled clock.
*/
void
m8260_cpm_setbrg(uint brg, uint rate)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
volatile uint *bp;
uint cd = BRG_UART_CLK / rate;

if ((BRG_UART_CLK % rate) < (rate / 2))
cd--;
if (brg < 4) {
bp = (uint *)&immr->im_brgc1;
}
else {
bp = (uint *)&immr->im_brgc5;
brg -= 4;
}
bp += brg;
*bp = (cd << 1) | CPM_BRG_EN;
}

/* This function is used to set high speed synchronous baud rate
* clocks.
*/
void
m8260_cpm_fastbrg(uint brg, uint rate, int div16)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
volatile uint *bp;

/* This is good enough to get SMCs running.....
*/
if (brg < 4) {
bp = (uint *)&immr->im_brgc1;
}
else {
bp = (uint *)&immr->im_brgc5;
brg -= 4;
}
bp += brg;
*bp = (((((BRG_INT_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
if (div16)
*bp |= CPM_BRG_DIV16;
}

/* This function is used to set baud rate generators using an external
* clock source and 16x oversampling.
*/

void
m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
volatile uint *bp;

if (brg < 4) {
bp = (uint *)&immr->im_brgc1;
}
else {
bp = (uint *)&immr->im_brgc5;
brg -= 4;
}
bp += brg;
*bp = ((((((extclk/16)+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
if (pinsel == 0)
*bp |= CPM_BRG_EXTC_CLK3_9;
else
*bp |= CPM_BRG_EXTC_CLK5_15;
}

+ 0
- 9
arch/powerpc/cpu/mpc8260/config.mk View File

@@ -1,9 +0,0 @@
#
# (C) Copyright 2000-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#

PLATFORM_CPPFLAGS += -DCONFIG_CPM2 \
-mstring -mcpu=603e -mmultiple

+ 0
- 323
arch/powerpc/cpu/mpc8260/cpu.c View File

@@ -1,323 +0,0 @@
/*
* (C) Copyright 2000-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/

/*
* CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x
*
* written or collected and sometimes rewritten by
* Magnus Damm <damm@bitsmart.com>
*
* modified by
* Wolfgang Denk <wd@denx.de>
*
* modified for 8260 by
* Murray Jensen <Murray.Jensen@cmst.csiro.au>
*
* added 8260 masks by
* Marius Groeger <mag@sysgo.de>
*
* added HiP7 (824x/827x/8280) processors support by
* Yuli Barcohen <yuli@arabellasw.com>
*/

#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <mpc8260.h>
#include <netdev.h>
#include <asm/processor.h>
#include <asm/cpm_8260.h>

#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <fdt_support.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_GET_CPU_STR_F)
extern int get_cpu_str_f (char *buf);
#endif

int checkcpu (void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
ulong clock = gd->cpu_clk;
uint pvr = get_pvr ();
uint immr, rev, m, k;
char buf[32];
int ret;

ret = prt_8260_rsr();
if (ret)
return ret;
ret = prt_8260_clks();
if (ret)
return ret;
puts ("CPU: ");

switch (pvr) {
case PVR_8260:
case PVR_8260_HIP3:
k = 3;
break;
case PVR_8260_HIP4:
k = 4;
break;
case PVR_8260_HIP7R1:
case PVR_8260_HIP7RA:
case PVR_8260_HIP7:
k = 7;
break;
default:
return -1; /* whoops! not an MPC8260 */
}
rev = pvr & 0xff;

immr = immap->im_memctl.memc_immr;
if ((immr & IMMR_ISB_MSK) != CONFIG_SYS_IMMR)
return -1; /* whoops! someone moved the IMMR */

#if defined(CONFIG_GET_CPU_STR_F)
get_cpu_str_f (buf);
printf ("%s (HiP%d Rev %02x, Mask ", buf, k, rev);
#else
printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev);
#endif

/*
* the bottom 16 bits of the immr are the Part Number and Mask Number
* (4-34); the 16 bits at PROFF_REVNUM (0x8af0) in dual port ram is the
* RISC Microcode Revision Number (13-10).
* For the 8260, Motorola doesn't include the Microcode Revision
* in the mask.
*/
m = immr & (IMMR_PARTNUM_MSK | IMMR_MASKNUM_MSK);
k = immap->im_dprambase16[PROFF_REVNUM / sizeof(u16)];

switch (m) {
case 0x0000:
puts ("0.2 2J24M");
break;
case 0x0010:
puts ("A.0 K22A");
break;
case 0x0011:
puts ("A.1 1K22A-XC");
break;
case 0x0001:
puts ("B.1 1K23A");
break;
case 0x0021:
puts ("B.2 2K23A-XC");
break;
case 0x0023:
puts ("B.3 3K23A");
break;
case 0x0024:
puts ("C.2 6K23A");
break;
case 0x0060:
puts ("A.0(A) 2K25A");
break;
case 0x0062:
puts ("B.1 4K25A");
break;
case 0x0064:
puts ("C.0 5K25A");
break;
case 0x0A00:
puts ("0.0 0K49M");
break;
case 0x0A01:
puts ("0.1 1K49M");
break;
case 0x0A10:
puts ("1.0 1K49M");
break;
case 0x0C00:
puts ("0.0 0K50M");
break;
case 0x0C10:
puts ("1.0 1K50M");
break;
case 0x0D00:
puts ("0.0 0K50M");
break;
case 0x0D10:
puts ("1.0 1K50M");
break;
default:
printf ("unknown [immr=0x%04x,k=0x%04x]", m, k);
break;
}

printf (") at %s MHz\n", strmhz (buf, clock));

return 0;
}

/* ------------------------------------------------------------------------- */
/* configures a UPM by writing into the UPM RAM array */
/* uses bank 11 and a dummy physical address (=BRx_BA_MSK) */
/* NOTE: the physical address chosen must not overlap into any other area */
/* mapped by the memory controller because bank 11 has the lowest priority */

void upmconfig (uint upm, uint * table, uint size)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
volatile uchar *dummy = (uchar *) BRx_BA_MSK; /* set all BA bits */
uint i;

/* first set up bank 11 to reference the correct UPM at a dummy address */

memctl->memc_or11 = ORxU_AM_MSK; /* set all AM bits */

switch (upm) {

case UPMA:
memctl->memc_br11 =
((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMA |
BRx_V;
memctl->memc_mamr = MxMR_OP_WARR;
break;

case UPMB:
memctl->memc_br11 =
((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMB |
BRx_V;
memctl->memc_mbmr = MxMR_OP_WARR;
break;

case UPMC:
memctl->memc_br11 =
((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMC |
BRx_V;
memctl->memc_mcmr = MxMR_OP_WARR;
break;

default:
panic ("upmconfig passed invalid UPM number (%u)\n", upm);
break;

}

/*
* at this point, the dummy address is set up to access the selected UPM,
* the MAD pointer is zero, and the MxMR OP is set for writing to RAM
*
* now we simply load the mdr with each word and poke the dummy address.
* the MAD is incremented on each access.
*/

for (i = 0; i < size; i++) {
memctl->memc_mdr = table[i];
*dummy = 0;
}

/* now kill bank 11 */
memctl->memc_br11 = 0;
}

/* ------------------------------------------------------------------------- */

#if !defined(CONFIG_HAVE_OWN_RESET)
int
do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
ulong msr, addr;

volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;

immap->im_clkrst.car_rmr = RMR_CSRE; /* Checkstop Reset enable */

/* Interrupts and MMU off */
__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);

msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
__asm__ __volatile__ ("mtmsr %0"::"r" (msr));

/*
* Trying to execute the next instruction at a non-existing address
* should cause a machine check, resulting in reset
*/
#ifdef CONFIG_SYS_RESET_ADDRESS
addr = CONFIG_SYS_RESET_ADDRESS;
#else
/*
* note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
* - sizeof (ulong) is usually a valid address. Better pick an address
* known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
*/
addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
#endif
((void (*)(void)) addr) ();
return 1;

}
#endif /* CONFIG_HAVE_OWN_RESET */

/* ------------------------------------------------------------------------- */

/*
* Get timebase clock frequency (like cpu_clk in Hz)
*
*/
unsigned long get_tbclk (void)
{
ulong tbclk;

tbclk = (gd->bus_clk + 3L) / 4L;

return (tbclk);
}

/* ------------------------------------------------------------------------- */

#if defined(CONFIG_WATCHDOG)
void watchdog_reset (void)
{
int re_enable = disable_interrupts ();

reset_8260_watchdog ((immap_t *) CONFIG_SYS_IMMR);
if (re_enable)
enable_interrupts ();
}
#endif /* CONFIG_WATCHDOG */

/* ------------------------------------------------------------------------- */
#ifdef CONFIG_OF_BOARD_SETUP
void ft_cpu_setup (void *blob, bd_t *bd)
{
do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
"clock-frequency", bd->bi_brgfreq, 1);

do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"bus-frequency", bd->bi_busfreq, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"timebase-frequency", OF_TBCLK, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"clock-frequency", bd->bi_intfreq, 1);
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
#endif /* CONFIG_OF_BOARD_SETUP */

/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
int cpu_eth_init(bd_t *bis)
{
#if defined(CONFIG_ETHER_ON_FCC)
fec_initialize(bis);
#endif
#if defined(CONFIG_ETHER_ON_SCC)
mpc82xx_scc_enet_initialize(bis);
#endif
return 0;
}

+ 0
- 272
arch/powerpc/cpu/mpc8260/cpu_init.c View File

@@ -1,272 +0,0 @@
/*
* (C) Copyright 2000-2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/

#include <common.h>
#include <mpc8260.h>
#include <asm/cpm_8260.h>
#include <ioports.h>

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
extern unsigned long board_get_cpu_clk_f (void);
#endif

static void config_8260_ioports (volatile immap_t * immr)
{
int portnum;

for (portnum = 0; portnum < 4; portnum++) {
uint pmsk = 0,
ppar = 0,
psor = 0,
pdir = 0,
podr = 0,
pdat = 0;
iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
iop_conf_t *eiopc = iopc + 32;
uint msk = 1;

/*
* NOTE:
* index 0 refers to pin 31,
* index 31 refers to pin 0
*/
while (iopc < eiopc) {
if (iopc->conf) {
pmsk |= msk;
if (iopc->ppar)
ppar |= msk;
if (iopc->psor)
psor |= msk;
if (iopc->pdir)
pdir |= msk;
if (iopc->podr)
podr |= msk;
if (iopc->pdat)
pdat |= msk;
}

msk <<= 1;
iopc++;
}

if (pmsk != 0) {
volatile ioport_t *iop = ioport_addr (immr, portnum);
uint tpmsk = ~pmsk;

/*
* the (somewhat confused) paragraph at the
* bottom of page 35-5 warns that there might
* be "unknown behaviour" when programming
* PSORx and PDIRx, if PPARx = 1, so I
* decided this meant I had to disable the
* dedicated function first, and enable it
* last.
*/
iop->ppar &= tpmsk;
iop->psor = (iop->psor & tpmsk) | psor;
iop->podr = (iop->podr & tpmsk) | podr;
iop->pdat = (iop->pdat & tpmsk) | pdat;
iop->pdir = (iop->pdir & tpmsk) | pdir;
iop->ppar |= ppar;
}
}
}

#define SET_VAL_MASK(a, b, mask) ((a & mask) | (b & ~mask))
/*
* Breath some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers,
* initialize the UPM's
*/
void cpu_init_f (volatile immap_t * immr)
{
uint sccr;
#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
unsigned long cpu_clk;
#endif
volatile memctl8260_t *memctl = &immr->im_memctl;
extern void m8260_cpm_reset (void);

/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);

/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));

/* RSR - Reset Status Register - clear all status (5-4) */
gd->arch.reset_status = immr->im_clkrst.car_rsr;
immr->im_clkrst.car_rsr = RSR_ALLBITS;

/* RMR - Reset Mode Register - contains checkstop reset enable (5-5) */
immr->im_clkrst.car_rmr = CONFIG_SYS_RMR;

/* BCR - Bus Configuration Register (4-25) */
#if defined(CONFIG_SYS_BCR_60x) && (CONFIG_SYS_BCR_SINGLE)
if (immr->im_siu_conf.sc_bcr & BCR_EBM) {
immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_60x, 0x80000010);
} else {
immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_SINGLE, 0x80000010);
}
#else
immr->im_siu_conf.sc_bcr = CONFIG_SYS_BCR;
#endif

/* SIUMCR - contains debug pin configuration (4-31) */
#if defined(CONFIG_SYS_SIUMCR_LOW) && (CONFIG_SYS_SIUMCR_HIGH)
cpu_clk = board_get_cpu_clk_f ();
if (cpu_clk >= 100000000) {
immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_HIGH, 0x9f3cc000);
} else {
immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_LOW, 0x9f3cc000);
}
#else
immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR;
#endif

config_8260_ioports (immr);

/* initialize time counter status and control register (4-40) */
immr->im_sit.sit_tmcntsc = CONFIG_SYS_TMCNTSC;

/* initialize the PIT (4-42) */
immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;

/* System clock control register (9-8) */
sccr = immr->im_clkrst.car_sccr &
(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK);
immr->im_clkrst.car_sccr = sccr |
(CONFIG_SYS_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) );

/*
* Memory Controller:
*/

/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
* addresses - these have to be modified later when FLASH size
* has been determined
*/

#if defined(CONFIG_SYS_OR0_REMAP)
memctl->memc_or0 = CONFIG_SYS_OR0_REMAP;
#endif
#if defined(CONFIG_SYS_OR1_REMAP)
memctl->memc_or1 = CONFIG_SYS_OR1_REMAP;
#endif

/* now restrict to preliminary range */
/* the PS came from the HRCW, don't change it */
memctl->memc_br0 = SET_VAL_MASK(memctl->memc_br0 , CONFIG_SYS_BR0_PRELIM, BRx_PS_MSK);
memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;

#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
#endif

#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
#endif

#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
#endif

#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
#endif

#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
#endif

#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM;
memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM;
#endif

#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM;
memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM;
#endif

#if defined(CONFIG_SYS_BR8_PRELIM) && defined(CONFIG_SYS_OR8_PRELIM)
memctl->memc_or8 = CONFIG_SYS_OR8_PRELIM;
memctl->memc_br8 = CONFIG_SYS_BR8_PRELIM;
#endif

#if defined(CONFIG_SYS_BR9_PRELIM) && defined(CONFIG_SYS_OR9_PRELIM)
memctl->memc_or9 = CONFIG_SYS_OR9_PRELIM;
memctl->memc_br9 = CONFIG_SYS_BR9_PRELIM;
#endif

#if defined(CONFIG_SYS_BR10_PRELIM) && defined(CONFIG_SYS_OR10_PRELIM)
memctl->memc_or10 = CONFIG_SYS_OR10_PRELIM;
memctl->memc_br10 = CONFIG_SYS_BR10_PRELIM;
#endif

#if defined(CONFIG_SYS_BR11_PRELIM) && defined(CONFIG_SYS_OR11_PRELIM)
memctl->memc_or11 = CONFIG_SYS_OR11_PRELIM;
memctl->memc_br11 = CONFIG_SYS_BR11_PRELIM;
#endif

m8260_cpm_reset ();
}

/*
* initialize higher level parts of CPU like time base and timers
*/
int cpu_init_r (void)
{
volatile immap_t *immr = (immap_t *) gd->bd->bi_immr_base;

immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR;

return (0);
}

/*
* print out the reason for the reset
*/
int prt_8260_rsr (void)
{
static struct {
ulong mask;
char *desc;
} bits[] = {
{
RSR_JTRS, "JTAG"}, {
RSR_CSRS, "Check Stop"}, {
RSR_SWRS, "Software Watchdog"}, {
RSR_BMRS, "Bus Monitor"}, {
RSR_ESRS, "External Soft"}, {
RSR_EHRS, "External Hard"}
};
static int n = ARRAY_SIZE(bits);
ulong rsr = gd->arch.reset_status;
int i;
char *sep;

puts (CPU_ID_STR " Reset Status:");

sep = " ";
for (i = 0; i < n; i++)
if (rsr & bits[i].mask) {
printf ("%s%s", sep, bits[i].desc);
sep = ", ";
}

puts ("\n\n");
return (0);
}

+ 0
- 1155
arch/powerpc/cpu/mpc8260/ether_fcc.c
File diff suppressed because it is too large
View File


+ 0
- 367
arch/powerpc/cpu/mpc8260/ether_scc.c View File

@@ -1,367 +0,0 @@
/*
* MPC8260 SCC Ethernet
*
* Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
*
* (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright (c) 2001
* Advent Networks, Inc. <http://www.adventnetworks.com>
* Jay Monkman <jtm@smoothsmoothie.com>
*
* Modified so that it plays nicely when more than one ETHERNET interface
* is in use a la ether_fcc.c.
* (C) Copyright 2008
* DENX Software Engineerin GmbH
* Gary Jennejohn <garyj@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/

#include <common.h>
#include <asm/cpm_8260.h>
#include <mpc8260.h>
#include <malloc.h>
#include <net.h>
#include <command.h>
#include <config.h>

#if (CONFIG_ETHER_INDEX == 1)
# define PROFF_ENET PROFF_SCC1
# define CPM_CR_ENET_PAGE CPM_CR_SCC1_PAGE
# define CPM_CR_ENET_SBLOCK CPM_CR_SCC1_SBLOCK
# define CMXSCR_MASK (CMXSCR_SC1 |\
CMXSCR_RS1CS_MSK |\
CMXSCR_TS1CS_MSK)

#elif (CONFIG_ETHER_INDEX == 2)
# define PROFF_ENET PROFF_SCC2
# define CPM_CR_ENET_PAGE CPM_CR_SCC2_PAGE
# define CPM_CR_ENET_SBLOCK CPM_CR_SCC2_SBLOCK
# define CMXSCR_MASK (CMXSCR_SC2 |\
CMXSCR_RS2CS_MSK |\
CMXSCR_TS2CS_MSK)

#elif (CONFIG_ETHER_INDEX == 3)
# define PROFF_ENET PROFF_SCC3
# define CPM_CR_ENET_PAGE CPM_CR_SCC3_PAGE
# define CPM_CR_ENET_SBLOCK CPM_CR_SCC3_SBLOCK
# define CMXSCR_MASK (CMXSCR_SC3 |\
CMXSCR_RS3CS_MSK |\
CMXSCR_TS3CS_MSK)
#elif (CONFIG_ETHER_INDEX == 4)
# define PROFF_ENET PROFF_SCC4
# define CPM_CR_ENET_PAGE CPM_CR_SCC4_PAGE
# define CPM_CR_ENET_SBLOCK CPM_CR_SCC4_SBLOCK
# define CMXSCR_MASK (CMXSCR_SC4 |\
CMXSCR_RS4CS_MSK |\
CMXSCR_TS4CS_MSK)

#endif


/* Ethernet Transmit and Receive Buffers */
#define DBUF_LENGTH 1520

#define TX_BUF_CNT 2

#if !defined(CONFIG_SYS_SCC_TOUT_LOOP)
#define CONFIG_SYS_SCC_TOUT_LOOP 1000000
#endif

static char txbuf[TX_BUF_CNT][ DBUF_LENGTH ];

static uint rxIdx; /* index of the current RX buffer */
static uint txIdx; /* index of the current TX buffer */

/*
* SCC Ethernet Tx and Rx buffer descriptors allocated at the
* immr->udata_bd address on Dual-Port RAM
* Provide for Double Buffering
*/

typedef volatile struct CommonBufferDescriptor {
cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
} RTXBD;

static RTXBD *rtx;


static int sec_send(struct eth_device *dev, void *packet, int length)
{
int i;
int result = 0;

if (length <= 0) {
printf("scc: bad packet size: %d\n", length);
goto out;
}

for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
if (i >= CONFIG_SYS_SCC_TOUT_LOOP) {
puts ("scc: tx buffer not ready\n");
goto out;
}
}

rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
rtx->txbd[txIdx].cbd_datlen = length;
rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |
BD_ENET_TX_WRAP);

for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
if (i >= CONFIG_SYS_SCC_TOUT_LOOP) {
puts ("scc: tx error\n");
goto out;
}
}

/* return only status bits */
result = rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;

out:
return result;
}


static int sec_rx(struct eth_device *dev)
{
int length;

for (;;)
{
if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
length = -1;
break; /* nothing received - leave for() loop */
}

length = rtx->rxbd[rxIdx].cbd_datlen;

if (rtx->rxbd[rxIdx].cbd_sc & 0x003f)
{
printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
}
else
{
/* Pass the packet up to the protocol layers. */
net_process_received_packet(net_rx_packets[rxIdx], length - 4);
}


/* Give the buffer back to the SCC. */
rtx->rxbd[rxIdx].cbd_datlen = 0;

/* wrap around buffer index when necessary */
if ((rxIdx + 1) >= PKTBUFSRX) {
rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP |
BD_ENET_RX_EMPTY);
rxIdx = 0;
}
else {
rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
rxIdx++;
}
}
return length;
}

/**************************************************************
*
* SCC Ethernet Initialization Routine
*
*************************************************************/

static int sec_init(struct eth_device *dev, bd_t *bis)
{
int i;
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
scc_enet_t *pram_ptr;
uint dpaddr;
uchar ea[6];

rxIdx = 0;
txIdx = 0;

/*
* Assign static pointer to BD area.
* Avoid exhausting DPRAM, which would cause a panic.
*/
if (rtx == NULL) {
dpaddr = m8260_cpm_dpalloc(sizeof(RTXBD) + 2, 16);
rtx = (RTXBD *)&immr->im_dprambase[dpaddr];
}

/* 24.21 - (1-3): ioports have been set up already */

/* 24.21 - (4,5): connect SCC's tx and rx clocks, use NMSI for SCC */
immr->im_cpmux.cmx_uar = 0;
immr->im_cpmux.cmx_scr = ( (immr->im_cpmux.cmx_scr & ~CMXSCR_MASK) |
CONFIG_SYS_CMXSCR_VALUE);


/* 24.21 (6) write RBASE and TBASE to parameter RAM */
pram_ptr = (scc_enet_t *)&(immr->im_dprambase[PROFF_ENET]);
pram_ptr->sen_genscc.scc_rbase = (unsigned int)(&rtx->rxbd[0]);
pram_ptr->sen_genscc.scc_tbase = (unsigned int)(&rtx->txbd[0]);

pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Nrml Ops and Mot byte ordering */
pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Nrml access */

pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. package len 1520 */

pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */


/* 24.21 - (7): Write INIT RX AND TX PARAMETERS to CPCR */
while(immr->im_cpm.cp_cpcr & CPM_CR_FLG);
immr->im_cpm.cp_cpcr = mk_cr_cmd(CPM_CR_ENET_PAGE,
CPM_CR_ENET_SBLOCK,
0x0c,
CPM_CR_INIT_TRX) | CPM_CR_FLG;

/* 24.21 - (8-18): Set up parameter RAM */
pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
pram_ptr->sen_alec = 0x0; /* Align Error Counter (unused) */
pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */

pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */

pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */

pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */

pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */

pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */

eth_getenv_enetaddr("ethaddr", ea);
pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];

pram_ptr->sen_pper = 0x0; /* Persistence (unused) */

pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */

pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */

/* 24.21 - (19): Initialize RxBD */
for (i = 0; i < PKTBUFSRX; i++)
{
rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
rtx->rxbd[i].cbd_datlen = 0; /* Reset */
rtx->rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i];
}

rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;

/* 24.21 - (20): Initialize TxBD */
for (i = 0; i < TX_BUF_CNT; i++)
{
rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD |
BD_ENET_TX_LAST |
BD_ENET_TX_TC);
rtx->txbd[i].cbd_datlen = 0; /* Reset */
rtx->txbd[i].cbd_bufaddr = (uint)&txbuf[i][0];
}

rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;

/* 24.21 - (21): Write 0xffff to SCCE */
immr->im_scc[CONFIG_ETHER_INDEX-1].scc_scce = ~(0x0);

/* 24.21 - (22): Write to SCCM to enable TXE, RXF, TXB events */
immr->im_scc[CONFIG_ETHER_INDEX-1].scc_sccm = (SCCE_ENET_TXE |
SCCE_ENET_RXF |
SCCE_ENET_TXB);

/* 24.21 - (23): we don't use ethernet interrupts */

/* 24.21 - (24): Clear GSMR_H to enable normal operations */
immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrh = 0;

/* 24.21 - (25): Clear GSMR_L to enable normal operations */
immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl = (SCC_GSMRL_TCI |
SCC_GSMRL_TPL_48 |
SCC_GSMRL_TPP_10 |
SCC_GSMRL_MODE_ENET);

/* 24.21 - (26): Initialize DSR */
immr->im_scc[CONFIG_ETHER_INDEX-1].scc_dsr = 0xd555;

/* 24.21 - (27): Initialize PSMR2
*
* Settings:
* CRC = 32-Bit CCITT
* NIB = Begin searching for SFD 22 bits after RENA
* FDE = Full Duplex Enable
* BRO = Reject broadcast packets
* PROMISCOUS = Catch all packets regardless of dest. MAC adress
*/
immr->im_scc[CONFIG_ETHER_INDEX-1].scc_psmr = SCC_PSMR_ENCRC |
SCC_PSMR_NIB22 |
#if defined(CONFIG_SCC_ENET_FULL_DUPLEX)
SCC_PSMR_FDE |
#endif
#if defined(CONFIG_SCC_ENET_NO_BROADCAST)
SCC_PSMR_BRO |
#endif
#if defined(CONFIG_SCC_ENET_PROMISCOUS)
SCC_PSMR_PRO |
#endif
0;

/* 24.21 - (28): Write to GSMR_L to enable SCC */
immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR |
SCC_GSMRL_ENT);

return 0;
}


static void sec_halt(struct eth_device *dev)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl &= ~(SCC_GSMRL_ENR |
SCC_GSMRL_ENT);
}

#if 0
static void sec_restart(void)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
immr->im_cpm.cp_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR |
SCC_GSMRL_ENT);
}
#endif

int mpc82xx_scc_enet_initialize(bd_t *bis)
{
struct eth_device *dev;

dev = (struct eth_device *) malloc(sizeof *dev);
memset(dev, 0, sizeof *dev);

strcpy(dev->name, "SCC");
dev->init = sec_init;
dev->halt = sec_halt;
dev->send = sec_send;
dev->recv = sec_rx;

eth_register(dev);

return 1;
}

+ 0
- 255
arch/powerpc/cpu/mpc8260/interrupts.c View File

@@ -1,255 +0,0 @@
/*
* (C) Copyright 2000-2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*
* Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 22-Oct-00
*/

#include <common.h>
#include <command.h>
#include <mpc8260.h>
#include <mpc8260_irq.h>
#include <asm/processor.h>

DECLARE_GLOBAL_DATA_PTR;

/****************************************************************************/

struct irq_action {
interrupt_handler_t *handler;
void *arg;
ulong count;
};

static struct irq_action irq_handlers[NR_IRQS];

static ulong ppc_cached_irq_mask[NR_MASK_WORDS];

/****************************************************************************/
/* this section was ripped out of arch/powerpc/kernel/ppc8260_pic.c in the */
/* Linux/PPC 2.4.x source. There was no copyright notice in that file. */

/* The 8260 internal interrupt controller. It is usually
* the only interrupt controller.
* There are two 32-bit registers (high/low) for up to 64
* possible interrupts.
*
* Now, the fun starts.....Interrupt Numbers DO NOT MAP
* in a simple arithmetic fashion to mask or pending registers.
* That is, interrupt 4 does not map to bit position 4.
* We create two tables, indexed by vector number, to indicate
* which register to use and which bit in the register to use.
*/
static u_char irq_to_siureg[] = {
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0
};

static u_char irq_to_siubit[] = {
31, 16, 17, 18, 19, 20, 21, 22,
23, 24, 25, 26, 27, 28, 29, 30,
29, 30, 16, 17, 18, 19, 20, 21,
22, 23, 24, 25, 26, 27, 28, 31,
0, 1, 2, 3, 4, 5, 6, 7,
8, 9, 10, 11, 12, 13, 14, 15,
15, 14, 13, 12, 11, 10, 9, 8,
7, 6, 5, 4, 3, 2, 1, 0
};

static void m8260_mask_irq (unsigned int irq_nr)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
int bit, word;
volatile uint *simr;

bit = irq_to_siubit[irq_nr];
word = irq_to_siureg[irq_nr];

simr = &(immr->im_intctl.ic_simrh);
ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
simr[word] = ppc_cached_irq_mask[word];
}

static void m8260_unmask_irq (unsigned int irq_nr)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
int bit, word;
volatile uint *simr;

bit = irq_to_siubit[irq_nr];
word = irq_to_siureg[irq_nr];

simr = &(immr->im_intctl.ic_simrh);
ppc_cached_irq_mask[word] |= (1 << (31 - bit));
simr[word] = ppc_cached_irq_mask[word];
}

static void m8260_mask_and_ack (unsigned int irq_nr)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
int bit, word;
volatile uint *simr, *sipnr;

bit = irq_to_siubit[irq_nr];
word = irq_to_siureg[irq_nr];

simr = &(immr->im_intctl.ic_simrh);
sipnr = &(immr->im_intctl.ic_sipnrh);
ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
simr[word] = ppc_cached_irq_mask[word];
sipnr[word] = 1 << (31 - bit);
}

static int m8260_get_irq (struct pt_regs *regs)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
int irq;
unsigned long bits;

/* For MPC8260, read the SIVEC register and shift the bits down
* to get the irq number. */
bits = immr->im_intctl.ic_sivec;
irq = bits >> 26;
return irq;
}

/* end of code ripped out of arch/powerpc/kernel/ppc8260_pic.c */
/****************************************************************************/

int interrupt_init_cpu (unsigned *decrementer_count)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;

*decrementer_count = (gd->bus_clk / 4) / CONFIG_SYS_HZ;

/* Initialize the default interrupt mapping priorities */
immr->im_intctl.ic_sicr = 0;
immr->im_intctl.ic_siprr = 0x05309770;
immr->im_intctl.ic_scprrh = 0x05309770;
immr->im_intctl.ic_scprrl = 0x05309770;

/* disable all interrupts and clear all pending bits */
immr->im_intctl.ic_simrh = ppc_cached_irq_mask[0] = 0;
immr->im_intctl.ic_simrl = ppc_cached_irq_mask[1] = 0;
immr->im_intctl.ic_sipnrh = 0xffffffff;
immr->im_intctl.ic_sipnrl = 0xffffffff;

return 0;
}

/****************************************************************************/

/*
* Handle external interrupts
*/
void external_interrupt (struct pt_regs *regs)
{
int irq, unmask = 1;

irq = m8260_get_irq (regs);

m8260_mask_and_ack (irq);

enable_interrupts ();

if (irq_handlers[irq].handler != NULL)
(*irq_handlers[irq].handler) (irq_handlers[irq].arg);
else {
printf ("\nBogus External Interrupt IRQ %d\n", irq);
/*
* turn off the bogus interrupt, otherwise it
* might repeat forever
*/
unmask = 0;
}

if (unmask)
m8260_unmask_irq (irq);
}

/****************************************************************************/

/*
* Install and free an interrupt handler.
*/

void
irq_install_handler (int irq, interrupt_handler_t * handler, void *arg)
{
if (irq < 0 || irq >= NR_IRQS) {
printf ("irq_install_handler: bad irq number %d\n", irq);
return;
}

if (irq_handlers[irq].handler != NULL)
printf ("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
(ulong) handler, (ulong) irq_handlers[irq].handler);

irq_handlers[irq].handler = handler;
irq_handlers[irq].arg = arg;

m8260_unmask_irq (irq);
}

void irq_free_handler (int irq)
{
if (irq < 0 || irq >= NR_IRQS) {
printf ("irq_free_handler: bad irq number %d\n", irq);
return;
}

m8260_mask_irq (irq);

irq_handlers[irq].handler = NULL;
irq_handlers[irq].arg = NULL;
}

/****************************************************************************/

void timer_interrupt_cpu (struct pt_regs *regs)
{
/* nothing to do here */
return;
}

/****************************************************************************/

#if defined(CONFIG_CMD_IRQ)

/* ripped this out of ppc4xx/interrupts.c */

/*******************************************************************************
*
* irqinfo - print information about PCI devices
*
*/
void
do_irqinfo (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
{
int irq, re_enable;

re_enable = disable_interrupts ();

puts ("\nInterrupt-Information:\n"
"Nr Routine Arg Count\n");

for (irq = 0; irq < 32; irq++)
if (irq_handlers[irq].handler != NULL)
printf ("%02d %08lx %08lx %ld\n", irq,
(ulong) irq_handlers[irq].handler,
(ulong) irq_handlers[irq].arg,
irq_handlers[irq].count);

if (re_enable)
enable_interrupts ();
}

#endif

+ 0
- 52
arch/powerpc/cpu/mpc8260/kgdb.S View File

@@ -1,52 +0,0 @@
/*
* Copyright (C) 2000 Murray Jensen <Murray.Jensen@cmst.csiro.au>
*
* SPDX-License-Identifier: GPL-2.0+
*/

#include <config.h>
#include <command.h>
#include <mpc8260.h>

#include <ppc_asm.tmpl>
#include <ppc_defs.h>

#include <asm/cache.h>
#include <asm/mmu.h>

#if defined(CONFIG_CMD_KGDB)

/*
* cache flushing routines for kgdb
*/

.globl kgdb_flush_cache_all
kgdb_flush_cache_all:
mfspr r3, HID0
ori r3, r3, HID0_ICFI|HID0_DCI /* Invalidate All */
SYNC
mtspr HID0, r3
blr

.globl kgdb_flush_cache_range
kgdb_flush_cache_range:
li r5,CONFIG_SYS_CACHELINE_SIZE-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT
beqlr
mtctr r4
mr r6,r3
1: dcbst 0,r3
addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b
sync /* wait for dcbst's to get to ram */
mtctr r4
2: icbi 0,r6
addi r6,r6,CONFIG_SYS_CACHELINE_SIZE
bdnz 2b
SYNC
blr

#endif

+ 0
- 382
arch/powerpc/cpu/mpc8260/pci.c View File

@@ -1,382 +0,0 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (c) 2005 MontaVista Software, Inc.
* Vitaly Bordug <vbordug@ru.mvista.com>
* Added support for PCI bridge on MPC8272ADS
*
* SPDX-License-Identifier: GPL-2.0+
*/

#include <common.h>

#ifdef CONFIG_PCI

#include <pci.h>
#include <mpc8260.h>
#include <asm/m8260_pci.h>
#include <asm/io.h>
#ifdef CONFIG_OF_LIBFDT
#include <libfdt.h>
#include <fdt_support.h>
#endif

/*
* Local->PCI map (from CPU) controlled by
* MPC826x master window
*
* 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0
* 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1
*
* 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1)
* PCI Mem with prefetch
*
* 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2)
* PCI Mem w/o prefetch
*
* 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3)
* 32-bit PCI IO
*
* PCI->Local map (from PCI)
* MPC826x slave window controlled by
*
* 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1)
* MPC826x local memory
*/

/*
* Slave window that allows PCI masters to access MPC826x local memory.
* This window is set up using the first set of Inbound ATU registers
*/

#ifndef CONFIG_SYS_PCI_SLV_MEM_LOCAL
#define PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
#else
#define PCI_SLV_MEM_LOCAL CONFIG_SYS_PCI_SLV_MEM_LOCAL
#endif

#ifndef CONFIG_SYS_PCI_SLV_MEM_BUS
#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
#else
#define PCI_SLV_MEM_BUS CONFIG_SYS_PCI_SLV_MEM_BUS
#endif

#ifndef CONFIG_SYS_PICMR0_MASK_ATTRIB
#define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
PICMR_PREFETCH_EN)
#else
#define PICMR0_MASK_ATTRIB CONFIG_SYS_PICMR0_MASK_ATTRIB
#endif

/*
* These are the windows that allow the CPU to access PCI address space.
* All three PCI master windows, which allow the CPU to access PCI
* prefetch, non prefetch, and IO space (see below), must all fit within
* these windows.
*/

/* PCIBR0 */
#ifndef CONFIG_SYS_PCI_MSTR0_LOCAL
#define PCI_MSTR0_LOCAL 0x80000000 /* Local base */
#else
#define PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR0_LOCAL
#endif

#ifndef CONFIG_SYS_PCIMSK0_MASK
#define PCIMSK0_MASK PCIMSK_1GB /* Size of window */
#else
#define PCIMSK0_MASK CONFIG_SYS_PCIMSK0_MASK
#endif

/* PCIBR1 */
#ifndef CONFIG_SYS_PCI_MSTR1_LOCAL
#define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
#else
#define PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR1_LOCAL
#endif

#ifndef CONFIG_SYS_PCIMSK1_MASK
#define PCIMSK1_MASK PCIMSK_64MB /* Size of window */
#else
#define PCIMSK1_MASK CONFIG_SYS_PCIMSK1_MASK
#endif

/*
* Master window that allows the CPU to access PCI Memory (prefetch).
* This window will be setup with the first set of Outbound ATU registers
* in the bridge.
*/

#ifndef CONFIG_SYS_PCI_MSTR_MEM_LOCAL
#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
#else
#define PCI_MSTR_MEM_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
#endif

#ifndef CONFIG_SYS_PCI_MSTR_MEM_BUS
#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
#else
#define PCI_MSTR_MEM_BUS CONFIG_SYS_PCI_MSTR_MEM_BUS
#endif

#ifndef CONFIG_SYS_CPU_PCI_MEM_START
#define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
#else
#define CPU_PCI_MEM_START CONFIG_SYS_CPU_PCI_MEM_START
#endif

#ifndef CONFIG_SYS_PCI_MSTR_MEM_SIZE
#define PCI_MSTR_MEM_SIZE 0x10000000